Topical Workshop on Electronics for Particle Physics 2012 (TWEPP12)

Radiation hard analog to digital converter (ADC) has been designed for future high energy physics experiments. The ADC has been designed in a commercial 130 nm CMOS process and it achieves 12-bit resolution, 25 MS/s sampling speed, 15 mW power consumption and hardness to at least 1.8 Megarad(Si) of total ionizing dose (TID). 16 ADC channels will be placed on one packaged silicon chip. The readout of the Liquid Argon Calorimeter of the ATLAS detector in the planned High-Luminosity Large Hadron Collider is one possible application for this ADC.

The Insertable B-layer (IBL) is a fourth pixel layer that will be added inside the existing ATLAS pixel detector during the long LHC shutdown of 2013 and 2014. The new four layer pixel system will ensure excellent tracking, vertexing and b-tagging performance in the high luminosity pile-up conditions projected for the next LHC run. The peak luminosity is expected to reach 3·10³⁴ cm⁻²s⁻¹with an integrated luminosity over the IBL lifetime of 300 fb⁻¹ corresponding to a design lifetime fluence of 5·10¹⁵ n_eqcm⁻² and ionizing dose of 250 Mrad including safety factors. The production front-end electronics FE-I4B for the IBL has been fabricated at the end of 2011 and has been extensively characterized on diced ICs as well as at the wafer level. The production tests at the wafer level were performed during 2012. Selected results of the diced IC characterization are presented, including measurements of the on-chip voltage regulators. The IBL powering scheme, which was chosen based on these results, is described. Preliminary wafer to wafer distributions as well as yield calculations are given.

A 130 nm Transimpedance Amplifier has been developed with a 255 MHz bandwidth, 90 dBΩ transimpedance gain and a dynamic input range of 1:325 or 50 dB for a photo-diode capacitance of 0.75 pF. The equivalent integrated input noise is 160 nA @ 25°C. The gain of the voltage amplifier, used in the transimpedance amplifier (TIA), degrades less than 3% over a temperature range from -40 °C up to 125 °C. The TIA and attenuator exhibit a radiation tolerance larger than 4 MGy, as evidenced by radiation assessment.

A readout ASIC called CaloRIC, has been developed to fulfil the signal processing requirements for the Silicon-Tungsten (Si-W) electromagnetic calorimeter of the International Linear Collider (ILC). This ASIC performs the complete processing of the signal delivered by the Si-PIN diode of the detector: charge sensitive amplification, shaping, analog memorization and digitization. Measurements show a global integral non-linearity better than 0.2% for low energy particles, and limited to 2% for high energy particles. The measured Equivalent Noise Charge (ENC) is evaluated at 0.6 fC, which corresponds to 1/6 times the signal released by a Minimum Ionizing Particle (MIP). With the timing sequence of the ILC, the power consumption of the complete channel is evaluated at 43 μW using a power pulsing.

A new ASIC (CaloRIC_4ch) with four improved readout channels has been designed and is ready for manufacturing.

In the KM3NeT project [1], Cherenkov light from the muon interactions with transparent matter around the detector, is used to detect neutrinos. Photo multiplier tubes (PMT) used as photon sensor, are housed in a glass sphere (aka Optical Module) to detect single photons from the Cherenkov light. The PMT needs high operational voltage ( ∼ 1.5 kV) and is generated by a Cockroft-Walton (CW) multiplier circuit. The electronics required to control the PMT's and collect the signals is integrated in two ASIC's namely: 1) a front-end mixed signal ASIC (PROMiS) for the readout of the PMT and 2) an analog ASIC (CoCo) to generate pulses for charging the CW circuit and to control the feedback of the CW circuit. In this article, we discuss the two integrated circuits and test results of the complete setup. PROMiS amplifies the input charge, converts it to a pulse width and delivers the information via LVDS signals. These LVDS signals carry accurate information on the Time of arrival ( < 2 ns) and Time over Threshold. A PROM block provides unique identification to the chip. The chip communicates with the control electronics via an I²C bus. This unique combination of the ASIC's results in a very cost and power efficient PMT base design.

We present an electronics design for a tracking trigger for the CERN SLHC. The on detector part uses asynchronous logic so the only clock required is the LHC crossing clock. High Pt tracks are identified with a hierarchical method that finds track stubs using closely spaced pairs of detectors. Track segments (called tracklets) are then formed from pairs of stubs that are separated by 40 mm. This separation is close enough so that matching stubs is relatively easy but far enough apart so that the tracklets can be projected to another layer with mm accuracy. Matching segments in two or more layers then define a track.

Complex and challenging instrumentation projects (LHC upgrades, HL LHC, new Detector concepts) will require the adoption of ever more empowering and complex IC technologies. We clearly see that by moving only two nodes from the current 130 nm CMOS to 65 nm, substantial processing power could be embedded in the front-end system. We have designed and fabricated a prototype pixel readout chip to explore 65 nm CMOS as a potential integrated circuit technology for future particle physics applications. Not only the reported functional test results are very encouraging, but we also found that the process is fundamentally tolerant to radiation doses higher than 600 Mrad.

DEPFET is an active pixel particle detector, in which a MOSFET is integrated in each pixel, providing first amplification stage of readout electronics. Excellent signal over noise performance is provided this way. The DEPFET sensor is planned to be used as an inner pixel detector in the BELLE II experiment at electron-positron SuperKEKB collider in Japan. Gated operation of the DEPFET sensor is a unique function which allows making sensor insensitive for incoming radiation for defined time interval. Charge previously integrated in the DEPFET's internal gate is saved and integration can continue afterwards. The insensitive mode of the DEPFET is achieved by a suppressed clear mechanism, which clears newly generated charge in the detector bulk, but keeps charge previously stored in the internal gate by a capacitive coupling to the external gate electrode. The properties of the gated operation were evaluated with the laser beam. It was proven, that DEPFET can operate this way. The average charge selection in the insensitive mode is lower than 0.4% and the suppressed clear mechanism does not cause charge loss higher than 200 electrons. Such fast mechanism which can define a time window, where detector stops integration of new charge, can be used for example to select out noisy bunches injected in an accelerator.

A Front End ASIC for the readout of Silicon Photo-Multipliers is presented with the following features: wide dynamic range, high speed, multi channel, low input impedance current preamplifier, low power (7mW per channel), DC coupled input with common mode voltage control and separated timing and charge signal output. A detailed description of the SiPM modeling and parameter extraction is also included allowing the emulation of the signal generated by different commercial devices in the design simulation stage. Current prototype is the first step for a more complex mixed signal design including more channels, analog processing and digital outputs, thus reducing power consumption and increasing integration. This prototype includes basic blocks for 3 channels with: preamplifier with two separate signal paths and fast current discriminator with digital output.

For developing a scintillating-fibre beam monitor, we have designed a front-end 16-Channel readout chip (version 2) to be associated with Multi-anode photomultipliers Ma-PMTs (Hamamatsu H8500) in a 0.35 μm BiCMOS process. Each channel of the ASIC consists of one input current conveyor driving separately a current comparator for signal event detection and a charge-sensitive amplifier (CSA) for signal charge measurement. The ASIC has brought significant improvements compared to its previous version: larger input dynamic range (53 dB against 33 dB), lower power consumption (11 mW/channel instead of 22 mW/channel under a 3.3-V supply), lower noise (4 fC versus 19 fC in Equivalent input Noise Charge, or ENC) and a better phase margin for optimizing stability and speed. This dedicated chip had been used in a beam test at HIT (Heidelberg Ion-Beam Therapy Center). System testing has shown achievements of 1 mm spatial resolution (size of the scintillating fibers) and a 4 MHz count rate. The main limitation comes from the Ma-PMTs which saturates at such a frequency. The ASIC operates normally with satisfied performances.

The GigaBit Laser Driver (GBLD) is a radiation tolerant ASIC which is part of the GigaBit Transceiver (GBT) chipset. It is aimed to drive both edge emitting and VCSEL laser diodes at a data rate in excess of 5 Gb/s. The GBLD can provide a modulation current up to 24 mA and a bias current up to 43 mA. Pre- and de-emphasis functions are implemented to compensate for high external capacitive loads and asymmetric laser response. The chip is designed in a 130 nm CMOS technology and is powered by a single 2.5 V supply.

In the new Belle II detector, which is currently under construction at the SuperKEKB accelerator, a two layer pixel detector will be introduced to improve the vertex reconstruction in a ultra high luminosity environment. The pixel detector will be produced using the DEPFET technology. A new ASIC (Data Handling Processor or DHP) designed to steer the readout process, pre-process and compress the raw data has been developed. The DHP will be directly bump bonded to the balcony of the all-silicon DEPFET module. The current chip prototype has been produced in CMOS 90 nm. Its test results, including the data processing quality, the signal integrity of the gigabit transmission lines will be presented here. For the final chip, which will be produced using CMOS 65 nm, single event upset (SEU) cross sections were measured. An additional chip, containing memory blocks to be tested, was submitted and produced using this technology.

We present designs and preliminary test results of LOCld1 and LOCld4, VCSEL drivers in a commercial 0.25-μm Silicon-on-Sapphire (SoS) CMOS process for ATLAS liquid Argon calorimeter upgrade. Active shunt peaking, multiple-stage amplification and higher voltage supply are used to achieve the data rate of 8 Gbps. LOCld1 is a single channel VCSEL driver with a differential output, while LOCld4 has four channels with single-ended open-drain outputs. Both drivers have tunable modulation and peaking strength. Bias current for VCSEL is also embedded.

An ASIC named CLARO-CMOS was designed for fast photon counting with MaPMTs, MCPs and SiPMs. The prototype was realized in a .35 μm CMOS technology and has four channels, each with a fast amplifier and a discriminator. The main features of the design are the high speed of operation and the low power dissipation, below 1 mW per channel. This paper focuses on the use of the CLARO for SiPM readout. The ASIC was tested with several SiPMs of various sizes, connected to the input of the chip both directly and through a coaxial cable about one meter long. In the latter case the ASIC is still fully functional although the speed of response is affected by the cable capacitance. The threshold could be set just above the single photoelectron level, and with 1 ×1 mm² SiPMs the discrete photoelectron peaks could be well resolved.

For the future e+ e- International Linear Collider (ILC) the ASIC SPIROC (Silicon Photomultiplier Integrated Read-Out Chip) was designed to read out the Analog Hadronic Calorimeter (AHCAL) equipped with Silicon Photomultiplier (SiPM). It is an evolution of the FLC_SiPM chip designed by the OMEGA group in 2005. SPIROC2 [1] was realized in AMS SiGe 0.35 μm technology [2] and developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of read-out channels. This ASIC is a very front-end read-out chip that integrates 36 self triggered channels with variable gain to achieve charge and time measurements. The charge measurement must be performed from 1 up to 2000 photo-electrons (p.e.) corresponding to 160 fC up to 320 pC for SiPM gain 10⁶. The time measurement is performed with a coarse 12-bit counter related to the bunch crossing clock (up to 5 MHz) and a fine time ramp based on this clock (down to 200 ns) to achieve a resolution of 1 ns. An analog memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. The analog memory content (time and charge) is digitized thanks to an internal 12-bit Wilkinson ADC. The data is then stored in a 4kbytes RAM. A complex digital part is necessary to manage all these features and to transfer the data to the DAQ. SPIROC2 is the second generation of the SPIROC ASIC family designed in 2008 by the OMEGA group. A very similar version (SPIROC2c) was submitted in February 2012 to improve the noise performance and also to integrate a new TDC (Time to Digital Converter) structure. This paper describes SPIROC2 and SPIROC2c ASICs and illustrates the main characteristics thank to a series of measurements.

A 48 × 64 pixels prototype CMOS pixel sensor (CPS) integrated with 4-bit column-level, self triggered ADCs for the outer layers of the ILD vertex detector (VTX) was developed and fabricated in a 0.35 μm CMOS process with a pixel pitch of 35 μm. The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation. The ADCs accommodating the pixel read out in a rolling shutter mode complete the conversion by performing a multi-bit/step approximation. The design was optimised for power saving at sampling frequency. The prototype sensor is currently at the stage of being started testing and evaluation. So what is described is based on post simulation results rather than test data. This 4-bit ADC dissipates, at a 3-V supply and 6.25-MS/s sampling rate, 486 μW in its inactive mode, which is by far the most frequent. This value rises to 714 μW in case of the active mode. Its footprint amounts to 35 × 545 μm².

The SPACIROC ASIC is designed for the JEM-EUSO observatory onboard of the International Space Station (ISS). The main goal of JEM-EUSO is to observe Extensive Air Shower (EAS) produced in the atmosphere by the passage of the high energetic extraterrestrial particles above a few 10¹⁹ eV. A low-power, rad-hard ASIC is proposed for reading out the 64-channel Multi-Anode Photomultipliers which are going to equip the detection surface of JEM-EUSO. The two main features of this ASIC are the photon counting mode for each input and the charge-to-time (Q-to-T) conversion for the multiplexed channels. In the photon counting mode, the 100% triggering efficiency is achieved for 50 fC input charges. For the Q-to-T converter, the ASIC requires a minimum input of 2 pC. In order to comply with the strict power budget available from the ISS, the ASIC is needed to dissipate less than 1 mW/channel. The design of SPACIROC and the test results are presented in this paper.

A monolithic active pixel sensor for charged particle tracking has been developed within the frame of a research and development project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology). TRAPPISTe aims to study the feasibility of developing a monolithic pixel sensor with SOI technology. TRAPPISTe-2 is the second prototype in this series and was fabricated with an OKI 0.20μm fully depleted (FD-SOI) CMOS process. This device contains test transistors and amplifiers, as well as two pixel matrices with integrated 3-transistor and amplifier readout electronics. The results presented are based on the first electrical measurements performed on the test structures and laser measurements on the pixel matrices.

The design of an 8-channel phase-aligner which is part of the GBTX chip for the LHC upgrade program is presented. The circuit is able to align the phases of up to 8 serial data streams to the GBTX transmitter clock so that the data can be merged, serialized and transmitted to the counting room. The bit rate is programmable at 80, 160 or 320Mbit/s. Data jitter up to ±3·T_bit/8 can be tolerated without jeopardizing the error-free data reception. The phase-aligner has been designed as a radiation-hard circuit in a 130nm CMOS technology and consumes only 3.5mW at a supply voltage of 1.5V.

The paper describes the design of a floating gate MOS sensor embedded in a readout CMOS element, used as a radiation monitor. A maximum sensitivity of 1 mV/rad is estimated within an absorbed dose range from 1 to 10 krad. The paper shows in particular the design of a microelectronic circuit that includes the floating gate sensor, an oscillator, a modulator, a transmitter and an integrated antenna. A prototype of the circuit has recently been simulated, fabricated and tested exploiting a commercial 180 nm, 4 metal CMOS technology. Some simulation results are presented along with a measurement of the readout circuit response to an input voltage swing. Given the small estimated area of the complete chip prototype, that is less than 1 mm², the chip fits a large variety of applications, from spot radiation monitoring systems in medicine to punctual measurements or radiation level in High-Energy Physics experiments.

A PLL (ePLL) is presented that is intended to be used as a frequency multiplier. The ePLL accepts 40, 80, 160 or 320MHz as a reference and generates clocks at the same frequencies, regardless of the input clock. Moreover, the outputs are available with a phase resolution of 90° for the 40, 80 and 160MHz output and 22.5° for the 320MHz output. The radiation-hard design, integrated in a 130nm CMOS technology, is able to operate at a supply voltage between 1.2V and 1.5V.

A Front End ASIC for the readout of Silicon Photo-Multipliers is presented with the following features: wide dynamic range, high speed, multi channel, low input impedance current preamplifier, low power (7mW per channel), DC coupled input with common mode voltage control and separated timing and charge signal output. A detailed description of the SiPM modeling and parameter extraction is also included allowing the emulation of the signal generated by different commercial devices in the design simulation stage. Current prototype is the first step for a more complex mixed signal design including more channels, analog processing and digital outputs, thus reducing power consumption and increasing integration. This prototype includes basic blocks for 3 channels with: preamplifier with two separate signal paths and fast current discriminator with digital output.

The Micro Vertex Detector (MVD) is the innermost tracking detector of the ANDA (antiProton Annihilation at Darmstadt) experiment at the upcoming FAIR (Facility for Antiproton and Ion Research) facility in Darmstadt. The detector consists of four barrel and six disk layers of silicon pixel and strip sensors to obtain precise tracking of charged particles. For the development of a front-end ASIC a flexible and powerful readout system was designed to test different ASIC prototypes. We will present the upgrade of the FPGA-based Jülich Digital Readout System and measurements of the recent MVD pixel front-end prototype ToPix3. Tests of the implementation of the radiation hard GBT transfer protocol are also shown.

One of the most important aspects of particle identification experiments is the digitisation of time, amplitude and charge data from detectors. These conversions are mostly undertaken with Application Specific Integrated Circuits (ASICs). However, recent developments in Field Programmable Gate Array (FPGA) technology allow us to use commercial electronic components for the required Front-End Electronics (FEE) and to do the digitisation in the FPGA. It is possible to do Time-of-Flight (ToF), Time-over-Threshold (ToT), amplitude and charge measurements with converters implemented in FPGA. We call this principle come & kiss: use COmplex ComMErcial Elements & Keep ItSmall and Simple.

A digitization scheme of sub-microampere current using a commercial comparator with adjustable hysteresis and FPGA-based Wave Union TDC has been tested. The comparator plus a few passive components forms a current controlled oscillator and the input current is sent into the hysteresis control pin. The input current is converted into the transition times of the oscillations, which are digitized with a Wave Union TDC in FPGA and the variation of the transition times reflects the variation of the input current. Preliminary tests show that input charges < 25 fC can be measured at > 50 M samples/s without a preamplifier.

The GANDALF 6U-VME64x/VXS module has been developed to cope with a variety of readout tasks in nuclear physics experiments and is operated at the COMPASS-II experiment at CERN. Based on this module, a 128-channel Time-to-Digital Converter with a time resolution of 93 ps has been implemented successfully in a Xilinx Virtex-5 FPGA using a shifted clock sampling algorithm. Beyond that, the design was extended by adding scaler channels for simultaneous rate measurements.

The Insertable B-layer project is planned for the upgrade of the ATLAS experiment at LHC. A silicon layer will be inserted into the existing Pixel Detector together with new electronics. The readout off-detector system is implemented with a Back-Of-Crate module implementing I/O functionality and a Readout-Driver card (ROD) for data processing. The ROD hosts the electronics devoted to control operations implemented both with a back-compatible solution (using a Digital Signal Processor) and with a PowerPC embedded into an FPGA. In this document major firmware and software achievements concerning the PowerPC implementation, tested on ROD prototypes, will be reported.

For the coming upgrade pixel detector of the ATLAS experiment at the Large Hadron Collider a redesign of the current data readout is necessary. To communicate with the additional 448 front-end chips assembled in the Insertable B-Layer (IBL) new FPGA based readout cards consisting of a Back of Crate card (BOC) and a Read Out Driver (ROD) have been developed. This paper describes the firmware and hardware development of the new BOC prototype. Firmware tests, like electrical and optical loopback and communication tests with the new IBL front-end modules and the ROD will also be presented.

In the context of upgraded read-out systems for the Liquid-Argon Calorimeters of the ATLAS detector, modified front-end, back-end and trigger electronics are foreseen for operation in the high-luminosity phase of the LHC. Accuracy and efficiency of the energy measurement and reliability of pile-up suppression are substantial when processing the detector raw-data in real-time. Several digital filter algorithms are investigated for their performance to extract energies from incoming detector signals and for the needs of the future trigger system. The implementation of fast, resource economizing, parameter driven filter algorithms in a modern Virtex FPGA is presented.

The Gigabit Link Interface Board (GLIB) project is an FPGA-based platform for users of high-speed optical links in high energy physics experiments. The major hardware component of the platform is the GLIB Advanced Mezzanine Card (AMC). Additionally to the AMC, auxiliary components are developed that enhance GLIB platform's I/O bandwidth and compatibility with legacy and future triggering and/or data acquisition interfaces. This article focuses on the development of the auxiliary components that together with the GLIB AMC offer a complete solution for beam/irradiation tests of detector modules and evaluation of optical links.

The Versatile Transceiver is a part of the Versatile Link project, which is developing optical link architectures and components for future HL-LHC experiments. While having considerable size and weight constraints, Versatile Transceivers must work under severe environmental conditions. One such environmental parameter is the temperature: the operating temperature range is specified to be from -30 to +60°C. In this contribution we present the results of the temperature characterization of the VTRx transmitter and receiver. Several transmitter candidates from three different manufacturers have been characterized: multi-mode Vertical Cavity Surface-Emitting Lasers and a single-mode Edge-Emitter Laser. Also both single- and multi-mode receivers have been tested.

Detectors involved in the upgrade programme of the LHC will need high-speed optical links to transfer readout and control data. The link front-end will be based on a radiation tolerant opto-electronic module, the Versatile Transceiver (VTRx), developed under the Versatile Link project. In this contribution we present a test system and protocol to be used to verify the compliance of the VTRx modules to the specifications, and a Versatile Link demonstrator based on the VTRx and the Gigabit Link Interface Board. Finally, we introduce the Small Footprint VTRx which is being designed for the CMS Tracker upgrade.

We summarize the results obtained in a series of radiation tests of candidate laser and photodiode components for use in the Versatile Transceiver (VTRx), the front-end component of the Versatile Link. We have carried out radiation testing at a full spectrum of sources (neutrons, pions, gammas) and can now compare the results and show that the range of components that meet the radiation tolerance requirements is rather large. In addition, devices have been operated in a high magnetic field to qualify them for use in (HL-) LHC detectors.

The upgrade of the Drift Tube system of the CMS experiment foresee the relocation of the electronics actually sitting on the racks beside the magnet from the cavern to the counting room. It is thus required to convert the signals from electrical to optical, for a total number of 3500 channels that run at up to 480 Mb/s. A Copper to Optical Fiber board is currently under design. The board is divided into a mother board, which hosts the slow control system based on Field Programmable Gate Array, and four mezzanine cards, each with 8 conversion channels. A prototype of the mezzanine board has been designed and tested under irradiation.

Optical links will be an integral part of future LHC experiments at various scales from coupled sensors to off-detector communication. We are investigating CW lasers and light modulators as an alternative to VCSELs. Light modulators are small, use less power, have high bandwidth, are reliable, have low bit error rates and are very rad-hard. We present the quality of the links at 10Gbps and the results of radiation hardness measurements for the modulators built based on LiNbO₃, InP, and Si. Also we present results on modulator-based free space data links, steered by MEMS mirrors and optical feedback paths for the control loop.

Particle detectors in High Energy Physics experiments contain various types of mixed-signal integrated circuits and demand data rates of multiple Gigabits per second per chip and several Terabits per second for the whole detector. Optical transmission by external modulation of a continuous wave laser is a possible solution to solve the problem of high data rates. The detectors have to operate in a high radiation environment and particles passing through the circuits alter the properties of the circuits giving rise to performance issues. In this paper, we investigate the radiation hardness performance of Indium Phosphide (InP) based Mach-Zehnder modulators (MZM). The modulator circuit has been irradiated with a 24 GeV/c proton beam at CERN up to various fluences. The irradiated samples have been characterized and compared against measurements of non-irradiated devices. Also, a design of an optical integrated circuit using the Generic Integration philosophy is presented.

In this paper we want to demonstrate that an optical physical medium is compatible with the second generation of PCI Express. The benefit introduced by the optical decoupling of a PCI Express endpoint is twofold: it allows for a geographical detachment of the device and it remains compliant with the usual PCI accesses to the legacy I/O and memory spaces. We propose two boards that can bridge the PCI Express protocol over optical fiber. The first is a simple optical translator while the second is a more robust switch developed for connecting up to four devices to a single host. Such adapters are already working in the control and data acquisition system of a particle detector at CERN and hence they had been qualified for radiation hardness. The positive outcomes of the radiation tests of four types of off-the-shelf transceivers are finally reported.

CMS DT electronics upgrade involves laying down 3500 optical links from the CMS experimental cavern to the service cavern, whose lengths must be matched to minimize skew, so that the present upstream electronics can be reused at an initial stage. In order to assess the cables' compliance, a high resolution and cost-effective system has been developed to measure the length uniformity of these fibres. Transit-time oscillation method has been implemented with matched MTP 12-channel fibre optic transmitter and receiver and a Spartan-6 FPGA. After proper corrections and averaging, millimetre-range accuracy has been achieved.

Today vertically integrated circuits, (a.k.a. 3D integrated circuits) is a popular topic in many trade journals. The many advantages of these circuits have been described such as higher speed due to shorter trace lenghts, the ability to reduce cross talk by placing analog and digital circuits on different levels, higher circuit density without the going to smaller feature sizes, lower interconnect capacitance leading to lower power, reduced chip size, and different processing for the various layers to optimize performance. There are some added advantages specifically for MAPS (Monolithic Active Pixel Sensors) in High Energy Physics: four side buttable pixel arrays, 100% diode fill factor, the ability to move PMOS transistors out of the diode sensing layer, and a increase in channel density. Fermilab began investigating 3D circuits in 2006. Many different bonding processes have been described for fabricating 3D circuits [1]. Fermilab has used three different processes to fabricate several circuits for specific applications in High Energy Physics and X-ray imaging. This paper covers some of the early 3D work at Fermilab and then moves to more recent activities. The major processes we have used are discussed and some of the problems encountered are described. An overview of pertinent 3D circuit designs is presented along with test results thus far.

The upgrade of the CMS tracker at the HL-LHC requires the design of new front-end modules to cope with the increased luminosity and to implement L1 trigger functionality. The new modules under development are based on high density hybrid circuits with new flip-chip front-end ASIC, and are wire bonded to strip sensors and connected to a service board for the data transmission. The suitability of different substrate technologies considered for the design of the hybrids is discussed, aiming for a cost effective and reliable manufacturability of the CMS tracker modules.

The goal of this project is to examine the feasibility of data transmission up to ∼ 5 Gbit/s on a short ( ∼ 60 cm) low mass flex cable, for the readout of the upgraded vertex detector (VELO) of the LHCb experiment. They will be in a vacuum and very high radiation environment and also partly in the particle acceptance. For the full system 1600 readout links will be required. A set of single-ended and differential (edge-coupled) striplines, with a variety of line parameters have been prototyped using a material specifically tailored for this type of application (Dupont Pyralux AP-plus polyimide). To reduce mass, the total thickness of the cable is kept to 0.7 mm. We will present measurements of the characteristic impedance, insertion and return loss, obtained both from time and frequency domain, as well as a comparison with simulations and expectations. Also the effectiveness of grounded guard traces and the use of ground via holes to reduce crosstalk will be reported. From the measurements we were also able to extract the material properties such as the dielectric constant and loss factor up to several GHz. The measurements were done with a Vector Network Analyzer (VNA), TDR/TDT Digital Sampling Oscilloscope, serial PRBS generator and analyzer for eye diagram and CAD tools such as Agilent ADS and ANSYS HFSS simulators.

The Belle II silicon vertex detector will consist of four layers of double-sided silicon strip detectors, arranged in ladders. Each sensor will be read out individually by utilizing the Origami chip-on-sensor concept, where the APV25 chips are placed on flexible circuits, glued on top of the sensors. Beside a best compromise between low material budget and sufficient SNR, this concept allows efficient CO₂ cooling of the readout chips by a single, thin cooling pipe per ladder. Recently, we assembled a module consisting of two consecutive 6'' double-sided silicon strip detectors, both read out by Origami flexes. Such a compound of Origami modules is required for the ladders of the outer Belle II SVD layers. Consequently, it is intended to verify the scalability of the assembly procedure, the performance of combined Origami flexes as well as the efficiency of the CO₂ cooling system for a higher number of APV25 chips.

At the Large Hadron Collider (LHC) at CERN, the CMS experiment's Level 1 Trigger system for the endcap Cathode Strip Chambers (CSC) has 180 optical links to transmit Level 1 trigger primitives from 60 peripheral crates to the CSC Track Finder (CSCTF) which reconstructs muon candidates. Currently there is a limit of 3 trigger primitives per crate serving a cluster of 9 chambers. With the anticipated LHC luminosity increase up to 10³⁵ cm⁻²s⁻¹ at full energy of 7 TeV/beam the Muon Port Card (MPC), which transmits the primitives, the receiver in the CSCTF (Sector Processor) and the optical transmission system itself need to be upgraded. At the same time it is very desirable to preserve all the old optical links intact for compatibility with the present Track Finder during transition period. We present here the results of our efforts in the past two years to upgrade the MPC board, including the hardware developments, data transmission tests and latency measurements.

The CMS electromagnetic calorimeter (ECAL) comprises 75848 scintillating lead tungstate crystals. 61200 crystals are contained in the ECAL Barrel section and are read out by avalanche photodiode (APD) with internal gain of about 50. This gain is achieved with a high voltage (HV) of about 400 Volts. The gain stability requirement implies a supply voltage stable to within 0.01%. We describe our experience with the installed Barrel HV power supply system, which has been used for data taking since 2008.

We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including sensitivity to Single Event Upset. We also present our reliability analysis. Production of 2400 new bricks for the detector is currently in progress, and we present preliminary results from the production checkout.

The CMS pixel detector was designed for a nominal instantaneous LHC luminosity of 1⋅10³⁴ cm⁻²s⁻¹. During Phase-1 of the LHC upgrade, the instantaneous luminosity will be increased to about twice this value. To preserve the excellent performance of the pixel detector despite the increase in particle rates and track densities, the CMS Collaboration foresees the exchange of its pixel detector in the shutdown 2016/2017. The new pixel detector will be improved in many respects, and will comprise twice the number of readout channels. A powering scheme based on DC-DC conversion will be adopted, which will enable the provision of the required power with the present cable plant.

The powering scheme of the CMS pixel detector will be described, and the performance of prototype DC-DC buck converters will be presented, including power efficiency, system tests with DC-DC converters and pixel modules, thermal management, reliability at low temperature, and studies of potential frequency locking between DC-DC converters.

The precision requirements of the vertex detector at CLIC impose strong limitations on the mass of such a detector ( < 0.2% of a radiation length, X_o, per layer). To achieve such a low mass, ultra-thin hybrid pixel detectors are foreseen, while the mass for cooling and services will be reduced by implementing a power-pulsing scheme that takes advantage of the low duty cycle of the accelerator. The principal aim is to achieve significant power reduction without compromising the power integrity supplied to the front-end electronics. A power-pulsing scheme is proposed for the analog electronics and its electrical features are discussed on the basis of measurements.

Improving calorimetry by usage of the particle-flow algorithm requires to record the details of the shower development. Therefore a high granularity analogue readout hadron calorimeter (AHCAL) with small sensors and with electronics handling the enormous amount of channels, ≈ 40 000/m³, is required. Homogeneity is maintained by avoiding cooling tubes in the active volume and only cooling at the service end. For this concept low power consumption per channel, 40 μW, is essential. Future linear e+e⁻− collider designs, ILC or CLIC, foresee duty cycles for the bunch delivery. At ILC bunch trains of 1 ms duration are followed by long breaks of 200 ms. Power cycling the front end electronics with the train structure can reduce power consumption by a factor 100. However for a full scale CALICE-AHCAL switched currents reach magnitudes of kilo-amperes. This paper describes the design chain from front end PCB's through to external power supplies. By simulations a concept is developed, in which effects of electromagnetic interferences are kept small and localized. The goal is to keep current loops small, to limit the switched current to the region near the switched consumer and to allow only small frequency currents to spread out further into the system. By that analogue performance can be kept high and parasitic couplings to the surrounding metal structures and other sub-detectors will be minimized. Measurements with existing prototypes support the validity of the simulations.

In March 2012 the high voltage system of the silicon-sensor-based CMS Preshower detector underwent a significant upgrade. In order to increase the granularity of the bias distribution lines, the number of power supplies was doubled and fully configurable distribution boards were developed and installed. These new boards provide much improved flexibility in the powering, necessary to cope with the expected evolution of the 4288 silicon sensors with radiation damage. They also provide measurement of the ∼ 2200 bias-voltage lines that go to the detector, enabling fast identification/diagnosis of any anomalous currents and providing detailed knowledge of the sensor current evolution over time.

The power distribution systems considered for the ATLAS Inner Tracker Upgrade include linear voltage regulators on the front-end chips. In the paper we present two designs: a classical voltage regulator based on an NMOS transistor as the pass element, and an LDO voltage regulator employing a PMOS device. Both prototype regulators have been implemented in the 130 nm CMOS process and are foreseen to be integrated in the ABC130 front-end chip. In the paper the designs as well as the pre- and post-radiation test results for both prototypes are presented and discussed.

This paper describes a new portable test bench for the TileCal sub-detector of the ATLAS experiment at CERN. The system is used for the certification and quality checks of the front-end electronics drawers. It is designed to be an easily upgradable version of the current 10-year-old system, able to evaluate the new technologies planned for the upgrade as well as provide new functionality to the present system. It will be used during the long shutdown of the LHC in 2013-14 and during future maintenance periods.

The article addresses production test development effort of the ATLAS FE-I4 integrated circuit. This particular production test targets manufacturing faults in the ICs and has been taken as a supplementary approach, besides standard functional test, to further decrease the risk of potential application failures. The Design-for-Test structures inside the digital part of the chip, together with the specially devised top-level simulations enabled straightforward test development and debug in the production test environment. The production test itself has been commissioned to the external test company, with the supervision of the FE-I4 team at the test floor.

In the years around 2020 an upgrade of the LHC to the HL-LHC is scheduled, which will increase the accelerators luminosity by a factor of 10. In the context of this upgrade, the inner detector of the ATLAS experiment will be replaced entirely including the pixel detector. This new pixel detector requires a specific control system which complies with the strict requirements in terms of radiation hardness, material budget and space for the electronics in the ATLAS experiment. The University of Wuppertal is developing a concept for a DCS (Detector Control System) network consisting of two kinds of ASICs. The first ASIC is the DCS Chip which is located on the pixel detector, very close to the interaction point. The second ASIC is the DCS Controller which is controlling 4x4 DCS Chips from the outer regions of ATLAS via differential data lines. Both ASICs are manufactured in 130 nm deep sub micron technology. We present results from measurements from new prototypes of components for the DCS network.

With the forthcoming High Luminosity LHC accelerator upgrade, the CMS Endcap Muon system will require new electronics to handle the increased data rate while maintaining high data collection efficiency. Maintaining trigger efficiency for pseudorapidity above 2.1 requires deployment of higher performance electronics already in 2013. With the increased luminosity, the new electronics will be exposed to substantial radiation levels requiring higher tolerance of the components to radiation. We report on the progress in developing and building the new system and the results of radiation tolerance testing of the commercial components used in the system.

The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.

Field Programmable Gate Arrays (FPGAs) are increasingly being used as a key component of digital systems because of their in-field reprogrammability, low non-recurring engineering costs (NRE), and relatively short design cycle. Recently, there has been great interest in using FPGAs within spacecraft. FPGAs, like all semiconductor devices, are susceptible to the effects of radiation. There is an active research community investigating the effects of radiation on FPGAs and developing methods to mitigate against these effects. There has been significant progress over the last decade in the understanding and developing FPGA technology that is resistant to the effects of radiation. The success of FPGAs within spacecraft suggests that FPGAs may be used in particle physics experiments where radiation levels are considerable higher than the conventional terrestrial earth environment. This paper will summarize the effects of radiation on FPGAs, methods to mitigate against these effects, provide a case study of a successful FPGA system operating in space, and discuss the issues that will affect the use of FPGAs within particle physics experiments.

Several Research and Development activities are ongoing at European Space Agency [1] to secure the supply of key electronic parts for current and future space avionics systems. Analogously to astro-particle and high-energy physics, the space missions radiation environment drives the radiation hardness requirements, which limits availability of suitable electronic components. In particular for the future ESA flagship Jupiter science mission, the necessary processing, reliability, mass, power performance requirements are difficult to meet with current components and systems with sufficient radiation tolerance margins. Improved radiation characterisation and modelling of the Jupiter radiation environment as well as operational radiation monitoring during the mission will be key in ensuring adequate margins for the operation of electronic components.

Single Event Upsets (SEUs) are a major concern for the TPC Readout Control Unit (RCU) of the ALICE experiment. A SEU is defined as a radiation related bit-flip in a memory cell, and a SEU in the onboard SRAM based FPGA of the RCU may lead to corrupted data or, even worse, a system malfunction. The latter situation will affect the operation of the ALICE detector since it causes a premature end of data taking. Active partial reconfiguration is utilized in a dedicated reconfiguration solution on the RCU, and this makes it possible to implement fault injection. Fault injection means inserting bit flips in the configuration memory of the FPGA in a controlled laboratory environment. This paper presents the results of the fault injection study and shows how this result can be combined with SEU measurements to estimate the functional failure rate as a function of luminosity.

The Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is the world's most powerful particle collider. The LHC has several thousand magnets, both warm and super-conducting, which are supplied with current by power converters. Each converter is controlled by a purpose-built electronic module called a Function Generator Controller (FGC). The FGC allows remote control of the power converter and forms the central part of a closed-loop control system where the power converter voltage is set, based on the converter output current and magnet-circuit characteristics. Some power converters and FGCs are located in areas which are exposed to beam-induced radiation. There are numerous radiation induced effects, some of which lead to a loss of control of the power converter, having a direct impact upon the accelerator's availability. Following the first long shut down (LS1), the LHC will be able to run with higher intensity beams and higher beam energy. This is expected to lead to significantly increased radiation induced effects in materials close to the accelerator, including the FGC. Recent radiation tests indicate that the current FGC would not be sufficiently reliable. A so-called FGClite is being designed to work reliably in the radiation environment in the post-LS1 era. This paper outlines the concepts of power converter controls for machines such as the LHC, introduces the risks related to radiation and a radiation tolerant project flow. The FGClite is then described, with its key concepts and challenges: aiming for high reliability in a radiation field.

A hybrid readout system is being developed for installation in one module of the ATLAS scintillating Tile Calorimeter (TileCal) during the long LHC shutdown in 2013/2014. The hybrid combines a fully functional demonstrator of the full-digital system planned for installation in 2022 with circuitry to maintain compatibility with the existing system. This is the report on a second generation prototype link and controller board connecting the on- and off-detector electronics. The main logic component within this board is a XILINX Kintex-7 FPGA connected to an 12 ×5 Gbps SNAP12 opto transmitter and a 4 ×10 Gbps QSFP+ connector, for off-detector communication. One of the latter two will be chosen for the final design.

We describe the observation and mitigation of anomalous, large signals, observed in the barrel part of the CMS Electromagnetic Calorimeter during proton collisions at LHC. Laboratory and beam tests, as well as simulations, have been used to understand their origin. They are ascribed to direct energy deposition by particles in the avalanche photodiodes used for light readout. A reprogramming of the front-end electronics has allowed a majority of these anomalous signals to be identified and rejected at the first (hardware) trigger level with minimum impact on physics performance. Further rejection is performed in the high-level software trigger and offline analyses.

Developed within RD51 Collaboration for the Development of Micro-Pattern Gas Detectors Technologies, the Scalable Readout System (SRS) is intended as a general purpose multi-channel readout solution for a wide range of detector types and detector complexities. The scalable architecture, achieved using multi-Gbps point-to-point links with no buses involved, allows the user to tailor the system size to his needs. The modular topology enables the integration of different front-end ASICs, giving the user the possibility to use the most appropriate front-end for his purpose or to build a heterogeneous experimental apparatus which integrates different front-ends into the same DAQ system. Current applications include LHC upgrade activities, geophysics or homeland security applications as well as detector R&D. The system architecture, development and running experience will be presented, together with future prospects, ATCA implementation options and application possibilities.

The Beam Instrumentation Group (BI) is responsible for designing, building and maintaining the instrumen ts that allow observation of the particle beams and the measurement of related parameters for all CERN accelerators and transfer lines. This contribution is aimed to give an overview of the ongoing electronic developments within the beam instrumentation group both to improve the performances and ease the maintenance of instrumentation in the existing machines and to meet the requirements of future accelerators. Details on some of the challenges and proposed technical solutions will be presented.

The Beam Instrumentation Group (BI) is responsible for designing, building and maintaining the instrumen ts that allow observation of the particle beams and the measurement of related parameters for all CERN accelerators and transfer lines. This contribution is aimed to give an overview of the ongoing electronic developments within the beam instrumentation group both to improve the performances and ease the maintenance of instrumentation in the existing machines and to meet the requirements of future accelerators. Details on some of the challenges and proposed technical solutions will be presented.

Resistive Plate Chambers (RPCs) are widely used in high energy physics for both tracking and triggering purposes. They have good time resolution and with finely segmented readout can also give a spatial resolution of better than 1 mm. RPCs can be produced cost-effectively on large scales, are of rugged build, and have excellent detection efficiency for charged particles. Our group has successfully built a Muon Scattering Tomography (MST) prototype, using 12 RPCs to obtain tracking information of muons going through a target volume of ∼ 50 cm × 50 cm × 70 cm, reconstructing both the incoming and outgoing muon tracks. We describe a readout system for fine-pitch RPCs using MAROC3 readout chips capable of scaling to a large system.

Ultrahigh-energy neutrinos with energies in excess of 100 PeV from the GZK effect will be studied using a new detector at the South Pole called the Askaryan Radio Array (ARA). The radiofrequency emission which occurs when these particles interact in the glacial ice is detected by an array of antennas spread out over an enormous area, over 100 km² and embedded in the ice at depths of 200 m to increase sensitivity. Signals from the antennas are digitized by specialized electronics and must be time synchronized with accuracies of order 50 ps or less for event reconstruction to function properly. A system has been proposed which digitizes the impulse waveforms in situ in the ice and sends the data to the surface using high-speed serial links. This requires distribution of a low-jitter clock to each hole but has substantial advantages in cost and power which drive our development effort to realize this technology. Last year we implemented a first version of a long distance clock synchronization system using electrical signaling over CAT5. This year we have updated our solution to optical fiber using high speed transceiver blocks in Spartan 6 FPGAs. The master clock is embedded into the data stream and distributed to the various holes where a phase-locked derivative is recovered. In this way, we have implemented a 1.25 Gbps data link over a bi-directional communication system fulfilling the requirements of the project. This note describes our efforts on the latter solution: technical details as well as methods of maintaining fixed phase difference between two clocks after power cycle and reset.

The Silicon Vertex Detector of the future Belle II experiment at KEK (Japan) will consist of 6'' double-sided strip sensors. Those are read out by APV25 chips (originally developed for CMS) which are powered by DC/DC converters with low voltages tied to the sensor bias potentials. The signals are transmitted by cable links of about 12 meters. In the back-end, the data are digitized and processed by FADC modules with powerful FPGAs, which are also capable of precisely measuring the hit time of each particle in order to discard off-time background.

Virtually all Data Acquisition Systems (DAQ) for nuclear and particle physics experiments use a large number of Field Programmable Gate Arrays (FPGAs) for data transport and more complex tasks as pattern recognition and data reduction. All these FPGAs in a large system have to share a common state like a trigger number or an epoch counter to keep the system synchronized for a consistent event/epoch building. Additionally, the collected data has to be transported with high bandwidth, optionally via the ubiquitous Ethernet protocol. Furthermore, the FPGAs' internal states and configuration memories have to be accessed for control and monitoring purposes.

Another requirement for a modern DAQ-network is the fault-tolerance for intermittent data errors in the form of automatic retransmission of faulty data. As FPGAs suffer from Single Event Effects when exposed to ionizing particles, the system has to deal with failing FPGAs. The TrbNet protocol was developed taking all these requirements into account. Three virtual channels are merged on one physical medium: The trigger/epoch information is transported with the highest priority. The data channel is second in the priority order, while the control channel is the last. Combined with a small frame size of 80 bit this guarantees a low latency data transport: A system with 100 front-ends can be built with a one-way latency of 2.2 us.

The TrbNet-protocol was implemented in each of the 550 FPGAs of the HADES upgrade project and has been successfully used during the Au+Au campaign in April 2012. With 2⋅10⁶/s Au-ions and 3% interaction ratio the accepted trigger rate is 10 kHz while data is written to storage with 150 MBytes/s. Errors are reliably mitigated via the implemented retransmission of packets and auto-shut-down of individual links. TrbNet was also used for full monitoring of the FEE status. The network stack is written in VHDL and was successfully deployed on various Lattice and Xilinx devices. The TrbNet is also used in other experiments, like systems for detector and electronics development for PANDA and CBM at FAIR. As a platform for such set-ups, e.g. for high-channel time measurement with 15 ps resolution, a generic FPGA platform (TRB3) has been developed.

The LHCb Silicon Tracker is part of the main tracking system of the LHCb detector at the LHC. It measures very precisely the particle trajectories coming from the interaction point in the region of high occupancies around the beam axis. It covers the full acceptance angle in front of the dipole magnet in the Tracker Turicensis station and the innermost part around the beam axis in the three Inner Tracker stations downstream of the magnet. The Silicon Tracker covers a sensitive area of 12 m² using silicon micro-strip sensors with very long readout strips. We report on running experience for the experiment. Focussing on electronic and hardware issues we describe some of the lessons learned and pitfalls encountered after three years of successful operation.

Silicon photomultpiliers are robust, low voltage sensors capable of measuring low light levels. They are well suited for use in a cosmic ray detector using scintillator embedded with wavelength shifting fibre, designed for lab based and high altitude cosmic ray experiments. The development of such a detector, using an ARM Cortex M3 microcontroller based data acquisition system is discussed.

The readout architecture for the silicon pixel detector of the PANDA MVD (Micro Vertex Detector) is presented. The pixel detector has to provide timing, position and energy information on a event-driven base, since no trigger signal is foreseen. The readout system is based on a custom ASIC, named ToPiX, directly connected to the GBT (GigaBit Transceiver) optical transceiver. A reduced size prototype with most of the main functionalities has been designed and tested. The ASIC has been bonded to a sensor based on the epitaxial technology and tested on a beam test. TID (Total Ionizing Dose) tests on the ToPiX prototype have been performed.

The upgraded LHCb readout system aims at a trigger-free readout of the entire detector at the bunch-crossing rate. This implies a major architectural change for the readout system that must capture the data at 40 MHz instead of 1 MHz. One of the key components of this upgrade system is the readout board. The LHCb collaboration has chosen to evaluate the ATCA architecture as form-factor for the readout board. The readout system architecture relies on a unique board able to satisfy all the requirements for data transmission, timing and fast control as well as experiment control system. A generic ATCA carrier board has been developped. It is equipped with four dense AMC mezzanines able to interface a total of 144 bidirectional optical links at up to 10 Gbits/s. This board embeds 4 high end Stratix V GX devices for data processing and a programmable set of commutation functions allowing to reconfigure the connectivity of the system in a flexible way. The overall architecture will be presented and how the cards map over each functionality. First results and measurements will be described in particular those related to the use of new highly integrated optical devices. At last we will present the incremental development methodology used in this project.

The modern market offers low cost high performance FPGA integrated circuits equipped with dozens of multi gigabit serial links making them ideal devices for data transmission and data sorting applications. Therefore we have designed the new DAQ system that would perform the detector readout and event building in a custom made FPGA based hardware. The software part will provide the control and monitoring function. Currently, the prototypes of the new FPGA card are being tested and the control and monitoring software is being prepared for the tests with the real hardware.

In high energy physics experiments, the electronics located near the interaction region are prone to soft errors as a result of radiation coming from the collisions. Depending on the type of error, the scope of its impact on data collection can range from being hardly noticeable to being completely debilitating. In this paper, we define the mechanism used by the Compact Muon Solenoid (CMS) experiment to pause the data collection machine in order to allow subsystems to recover from soft errors. An attractive feature of this mechanism is that it is general enough to facilitate the recovery from any well-defined error, not only those caused by radiation. We show the effectiveness of this method to maximize the data collection efficiency of CMS.

The ANDA experiment at the future FAIR facility will study annihilation reactions of antiprotons. The Micro-Vertex-Detector (MVD) as part of the tracking system will permit precise tracking and detection of secondary vertices. It is made of silicon pixel detectors and double-sided silicon strip detectors. The unique data acquisition concept without a central trigger poses a challenge to all sub-detectors. Developments for the MVD strip detector cover the evaluation of prototype sensors as well as the readout chain, ranging from the front-end for the trigger-less readout over the Module Data Concentrator ASIC to the off-detector electronics.

Experiments at high pulse rate Free Electron Laser (FEL) facilities require new cameras capable of acquiring 2D images at high rates, handling large signal dynamic ranges and resolving images from individual pulses. The Adaptive Gain Integrated Pixel Detector (AGIPD) will operated with pulse rates and separations of 27000/s and 220 ns, respectively at European XFEL. Si-sensors, ASICs, PCBs, and FPGA logic are developed for a 1 Mega-pixel camera with 200 μm square pixels with per-pulse occupancies  ⩽ 10⁴. Data from 3520 images/s will be transferred with 80 Gbits/s to a DAQ-system. The electronics have been adapted for use in other synchrotron light source detectors.

The NA62 experiment [1] will measure the BR(K⁺→π⁺ν) to within about 10%. To reject the dominant background from final state photons, the large-angle vetoes (LAVs) must detect particles with better than 1 ns time resolution and 10% energy resolution over a very large energy range. A low threshold, large dynamic range, Time-over-threshold based solution has been developed for the LAV front end electronics. Our custom 32 channel 9U board uses a pair of low threshold discriminators for each channel to produce LVDS logic signals. The achieved time resolution obtained in laboratory, coupled to an HPTDC based readout board, is ∼ 150 ps.

The clock and control (CC) system for the EuXFEL megapixel detectors was presented in TWEPP 2011. It consists of a multipurpose MTCA.4 AMC card with an FPGA and a custom designed Rear Transition Module (RTM). This paper presents the experiences with the system since its first prototype and the development of the final hardware. Experiences with the hardware included the tests performed to evaluate the system functionality such as Front End Electronics (FEE) communication and the performance metrics such as the FEE clock jitter. The final version of the CC hardware along with the associated firmware are also presented.

Precision sound velocity measurements can simultaneously determine binary gas composition and flow. We have developed an analyzer with custom electronics, currently in use in the ATLAS inner detector, with numerous potential applications. The instrument has demonstrated ∼ 0.3% mixture precision for C₃F₈/C₂F₆ mixtures and < 10⁻⁴ resolution for N₂/C₃F₈ mixtures. Moderate and high flow versions of the instrument have demonstrated flow resolutions of ± 2% of full scale for flows up to 250 l min⁻¹, and ± 1.9% of full scale for linear flow velocities up to 15 m s⁻¹; the latter flow approaching that expected in the vapour return of the thermosiphon fluorocarbon coolant recirculator being built for the ATLAS silicon tracker.

The LHC Bunch Clock is one of the most important accelerator signals delivered to the experiments. Being directly derived from the Radio Frequency driving the beams in the accelerator by a simple division of its frequency by a factor of 10, the Bunch Clock signal represents the frequency at which the bunches are crossing each other at each experiment. It is thus used to synchronize all the electronics systems in charge of event detection. Its frequency is around 40.079 MHz, but varies with beam parameters (energy, particle type, etc) by a few hundreds of Hz. The present paper discusses the quality of this Bunch Clock signal in terms of jitter. It is in particular compared to typical requirements of electronic components of the LHC detectors and put in perspective with the intrinsic jitter of the beam itself, to which this signal is related.

Solar Orbiter is an ESA mission to study the heliosphere in proximity to the Sun, scheduled for launch in January 2017. It carries a suite of ten instruments for comprehensive remote-sensing and in-situ measurements.

The Spectrometer Telescope for Imaging X-Rays (STIX), one of the remote sensing instruments, images X-rays between 4 and 150keV using an Fourier technique. The angular resolution is 7 arcsec and the spectral resolution 1keV full-width-half-maximum at 6keV. X-ray detection uses pixelized Cadmium Telluride crystals provided by the Paul Scherrer Institute. The crystals are bonded to read-out hybrids developed by CEA Saclay, called Caliste-SO, incorporating a low-noise, low-power analog front-end ASIC IDeF-X HD. The crystals are cooled to -20°C to obtain very low leakage currents of less than 60pA per pixel, the prerequisite for obtaining the required spectral resolution.

This article briefly describes the mission goals and then details the front-end electronics design and main challenges, resulting in part from the allocation limit in mass of 7kg and in power of 4W. Emphasis is placed on the design influence of the cooling requirement within the warm environment of a mission approaching the Sun to within the orbit of Mercury. The design for the long-term in-flight energy calibration is also explained.

The TrainBuilder is an Advanced Telecom ATCA data acquisition board being developed at the STFC Rutherford Appleton Laboratory to provide readout for the large 2D Mega-pixel detectors under construction for the European-XFEL in Hamburg. Each ATCA board can process ∼ 8 GBytes/sec of raw detector data. The TrainBuilder system merges up to 5,120 partial detector images per second using FPGAs with DDR2 data buffers and an analogue crosspoint switch architecture. The TrainBuilder links operate with 10 Gigabit Ethernet protocols implemented in FPGA logic. The first TrainBuilder demonstrator boards were manufactured in Q1/2012.

MicroBooNE experiment will use a ∼ 100 ton Liquid Argon (LAr) Time Projection Chamber (TPC) detector, presently under construction, to observe interactions of neutrinos from the on-axis Booster Neutrino Beam and off-axis NuMI Beam at Fermi National Accelerator Laboratory. The experiment will address the low energy excess observed by the MiniBooNE experiment, measure low energy neutrino cross sections, and serve as the necessary next step in a phased program towards massive Liquid Argon TPC detectors. An overview of the front end readout architecture of the MicroBooNE experiment will be presented. The design, prototypes and the production electronics system, comprised of cold CMOS electronics, warm interface electronics and TPC digitizing electronics will be described in some detail. The results of extensive tests on the noise versus temperature and of the uniformity of response will be presented.

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire readout architecture will be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. In this paper, we describe the architecture, functionalities and a first hardware implementation of a new fast Readout Control system for the LHCb upgrade, which will be entirely based on FPGAs and bi-directional links. We also outline the real-time implementations of the new Readout Control system, together with solutions on how to handle the synchronous distribution of timing and synchronous information to the complex upgraded LHCb readout architecture. One section will also be dedicated to the control and usage of the newly developed CERN GBT chipset to transmit fast and slow control commands to the upgraded LHCb Front-End electronics. At the end, we outline the plans for the deployment of the system in the global LHCb upgrade readout architecture.

The NA62 experiment at the CERN SPS aims to measure the Branching Ratio of the very rare kaon decay K⁺→π⁺ν collecting O(100) events with a 10% background in two years of data taking. To reject the K⁺→π⁺π⁰ background the NA48 liquid krypton calorimeter will be used in the 1-10 mrad angular region. The status of the Liquid Krypton Electromagnetic Calorimeter Level 0 Trigger is presented.

In 2009 COMPASS performed a short measurement of neutral Primakoff reactions, characterised by highly energetic photons in one of the two electromagnetic calorimeters. A digital trigger was implemented in the existing readout electronics which calculates the energy released in the central region of the calorimeter. In 2012 a long measurement of these processes has been performed. In order to extend the kinematic range to lower energetic photons the trigger system has been upgraded in a way to be more selective to specific physics channels. The new ADC firmware preserves hit information and provides it to newly developed backplane trigger modules. There hits from all three thousand channels are processed and the trigger decision is made.

The calorimeter trigger synchronization of the Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider (LHC) uses a synchronization method implemented in the synchronization and link board (SLB). These boards allow the synchronization of electromagnetic and hadronic trigger primitives at the LHC frequency (40.08 MHz) and its transmission to the Regional Calorimeter Trigger. The upgrade of the Calorimeter Trigger system dictates the use of input optical links at a rate of 4.8 Gb/s. In this paper we present the design options and technological choices for the optical part of new optical Synchronization and Link Boards (oSLB).

As the LHC increases luminosity and energy, it will become increasingly difficult to select interesting physics events and remain within the readout bandwidth limitations. An upgrade to the CMS Calorimeter Trigger implementing more complex algorithms is proposed. It utilizes AMC cards with Xilinx FPGAs running in microTCA crate with card interconnections via crate backplanes and optical links operating at up to 10 Gbps. Prototype cards with Virtex-6 and Virtex-7 FPGAs have been built and software frameworks for operation and monitoring developed. The physics goals, hardware architectures, and software will be described in this talk. More details can be found in a separate poster at this conference.

The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors as well as other sources and makes the final Level-1 Accept (L1A) decision. Due to the increasing luminosity of the LHC and the growing demands of physics and monitoring placed on the ATLAS Level-1 trigger system, the current CTP has reached its design limits. Therefore and in order to provide some margin for future operation, the CTP will be upgraded during the LHC shutdown of 2013/14.

Modern experiments at hadron colliders search for extremely rare processes hidden in a very large background. As the experiment complexity and the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. The FastTracker (FTK) processor for the ATLAS experiment offers extremely powerful, very compact and low power consumption processing units for the future, which is essential for increased efficiency and purity in the Level 2 trigger selection through the intensive use of tracking. Pattern recognition is performed with Associative Memories (AM). The AMBFTK board and the AMchip04 integrated circuit have been designed specifically for this purpose. We report on the preliminary test results of the first prototypes of the AMBFTK board and of the AMchip04.

The ATLAS Level-1 Trigger requires several upgrades to maintain physics sensitivity as the LHC luminosity is raised. One of the most challenging is the electron/photon trigger, with a major development planned for installation in 2018. New on-detector electronics will be installed to digitize electromagnetic calorimetry signals, providing trigger access to shower profile information. The trigger processing will be ATCA-based, with each multi-FPGA module processing  ∼ 1 Tbit/s of calorimeter digits within the current 2.5 microseconds Level-1 Trigger latency limit. This paper will address the system architecture and design, and give the status of a current technology demonstrator.

The ALICE experiment at the LHC is equipped with an electromagnetic calorimeter (EMCal) designed to enhance its capabilities for jet, photon and electron measurement. In addition, the EMCal enables triggering on jets and photons with a centrality dependent energy threshold. After its commissioning in 2010, the EMCal Level 1 (L1) trigger was officially approved for physics data taking in 2011. After describing the L1 hardware and trigger algorithms, the commissioning and the first year of running experience, both in proton and heavy ion beams, are reviewed. Additionally, the upgrades to the original L1 trigger design are detailed.

Around 2021 the Large Hadron Collider (LHC) will be upgraded to provide instantaneous luminosities of 5×10³⁴cm²s⁻¹, leading to excessive rates from the ATLAS Level-1 trigger. We describe a double buffer front-end architecture for the ATLAS tracker upgrade which should enable tracking information to be used in the Level-1 event selection. This will allow Level-1 rates to be controlled whilst preserving high efficiency for single lepton triggers at relatively low transverse momentum thresholds of ∼ 25 GeV, enabling ATLAS to remain sensitive to physics at the electroweak scale. In particular, a potential hardware solution for the communication between the upgraded barrel silicon strip detectors and the external processing within this architecture will be described, and discrete event simulations used to demonstrate that this fits within the tight latency constraints.

The ATLAS Level-1 Calorimeter Trigger is a pipelined system to identify high-p_T objects and to build energy sums within a fixed latency of ∼ 2 μs. It consists of a PreProcessor, which conditions and digitises analogue calorimeter signals, and two object-finding processors. The PreProcessor's tasks are implemented on a Multi-Chip Module, holding ADCs, time-adjustment and digital processing ASICs, and LVDS serialisers. A pin-compatible substitute, based on today's technology, like dual-channel ADCs and FPGAs, has been built to improve the BCID and pedestal subtraction algorithms. Test results with the first prototype are presented.

Test results are presented for two AMC cards, the ``CTP6'' and ``MP7''. The two cards take different approaches to connectivity: the CTP-6 has fully-populated backplane connectivity and a 396 Gbps asymmetric, optical interface, whilst the MP7 instead favours a 1.4 Tbps, symmetric, all-optical interface. The challenges of designing the MP7 card necessitated the development of several test cards; the results of which are presented.

Starting in 2014, the LHC will collide bunches of protons at up to 14 TeV with an instantaneous luminosity increasing above the design value of 1 × 10³⁴ cm⁻²s⁻¹. Even though the resulting higher event rate will challenge the existing ATLAS data acquisition system, the trigger rate can be reduced by selecting channels based on their expected decay topology and thus reducing background. This will be achieved by introducing a new FPGA based module in the Level-1 Trigger: the Topological Processor (L1Topo). With L1Topo it will be possible to concentrate detailed information from the entire calorimeters and the muon detector into a single module. L1Topo will receive a total aggregate bandwidth of ≈ 1 Tb/s. High density optical I/O and state of the art FPGAs with embedded multi-Gb/s transceivers will be required. For a typical algorithm, the topology data will be processed in less than 100 ns. This paper focuses on the design of the first L1Topo prototype and results from a full-size, full-function demonstrator module. Implementation details of a topological algorithm and latency figures are presented.

NEXT-DEMO is a prototype of NEXT (Neutrino Experiment with Xenon TPC), an experiment to search for neutrino-less double beta decay using a 100 kg radio-pure, 90 % enriched (136Xe isotope) high-pressure gaseous xenon TPC with electroluminescence readout. The detector is based on a PMT plane for energy measurements and a SiPM tracking plane for topological event filtering. The experiment will be located in the Canfranc Underground Laboratory in Spain.

Front-end electronics, trigger and data-acquisition systems (DAQ) have been built. The DAQ is an implementation of the Scalable Readout System (RD51 collaboration) based on FPGA. Our approach for trigger is to have a distributed and reconfigurable system in the DAQ itself. Moreover, the trigger allows on-line triggering based on the detection of primary or secondary scintillation light, or a combination of both, that arrives to the PMT plane.