An FPGA based Topological Processor prototype for the ATLAS Level-1 Trigger upgrade

Starting in 2014, the LHC will collide bunches of protons at up to 14 TeV with an instantaneous luminosity increasing above the design value of 1 × 10³⁴ cm⁻²s⁻¹. Even though the resulting higher event rate will challenge the existing ATLAS data acquisition system, the trigger rate can be reduced by selecting channels based on their expected decay topology and thus reducing background. This will be achieved by introducing a new FPGA based module in the Level-1 Trigger: the Topological Processor (L1Topo). With L1Topo it will be possible to concentrate detailed information from the entire calorimeters and the muon detector into a single module. L1Topo will receive a total aggregate bandwidth of ≈ 1 Tb/s. High density optical I/O and state of the art FPGAs with embedded multi-Gb/s transceivers will be required. For a typical algorithm, the topology data will be processed in less than 100 ns. This paper focuses on the design of the first L1Topo prototype and results from a full-size, full-function demonstrator module. Implementation details of a topological algorithm and latency figures are presented.