Nitrogen-doped β-Ga₂O₃ vertical transistors with a threshold voltage of ≥1.3 V and a channel mobility of 100 cm² V⁻¹ s⁻¹

Beta gallium oxide (β-Ga₂O₃) has become of interest in the power electronics industry especially for electric vehicles, power conditioning, power distribution, and switching applications, owing to its large bandgap (4.5–4.9 eV), high theoretical breakdown electric field (6–8 MV cm⁻¹), and Baliga's figure of merit (FOM) exceeding that of Si, SiC and GaN. To date, fabrication of devices using β-Ga₂O₃ has been actively carried out. ^1–9) Lateral transistors with a breakdown voltage of up to 8 kV ¹⁰⁾ and vertical transistors with a breakdown voltage of 2.6 kV ¹¹⁾ and 5 kV ¹²⁾ have been also demonstrated. So far, normally-off characteristics have been realized with a recessed gate structure in lateral transistors and a submicron fin-channel structure in vertical transistors without p-type doping ^11–13) because of the difficulty in fabricating a p-type conductive layer of β-Ga₂O₃. However, the threshold voltage (V_th) of these devices strongly depends on the recess depth or the submicron fin width. Therefore, it is difficult to fabricate mm-size power devices on conventional 4 and 6 inch mass-production lines. β-Ga₂O₃ high-resistive p-like-well structures whose V_th depends on the dopant concentration of deep acceptors such as nitrogen (N) ^14–16) and magnesium (Mg) ^16–18) have been investigated as alternative structures in which V_th does not strongly depend on the recess depth or fin width. In particular, a lateral transistor using a thin N-doped layer grown by molecular beam epitaxy ¹⁹⁾ and a vertical U-shaped trench gate metal-oxide-semiconductor field-effect transistor (MOS FET) using an N-ion implantation layer ²⁰⁾ were reported to have normally-off characteristics. However, the former transistor operated only in the subthreshold region and the later transistor required a large positive gate-bias voltage (V_gs) of 25 V for operation due to a nonoptimized dose of N⁺ implantation. In this paper, we report high-performance normally-off multi-fin β-Ga₂O₃ vertical transistors (V_th ≥ 1.3 V, R_on,sp = 2.6 mΩ·cm² @V_gs = 10 V, μ_FE ∼ 100 cm² V⁻¹ s⁻¹) in which the fin width has little impact on V_th; they have a thick N-doped β-Ga₂O₃ high-resistive layer grown by halide vapor phase epitaxy (HVPE).

The schematic device structure is shown in Fig. 1(a). To evaluate the MOS channel mobility, a 3.3 μm N-doped Ga₂O₃ well layer was grown by HVPE on a (001) n⁺-β-Ga₂O₃ substrate without a drift layer. The first n⁺ layer ([Si]≈ 1 × 10¹⁶–8 × 10¹⁸ cm⁻³, 650 nm depth) was formed on the surface by Si implantation ²¹⁾ up to 500 nm depth and diffusion up to 650 nm depth by annealing the Si at 1000 °C for 30 min under N₂ to connect the MOS channel to the source contact region. The second n⁺ layer ([Si] ≈ 6 × 10¹⁹ cm⁻³, 200 nm depth) was formed on the top surface to facilitate the source ohmic contact by Si implantation and annealing at 900 °C for 1 min under N₂. Doping profiles under the source after device fabrication were confirmed by secondary ion mass spectrometry (SIMS; Fig. 2). The thickness of the non-Si-implanted and diffused layer was 2.6 μm, where the N concentration was ∼1.0 × 10¹⁶ cm⁻³, Si concentration was ∼3.0 × 10¹⁵ cm⁻³ or less, and Cl concentration was ∼2.0 × 10¹⁵ cm⁻³. The source of N was most likely the N₂ carrier gas during HVPE growth. After Si implantation and diffusion, the SiO₂ etch mask was deposited by plasma-enhanced chemical vapor deposition (PECVD). Fin channels were defined by electron beam lithography and formed by dry etching using CHF₃ and BCl₃. The resultant fin channels had a near-vertical sidewall profile [Fig. 1(b)]. After dry etching, the wafer was treated with HF for 15 min to remove the SiO₂ etch mask and plasma-damaged layer. Then, 53 nm SiO₂ gate dielectric was deposited by atomic layer deposition and was post-deposition annealing at 800 °C for 10 min. 70 nm Cr gate metal was deposited by electron beam evaporation (EBE). Next, a thick SiO₂ spacer was deposited by PECVD from the bottom to the top of the fins. The SiO₂ spacer and Cr gate metal were etched to 600 nm below the fin top by dry etching using CHF₃ and Cl₂/O₂. Then, a thick SiO₂ spacer was deposited by PECVD again on the top of the fin. After removing the SiO₂ on the fin top, the source electrode (Ti/Au) on the fin top and the drain electrode (Ti/Au) on the back side of the n⁺-β-Ga₂O₃ substrate were deposited by EBE.

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Figure 1(c) shows top views of the fabricated multi-fin devices. Defining 0° as a fin with (100)-like sidewalls along the [010] direction, the devices with fins rotated clockwise by 60° were evaluated. The fin widths (W_fin) of the devices were 1.0, 1.5, and 2.0 μm, and the pitches were 6.0, 6.5, and 7.0 μm, respectively. The devices comprised 14 fins side by side, and 10 of them were covered with the source electrode. This is because the fins on the outside of the pattern tended to have large errors from the designed dimensions during the dry etching process.

The dependence of the transistor transfer characteristics and V_th on the W_fin is shown in Figs. 3(a), 3(b). Here, current density (J) is normalized by the active area A (fin number of 10 × pitch × fin length of 60 μm). V_th is linearly extrapolated from the J_d–V_gs characteristic between V_gs = 2 and 3 V. The device characteristics discussed are those after V_th stabilization, unless otherwise specified. From Fig. 3(a), these devices showed V_th exceeding 1 V regardless of the W_fin, an on–off ratio >10⁸, and current densities >1 A cm⁻² (V_gs = 3 V, V_ds = 0.1 V). In this experiment, J_d max decreased as the W_fin decreased. This is because of the etch-back process of SiO₂ optimizing for W_fin = 2 μm pattern, so the top of the gate electrode was lowered from the Si-doped n⁺ layer when W_fin was decreased to 1.5, 1.0 μm, and the source-channel resistance drastically increased. Figure 3(b) shows the W_fin dependency of V_th. The open and closed circles indicate the experimental results of V_th and the solid and dotted lines indicate the calculation of V_th for n-channel FinFETs. The open and closed circles indicate the fresh and stabilized V_th, extracted from the first upward transfer J_d–V_gs sweep and the subsequent J_d–V_gs sweep. In the subsequent J_d–V_gs sweep, V_th increased by 0.3–0.6 V and stabilized. This instability is attributed to the increase in the negative interface charge density due to the electron trapped at the MOS interface or inside SiO₂. The trapped electron density was estimated to 1.2–2.6 × 10¹¹ cm². Because these traps have a long emission time constant, it takes more than two weeks to return to the fresh state from the stabilized state. The lines show the dependence of the calculated V_th on W_fin for n-channel FinFETs. The V_th was obtained by the following formula (1):

$$\begin{eqnarray}&&{V}_{\mathrm{th}}={\varphi }_{\mathrm{ms}}-q{N}_{D}\left(\frac{{W}^{2}}{2{\varepsilon }_{0}{\varepsilon }_{s}}+\frac{W}{{C}_{\mathrm{ox}}}\right),\end{eqnarray} \tag{ 1 }$$

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V_th: threshold voltage, φ_ms: work function difference between metal and semiconductor.

N_D: donor concentration, W: W_fin/2, ε₀: vacuum permittivity.

ε_s: relative permittivity of Ga₂O₃, C_ox: capacitance of oxide film.

As shown by the solid lines, at the N_D of 0.5–1.0 × 10¹⁶ cm⁻³, that is, the lowest value demonstrated by HVPE, V_th depends greatly on the W_fin, and a W_fin of 0.4–0.5 μm or less is required to obtain normally-off characteristics. On the other hand, as shown by the dashed lines, if the N_D could be reduced to 1.0 × 10¹⁴ cm⁻³, V_th became less dependent on the W_fin and normally-off characteristics can be obtained even at 1 μm or more. In the N-doped channel, the concentration of deep acceptor impurity (N) is higher than that of donor impurity (Cl and Si) as shown in Fig. 2. Therefore, donors are fully compensated by deep acceptors in N-doped channel and V_th becomes less dependent on the W_fin. Furthermore, the deep acceptor level may raise the Fermi level in N-doped channel to further increase V_th.

Figure 4(a) shows the J_d–V_gs characteristics of a device with a W_fin of ∼2.0 μm. The device has a V_th of ∼1.9 V (V_ds = 0.1 V) and an on–off ratio of >10⁸. The subthreshold slope is ∼90 mV dec⁻¹. Figure 4(b) shows the estimated field-effect-mobility of the N-doped MOS FET. The field-effect-mobility of ∼100 cm² V⁻¹ s⁻¹ is two-third of a hall-mobility (150 cm² V⁻¹ s⁻¹) of an unintentionally doped epitaxy layer (N_D-N_A = 1 × 10¹⁶ cm⁻³) by HVPE. The FET was estimated using the formula (2):

$$\begin{eqnarray}&&{\mu }_{\mathrm{FE}}=\frac{1}{20}\times \frac{{\rm{\Delta }}{I}_{{\rm{D}}}}{{\rm{\Delta }}{V}_{{\rm{G}}}}\times \frac{{L}_{\mathrm{ch}}}{{L}_{\mathrm{fin}}}\times \frac{{t}_{\mathrm{OX}}}{{\varepsilon }_{0}{\varepsilon }_{r}}\times \frac{1}{{V}_{\mathrm{ds}}}.\end{eqnarray} \tag{ 2 }$$

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The one channel current is 1/20 of the drain current I_D (the device has 10 fins which have two sidewalls in the active area A), the channel length L_ch (2.6 μm) obtained from SIMS profiles in Fig. 2, the channel width equal to the fin length L_fin (60 μm), dielectric constant ε_r (4.06) of the gate insulating film estimated from the MOS capacitor on the same wafer, and SiO₂ thickness t_OX (53 nm). High electron mobility of 100 cm² V⁻¹ s⁻¹ will be obtained by reducing the roughness scattering and coulomb scattering at the MOS interface, because the low N acceptor concentration (1.0 × 10¹⁶ cm⁻³) in the channel reduces the effective electric field at the MOS interface under positive gate-bias condition. This mobility is attractive for 600–3000 V MOS FET applications, where R_on,sp has been limited by the MOS channel resistance being proportional to inverse of the channel mobility.

Figure 5 shows the J_d–V_ds characteristics of a device with a W_fin of ∼2.0 μm. R_on,sp was determined to be 2.9 mΩ·cm² (V_gs = 10 V) and J_d = 760 A cm⁻² (V_gs = 10 V, V_ds = 5 V). The calculated R_on,sp contains the substrate series resistance, 1.5 mΩ·cm² (N_D = 4 × 10¹⁸ cm⁻³, μ = 47 cm² V⁻¹ s⁻¹, t = 550 μm); therefore, the actual MOS channel resistance R_ch,sp should be 1.4 mΩ·cm².

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In conclusion, high-performance normally-off β-Ga₂O₃ vertical FETs were demonstrated. The fin width's impact on V_th was reduced by introducing an N-doped β-Ga₂O₃ high-resistive layer grown by HVPE. An R_on,sp of 2.9 mΩ·cm², J_d of 760 A cm⁻², and mobility of ∼100 cm² V⁻¹ s⁻¹ were achieved in multi-fin devices. These results are a significant step forward in the development of β-Ga₂O₃ power transistors.

Acknowledgments