Recessed gate normally-OFF Al₂O₃/InAlN/GaN MOS-HEMT on silicon

Normally-OFF GaN-based high-electron-mobility transistors (HEMT) on silicon are attractive for high-power and high-speed switching applications owing to their low-cost substrate and large-scale integration. Most of the existing normally-OFF GaN devices were based on the AlGaN barrier, which shows low on-current drive.^1–5) This is due to the low sheet carrier density in the access region. On the other hand, automotive applications require normally-OFF GaN devices with high-output current density.⁶⁾ Alternatively, high-drain-current normally-OFF GaN devices can be achieved by utilizing InAlN/GaN heterostructures with their high two-dimensional electron gas (2DEG) density (N_2DEG ∼ 10¹³ cm⁻²) owing to enhanced piezoelectric and spontaneous polarization effects.

In the past, few researchers demonstrated such high-drain-current InAlN/GaN normally-OFF Schottky-gated HEMTs.^7–9) The persistent problem involving a Schottky gate is high leakage that limits high-gate-voltage operation. This requires a metal–oxide–semiconductor HEMT (MOS-HEMT) structure to suppress the gate leakage. However, very few reports on InAlN/GaN normally-OFF MOS-HEMTs are available.¹⁰⁾ Moreover, all these reports on InAlN/GaN normally-OFF devices were either on SiC or sapphire, which are more expensive than Si. Unlike the growth of InAlN/GaN heterostructures on SiC or sapphire, that of InAlN/GaN/Si is still technically challenging. Therefore, in this work, we attempt to fabricate a gate-recessed normally-OFF MOS-HEMT using InAlN/GaN heterostructures grown on Si.

In this letter, we report on the fabrication of an Al₂O₃/InAlN/GaN/Si normally-OFF MOS-HEMT by using a gate recess and by the atomic layer deposition (ALD) of the Al₂O₃ layer. The fabricated MOS-HEMT featured a maximum drain current density (I_ds,max) of 840 mA/mm at a gate bias (V_gs) of +8 V, a peak transconductance (g_m,max) of 157 mS/mm, a specific on-resistance (R_on,sp) of 0.8 mΩ·cm², and a threshold voltage (V_th) of +1.9 V. The MOS-HEMT also showed a peak field-effect mobility of 472 cm² V⁻¹ s⁻¹. The breakdown voltage (BV) of the normally-OFF MOS-HEMT with (W_g/L_gd = 15/4 µm) was 278 V at V_gs = 0 V.

The InAlN/GaN/Si heterostructures used in this work were grown using a Taiyo Nippon Sanso metalorganic chemical vapor disposition (MOCVD) SR-4000 system. The heterostructure consists of 3-µm-thick buffer layers (similar to the buffer design used for our AlGaN/GaN/Si heterostructures),¹¹⁾ a 1 µm GaN layer, and a 10 nm In_0.15Al_0.85N layer. A 1 nm AlN spacer layer was used between the GaN channel and the InAlN barrier to reduce the interface roughness scattering and improve the channel electron mobility. Hall effect measurements showed a high N_2DEG of ∼3.25 × 10¹³ cm⁻² and an electron mobility of 1020 cm²/V·s yielding a low sheet resistance (R_sh) of 188 Ω/□. The N_2DEG value for this InAlN/GaN/Si heterostructure is comparable to those for device-grade InAlN/GaN heterostructures grown on sapphire and SiC.^7,8,12)

The MOS-HEMT fabrication started with mesa isolation using BCl₃-plasma-based reactive ion etching. Source/drain ohmic contacts were formed by depositing a Ti/Al/Ni/Au metal stack and annealing at 800 °C for 30 s in N₂ ambient. A gate footprint of 1.5 µm was used to etch the InAlN barrier layer in the gate region. The etching was stopped when the drain current (without the gate electrode) became zero. A 20 nm Al₂O₃ layer was AL-deposited at 300 °C. Subsequently, postdeposition annealing was carried out at 600 °C for 1 min to improve the oxide/semiconductor interface.^2,13) Finally, gate and pad metals (Pd/Ti/Au) were deposited. A schematic representation of the fabricated gate-recessed Al₂O₃/InAlN/GaN MOS-HEMT is shown in Fig. 1. For reference, a Schottky-gated normally-ON HEMT was also fabricated. Transmission line model (TLM) measurements showed a low R_sh value of 157 Ω/□ for a MOS-HEMT with Al₂O₃ passivation versus an R_sh of 191 Ω/□ for a conventional InAlN/GaN HEMT without Al₂O₃ passivation.

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Direct current (DC) measurements were carried out on a MOS-HEMT with device dimensions of (W/L)_g = 15/1.5 µm. Figure 2(a) shows typical DC transfer I_ds–V_gs characteristics at a V_ds of 8 V (saturation region) of the as-fabricated HEMT and MOS-HEMT. The gate-recessed MOS-HEMT demonstrated normally-OFF operation with a V_th of +1.9 V as compared with a V_th of −3.9 V for the conventional HEMT from the linear extrapolation of respective I_ds–V_gs curves. The InAlN/GaN MOS-HEMT showed an off-state current of 10⁻⁷ mA/mm at a gate bias of −1 V, and the corresponding on/off current ratio was ∼10⁹. The drain leakage at a gate bias of 0 V was 10⁻² mA/mm, which is lower than that reported for an InAlN/GaN normally-off MOS-HEMT.¹⁰⁾ The peak transconductances of the HEMT and MOS-HEMT were 272 and 157 mS/mm, respectively.

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A representative DC I_ds–V_ds characteristic of a MOS-HEMT is shown in Fig. 2(b). As shown, the MOS-HEMT exhibited an I_dsmax of 840 mA/mm at a V_gs of +8 V. This I_dsmax is relatively lower than that of the InAlN/GaN HEMT (I_dsmax ∼ 1300 mA/mm at a V_gs of 1 V). Nevertheless, the I_dsmax of the Al₂O₃/InAlN/GaN normally-OFF MOS-HEMT is higher than those of gate-recessed normally-OFF GaN MOS-HEMTs with a conventional AlGaN barrier^14–17) and is attributed to InAlN/GaN/Si heterostructures with a low sheet resistance and a high 2DEG density in the source/drain regions. Furthermore, a small knee voltage of 4.2 V with a low on-resistance of 5.9 Ω·mm (at a current level of 200 mA/mm) was observed for the MOS-HEMT. The translated specific R_on,sp was 0.8 mΩ·cm², with the active device area including a 2 µm transfer length from source/drain contacts.

The two-terminal gate–source leakage current (I_gs) values, as a function of V_gs for the HEMT and gate-recessed MOS-HEMT, are shown in Fig. 3. The I_gs of the MOS-HEMT was ∼10⁸ orders lower than that of the Schottky-gated HEMT at a reverse bias of −10 V. The MOS-HEMT also showed a low I_gs of 3.1 × 10⁻⁸ mA/mm at a forward bias of +8 V. Thus, the gate-recessed MOS-HEMT exhibits a low gate leakage current and ensures high-V_gs operation.

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Capacitance–voltage (C–V) measurements at 100 kHz were carried out on a gate-recessed Al₂O₃/InAlN/GaN/Si MOS diode of 300 µm diameter, as shown in Fig. 4(a). Typical C–V curves show a sharp transition from depletion to the accumulation regime with a small hysteresis window (ΔV_th) of 70 mV when the bias was swept from −4 to +8 V and from +8 to −4 V at a sweep-rate of 0.05 V/s. A small hysteresis during C–V sweeps indicates a low oxide/semiconductor trap state density in the recessed MOS structure.^18,19)

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To access the Al₂O₃/InAlN/GaN/Si MOS-channel controllability, the field-effect mobility (μ_FE) was extracted at a low drain bias (V_ds = 0.1 V) using the following expression:

$$\begin{equation*} \mu_{\text{FE}} = \frac{g_{\text{m}}L}{WC_{\text{ox}}V_{\text{ds}}}. \end{equation*}$$

Figure 4(b) shows the extracted μ_FE using "FAT-FET" with device dimensions (W/L)_g of 200/100 µm. The peak μ_FE was 472 cm² V⁻¹ s⁻¹, which is about twofold higher than those of some of the high-performance gate-recessed Al₂O₃/GaN MOS-channel normally-OFF devices.^14,19,20) This clearly shows that the use of a 1 nm AlN spacer layer in the InAlN/GaN heterostructure markedly reduces the interface roughness scattering,²¹⁾ and that the MOS channel effectively modulates the drain current. These excellent device performance characteristics are due to the high-quality InAlN/GaN/Si epitaxial growth using thick buffer layers, in combination with a high-k gate-recessed MOS structure.

The MOS-HEMT with an L_gd of 4 µm was subjected to three-terminal OFF-state BV measurement at a V_gs of 0 V. As shown in Fig. 5(a), the BV of the device was 278 V at a current compliance of 1 mA/mm, and the observed drain leakage current was high over the applied drain bias for the Al₂O₃/InAlN/GaN MOS-HEMT. Such a high drain leakage current in InAlN/GaN-based devices is likely to be caused by charge carrier leakage through buffer and surface leakage currents.^10,22) Furthermore, the BV can be improved by reducing the buffer leakage current and growing an AlN cap layer to reduce the surface leakage.²³⁾ Figure 5(b) shows the benchmarking of the maximum drain current density and threshold voltage of reported normally-OFF GaN devices with InAlN and AlGaN as barrier layers. It is worth mentioning that most of the normally-OFF GaN/Si devices used AlGaN as a barrier layer. From a comparison, it can be observed that the Al₂O₃/InAlN/GaN/Si normally-OFF MOS-HEMT in this work features a high I_ds,max compared with its predecessors.

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A high-drain-current-density normally-OFF MOS-HEMT has been successfully demonstrated using an InAlN/GaN heterostructure grown on a Si substrate. The as-fabricated Al₂O₃/InAlN/GaN normally-OFF MOS-HEMT featured an output drain current density of 840 mA/mm at a V_gs of +8 V, a peak transconductance of 157 mS/mm, a V_th of +1.9 V, an R_on,sp of 0.8 mΩ·cm², and a BV of 278 V at a V_gs of 0 V. Furthermore, the MOS-HEMT showed a peak field-effect mobility of 472 cm² V⁻¹ s⁻¹. These results are promising for the potential utilization of InAlN/GaN/Si normally-OFF MOS devices in next-generation power applications.

Acknowledgment