GaN FinFETs and trigate devices for power and RF applications: review and perspective

Figures 1(a) and (b) show two basic architectures of the lateral GaN FinFETs, the first type with the fin-shaped channels extending across the entire source-to-drain region and the second type with the fin-shaped channel only present in the gate region. The first type of GaN FinFETs is similar to the digital FinFET, and it can be fabricated either through the bottom-up growth of GaN nanowire (NW) transistors [42–44] or through top-down etching of a planar GaN structure [45–48]. This latter device is often called 'nanoribbon (NR) GaN HEMT.'

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While the NR GaN HEMTs allow strong carrier confinement, the 2DEG density in the NR was found to be very sensitive to mechanical stress, which can be easily influenced by passivation dielectrics and dielectric thickness [47, 49, 50]. In addition, the fin-shaped channels in the access regions induce higher access resistance and limit the current density normalized with the entire device area. As a result, the second type of FinFET (figure 1(b)), often referred to as the trigate HEMT, later became a more popular device of choice for GaN RF and power FinFETs.

A unique feature of the GaN FinFET that differs from the Si FinFET is the diversity in fin bodies. While Si fins usually employ an intrinsic or doped body, GaN FinFET bodies can be made of doped GaN, AlGaN/GaN heterojunction, and multiple heterojunctions (see figure 1(c)). In power and RF applications, devices are used as solid-state switches and amplifiers, and they usually operate in the linear or saturation regime, respectively, instead of the sub-threshold regime. The different device operation regimes suggest different current paths in GaN fins compared to the ones in digital Si FinFETs. As shown in figure 1(d), after the device turn-on, current can flow simultaneously through the bulk fin and the two sidewall accumulation-mode metal–oxide–semiconductor (MOS) channels in the heterojunction-free fins, and through the 2DEG channel and sidewall MOS channels in the heterojunction fins. In heterojunction fins, the 2DEG can be modulated by the fringing E-field from the top gate and two sidewall gates; in multi-channel fins, the buried 2DEG channels are mainly controlled by the sidewall gates.

Figure 1(e) illustrates three main types of gate stack in GaN trigate devices. The first trigate HEMTs were demonstrated based on Schottky-type gates by Tamura et al [51] and Ohi and Hashizume [52]. These Schottky-type trigate HEMTs were initially named as the multi-mesa-channel (MMC) HEMTs [51–54] or the nanochannel array HEMTs [55], depending on the degree of fin width scaling. More recently, trigate GaN HEMTs have adopted the MOS and the metal–insulator–semiconductor (MIS) gate stacks, which have gradually become the prevailing choice of gate stack in GaN trigate HEMTs. Compared to the Schottky-type trigate, the MIS/MOS-type trigate significantly reduces the gate leakage current and increases the gate voltage (V_G) operation range.

Recently, Ma and Xiao et al proposed a new trigate configuration, the junction trigate, in which the p–n junction wraps around the heterojunction fins and the gate metal forms Ohmic contact to the p-type material [56]. Owing to the higher built-in potential and the obviation of voltage drop in the insulator, the p–n junction can potentially provide a stronger depletion compared to the MIS/MOS stack, making it easier to realize E-mode operation and suppress short-channel effects. In addition, the junction trigate can eliminate the sidewall MOS channels and therefore avoid the potential gate dielectrics reliability issues.

Vertical power/RF FinFET combines the sub-micron fin-shaped channels to provide superior gate control and a lightly-doped, thick drift region to accommodate the large current, high voltage, and high power. The concept of using multiple gates to control a vertical channel on top of a drift region dates back to static induction transistors (SITs) and power junction field-effect transistors (JFETs). The SIT, first proposed in the 1950s and realized in the 1970s [57], possesses Schottky- or p–n-type gate stacks residing in recessed trenches [58]. The SIT is typically D-mode and pinched off by channel depletion at negative V_G. Commercial SiC SITs are now available for high-frequency power amplification applications with voltage up to 125 V [59, 60]. The SiC JFET has a similar structure but is developed for high-voltage power applications. While the vertical channel is n-type, the gate typically locates at the trench bottoms that are implanted to become p⁺-type. Both normally-off [61] and normally-on [62] SiC JFETs have been recently commercialized from 650 V to 1.7 kV [63].

Figure 2(a) shows the schematic of a vertical Fin-MOSFET. A key feature that differentiates the vertical Fin-MOSFET with SITs and JFETs is the sidewall MOS stack that allows parallel current conduction through the bulk fin and the two accumulation-mode MOS channels [64]. This sidewall MOS channel can significantly reduce the channel on-resistance and increase the current density. In addition, the vertical Fin-MOSFET only needs n-type layers and does not require epitaxial regrowth, making it attractive for many emerging semiconductors where only one type of doping is viable [41]. A recent review of wide-bandgap and ultra-wide-bandgap vertical power Fin-MOSFETs is presented in [41].

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Figure 2(b) shows the schematic of a vertical GaN Fin-JFET, which has a similar structure with SiC JFET but typically has an increasingly scaled fin width with the p-GaN fully filling the inter-fin trenches. The fabrication of vertical GaN Fin-JFET usually relies on the selective-area p-GaN epitaxy [65, 66], which can potentially allow better control of dopant diffusion when compared to the ion implantation used in SiC JFET fabrication. The fin-JFET retains the merits of the fin channel, making it easier to realize the avalanche breakdown [36, 37], and can potentially eliminate the oxide reliability issues that have been revealed to be a critical concern in SiC MOSFET [67] particularly at high temperatures [68, 69].

Vertical power FinFETs can be built on either a fully vertical structure (figure 2) or a quasi-vertical structure where the drain locates at the bottom of a deeply recessed mesa on the same side of the wafer as the source and gate [35, 70–73]. The fully vertical structure usually employs a free-standing n⁺-GaN substrate. In contrast, the quasi-vertical structure allows the fabrication of vertical GaN devices on foreign substrates, e.g. Si substrate (which is widely used in lateral GaN HEMTs). The GaN epitaxy on GaN substrates typically provides lower dislocation density compared to the one on foreign substrates, which enables lower leakage current in vertical devices [74]. Whereas, the GaN-on-Si and GaN-on-sapphire wafers provide cost advantages. Alternatively, GaN grown on engineered substrates (QST®) with a matched thermal expansion coefficient could enable low-cost vertical GaN FinFETs with thick (>10 μm) drift layers and large wafer diameters (8–12 inch) [35]. It should be noted that fully-vertical devices can also be fabricated in GaN-on-Si by a variety of approaches, including the layer transfer [73, 75], buffer doping [76, 77], and deep backside trenches [78, 79]. The performance and cost trade-offs between the full-vertical and quasi-vertical GaN devices have been thoroughly reviewed and discussed in [31], which will not be the focus of this paper.

The first trigate HEMT with over 100 V blocking voltage was demonstrated by Ohi and Hashizume in 2009 [52], based on the Schottky-type trigate (i.e. MMC HEMT). A fin width (W_Fin) down to 70–90 nm allows a positive shift in threshold voltage (V_TH) to −2.5 V. A breakdown voltage (BV) of 250 V was reported. The device R_on is found to be dominated by the channel resistance in the gate region [54], making the drain current (I_D) insensitive to access resistance. Reduced current collapse [53] and thermal resistance [26] were also reported in this D-mode Schottky-type trigate HEMT.

The first E-mode medium-voltage trigate HEMT was reported by Lu et al in 2012 [80] using an MIS-type trigate. To increase V_TH, an additional AlGaN barrier recess was implemented in part of the top region of the 120 nm wide fins (figure 3), allowing a V_TH over 0.8 V from linear extrapolation in the transfer characteristics. The device shows a BV of 565 V extracted at I_D of 0.6 µA mm⁻¹ and V_G of 0 V.

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Heterostructure-free power GaN FinFETs were reported by Im et al in 2013 [81, 82], with a W_Fin down to 60 nm, a V_TH up to −1.5 V, and a destructive BV of 600 V. The comparison between GaN FinFETs and AlGaN/GaN FinFETs reveals that [82, 83], though the AlGaN/GaN FinFET has higher channel mobility, it exhibits a more pronounced W_Fin dependence of R_on and an increased susceptibility to short-channel effects due to the high electron concentration in 2DEG.

Since 2017, Ma et al [84–87] have reported continued performance advancements in D-mode trigate power HEMTs by optimizing the fin geometry to enhance BV and using stacked 2DEG channels to lower R_on. With a higher filling factor [i.e. W_Fin/(W_Fin + S_Fin), where S_Fin is the fin spacing], a 792 V BV and 0.91 mΩ cm² R_on were reported in D-mode trigate HEMTs [84]. A slanted trigate structure was proposed in [85], where the fin width increases from 350 nm at the source side of the gate to 700 nm at the drain side of the gate. This slanted trigate allows reducing the E-field crowding at the gate region and enables a BV to increase up to 1350 V at I_D of 1 µA mm⁻¹ [85]. In 2018, Ma et al reported a five-2DEG-channel trigate HEMT, which demonstrates a 47% smaller R_on compared to the single-channel trigate HEMT [87]. In 2019, Ma et al reported a superior BV and R_on trade-off (1230 V/0.47 mΩ cm², where BV is extracted at I_D of 1 mA mm⁻¹) in a D-mode GaN power HEMT that combines the multi-channel structure and the slanted trigate structure [86] (figure 4).

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Since 2019, multiple groups have reported performance advancements in E-mode trigate power HEMTs. Nela et al demonstrated an E-mode fin-based MOS gate with a planar gate using high work-function (WF) metals [88]. Without metal coverage into the inter-fin trenches, this structure allows the scaling of W_Fin and S_Fin both down to below 40 nm, with the high-voltage E-mode operation being realized when W_Fin is reduced to 20 nm. Zhu et al [89] and Huang et al [90] reported MIS-type trigate HEMTs with additional gate recess, similar to Lu's work in 2012, but with enhanced performance by either integrating a gate field plate [89] or replacing the AlGaN/GaN barrier with an InAlN/GaN barrier [90], respectively. The InAlN/GaN barrier has a higher 2DEG density and stronger spontaneous polarization; hence, the partial strain relaxation and V_TH shift are more pronounced in narrow fins. Recently, Huang et al reported further reductions of the off-state leakage current in trigate InAlN/GaN power MIS-HEMTs by using a Schottky tri-drain extension [91].

An E-mode trigate MIS-HEMT using a novel ferroelectric charge-trapping dielectrics was reported by Wu et al [92]. The trapped negative charges in the periodic HfZrO₄/Al₂O₃ gate dielectrics lift V_TH, which obviates the additional gate recess and relaxes the need for aggressive W_Fin scaling to realize the positive V_TH. This further reduces R_on in the gate region and improves the current density [92]. However, it should be noted that the charge-trapping dielectrics necessitate a high gate bias (12 V) stress for the initialization process that fills the traps and converts the trigate device from the D-mode into the E-mode operation. The thermal stability of this trapped dielectrics and the relevant de-trapping time have not been reported, which may be a concern for the long-term and high-temperature operation of power devices.

While all the prior D-mode and E-mode trigate HEMTs rely on the Schottky gate or the MIS gate, Ma and Xiao et al recently demonstrated a trigate GaN junction HEMT using the heterogeneous p–n junction between p-NiO and 2DEG [56]. As shown in figure 5, the gate metal Ni forms Ohmic contact to p-NiO, and the hole concentration in NiO is above 10¹⁹ cm⁻³, allowing the entire WF difference between Ni and GaN to fall on GaN for fin depletion. Owing to the stronger depletion in the junction trigate when compared to the MIS trigate, a higher V_TH was reported in trigate junction HEMTs than that in the trigate MIS-HEMTs with the same W_Fin. This stronger depletion also suppresses the short-channel effect, allowing a gate length scaling down to at least 200 nm without device punch-through at over 2000 V drain voltage and zero V_G, while maintaining very low off-state leakage current. These junction trigate and junction fin structures have also been recently leveraged to develop high-voltage multi-channel AlGaN/GaN Schottky barrier diodes up to 5000 V [93].

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In 2016–2017, Sun et al reported the first E-mode vertical GaN power Fin-MOSFETs [32, 94] with a W_Fin of 450 nm, a R_on of 0.36 mΩ cm² (normalized to the fin area) and a BV over 800 V. The major challenges to further improve the BV and R_on were found to be the E-field crowding at the fin corners and the high contact resistance at the top of sub-micron-meter fins, respectively. To address the first challenge, a wet-etch based corner rounding process was developed, which allows removal of surface dry-etch damages and rounding the sharp fin corners [95]. At the same time, a thick field oxide was inserted between the gate metal and trench bottom, which enables a reduced-surface-field structure that moves the peak E-field from the trench bottom to the device periphery [32, 33]. To address the second challenge, a highly-doped n⁺-cap-layer was added to the epitaxial structure, and a Cl-based treatment was applied to facilitate the Ohmic formation [33, 96]. With these optimizations, Zhang and Sun et al demonstrated 1200 V E-mode vertical GaN Fin-MOSFETs with 200 nm W_Fin and 1 mΩ cm² R_on normalized to the total device active area [33]. This device shows one of the highest static power FOMs ($R_{{\text{on}}}^2/{\text{BV}}$) reported in all 0.6–1.7 kV Si, SiC and GaN transistors [33].

Subsequently, large-area 1.2 kV, 5 A GaN Fin-MOSFETs with a chip area of 0.45 mm² were reported based on a 2 inch wafer fabrication process [34]. As shown in figure 6, the large-area device has about 700 fins and an implanted edge termination at the device periphery. The demonstration of large-area devices allows experimental evaluation of junction capacitances, which often do not scale with the area. The gate charge (Q_G) and gate-to-drain charge (Q_GD) were further derived, which usually determines the device switching loss in hard-switching applications. A record-high switching FOM [R_on·(Q_G + Q_GD)] in all 0.9–1.2 kV transistors was reported from the large-area vertical GaN FinFETs [34].

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While the fabrication of lateral GaN trigate HEMTs simply adds one or two steps for fin etch onto the standard HEMT process, the fabrication of vertical Fin-MOSFET is entirely different. As shown in figure 6, the fabrication starts with over 1 µm fin etch on the n⁺-GaN/n⁻-GaN epistructure, followed by corner rounding [95] and edge termination implantation [97, 98]. Then all dielectric and metal layers are fabricated in a bottom-up manner, starting from the conformal deposition or sputtering, followed by a controlled etch to the desired level. The accurate control over the etch depth of the sidewall-covering dielectric/metal layers is realized by a photoresist planarization and timed etch technique, where the etch-stop level is defined by the thickness of the remaining photoresist in sub-micron trenches [32, 33, 41].

The concept of vertical GaN Fin-JFET was first patented in [99], followed by the simulation presented in [66] and [67]. The trade-off between vertical Fin-JFET and Fin-MOSFET is similar to the one between lateral trigate MIS-HEMTs and trigate junction HEMTs [56]. The stronger depletion of the p–n junction can potentially allow the realization of E-mode operation with a less scaled fin width and the suppression of punch-through at high blocking voltages. In addition, by placing p-GaN close to the E-field crowding region at the fin corners, avalanche breakdown can be potentially realized without complicated E-field management structures. Whereas, the Fin-JFET channel only has the bulk fin conduction path; the absence of the sidewall MOS channels in parallel would increase the channel resistance when compared to the Fin-MOSFET channel [41].

As shown in figure 7(a), selective-area lateral p–n junctions were demonstrated by Yeluri et al [100] and Zhang [101] using the dielectric-masked p-GaN trench-filling regrowth, as well as by selective ion implantation by Tadjer et al [102] and Zhang et al [103]. Subsequently, initial experimental demonstrations of vertical GaN Fin-JFETs were reported by Kotzea et al [67] and Yang et al [104] by using the selective p-GaN regrowth (figure 7(b)) and the blanket-regrowth-then-planarization-etch approach (figure 7(c)), respectively. However, the Fin-JFETs fabricated in both works showed merely basic transistor behaviors with large off-state leakage currents, minimal voltage blocking capabilities, and an on/off current ratio below 100. The large parasitic leakage was reported to be located at the regrown sidewall p–n junctions. The origin of the leakage current in these regrown nonplanar p-GaN structures has been recently revealed [105], as being related to the n⁺-type interfacial impurities (e.g. Si, O, C) introduced in the regrowth process [106–112].

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Very recently in the 2020 IEEE International Electron Devices Meeting (IEDM), the first 1.2 kV vertical GaN Fin-JFET was announced by NexGen Power Systems and Virginia Tech [36, 37]. The Fin-JFET was fabricated by NexGen in a 100 mm GaN-on-GaN fab, and it shows an on/off current ratio of 10⁹, a specific R_on of 0.82 mΩ cm², an on-state current over 4 A, and a V_TH as high as 2.05 V [37]. The V_TH shows less than 0.15 V shift from 25 °C to 200 °C, revealing the robust normally-off operation. The specific R_on is found be to at least 3 ∼ 4-fold lower than commercial 1.2 kV SiC MSOFETs [37].

In addition, the 1.2 kV vertical GaN Fin-JFETs also shows a robust avalanche under the unclamped inductive switching conditions with an avalanche BV of 1470 V and an avalanche current over 1 A [36, 37] (figure 7(d)). Despite the earlier reports of avalanche in vertical GaN p–n diodes [113, 114], the vertical GaN Fin-JFETs demonstrated the first avalanche capability in GaN transistors to date. Double-pulse tests were also reported to evaluate the device switching performance. When switched at 600 V/4 A, a rise/fall time of 12.9 ns/10.3 ns and a total loss of 37 μJ were presented (figure 7(e)), which outperform the commercial SiC MOSFETs under similar switching conditions.

Table 2 benchmarks the key device metrics of the reported D-mode and E-mode lateral GaN FinFETs and trigate HEMTs, as well as the E-mode vertical GaN FinFETs, all for power switching applications. Figure 8 plots the BV vs. R_on trade-off of the E-mode FinFETs and trigate HEMTs, in comparison to other E-mode lateral and vertical power transistors. Generally, lateral GaN trigate HEMTs and vertical GaN FinFETs show superior performance over other similarly-rated devices (e.g. commercial planar HEMTs, vertical MOSFETs), reinforcing their potential for power applications.

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E-mode lateral GaN trigate HEMTs show excellent R_on vs. BV trade-off in the 600–1200 V range, while vertical GaN FinFETs exhibit superior performance at 1200 V level. Whereas, it should be noted that all the reported lateral GaN trigate power HEMTs are small-area devices, where the specific R_on calculation accounts for only about 1.5 µm transfer length for source and drain contacts (or completely ignored in some reports). Due to a possible larger finger width (over 3 µm) and other unaccounted areas in multi-finger HEMTs, the specific R_on of large-area [115] and commercial GaN HEMTs are often larger than the one of the small-area counterpart. In contrast, large-area vertical GaN FinFETs have been demonstrated [34, 36] and their switching performance have been studied in the context of power converters.

The lack of demonstration of large-area lateral trigate HEMTs makes it difficult to evaluate their capacitance, charges, and losses similar to the switching performance analysis and characterizations reported for vertical GaN FinFETs [34, 36, 116, 117]. Hence, at this moment, it is still not clear whether trigate HEMTs or vertical FinFETs would be more advantageous for 600–1200 V applications.

One of the primary challenges for large-signal RF applications of GaN transistors is the nonlinear behavior of short-channel devices. Figure 9(a) shows the g_m characteristics of an ideal MOSFET, which increases linearly beyond V_TH and remains flat after reaching the peak value. However, in conventional planar GaN transistors, g_m shows distorted bell-shaped characteristics after reaching the peak value. This sharp g_m drop causes a sharp drop in f_T (figure 9(b)) and introduces non-linearity in large-signal operation. The device non-linearities result in significant side-bands, a saturation of output power at high input powers, as well as signal distortion in power amplifier operations. This issue becomes more serious as the gate length scales down. A relatively flatter g_m characteristic is desirable for the linear large signal operation of GaN transistors. Several material-level (e.g. N-polar GaN [118], polarization engineering [119]) and circuit-level (derivative superposition and cancellation [120]) approaches have been proposed and demonstrated to improve the linearity of GaN transistors. However, the material-level and circuit-level approaches are challenging and create additional complexity. GaN NW or FinFET devices emerged as one of the most promising candidates for linear large-signal operation for the ease of technological implementation and tunability [23–25].

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The first high-frequency characterization of GaN NW FET was demonstrated by Vandenbrouck et al in 2009 [121], using a GaN/AlN/AlGaN MISFET structure. NWs were synthesized on a c-plane sapphire substrate, with 80–160 nm diameter and 10–20 μm length. Maximum transconductance (g_m,max) value of 45 μS with relatively flat g_m profile over 5 V was demonstrated. The device also showed an f_T of 5 GHz. Despite the promising performance, the bottom-up technology for NW formation limits the device scalability (only 5 NWs in [121]) for applications. Moreover, the demonstrated device also suffers from low current driving capability [47].

To overcome the challenges of bottom-up technology, Azize et al [47] demonstrated NR MIS-HEMTs by top-down selective etching of InAlN barrier layers on GaN. A conformal Al₂O₃ layer was deposited in InAlN/GaN NRs to both increase the NR charge density through piezoelectric-induced doping and reduce the gate leakage current. The devices with W_fin of 50–90 nm showed g_m,max of 15 mS with relatively flat profile over 5 V. f_T of 6.75 GHz and f_max of 14.5 GHz were measured. In this device, multiple NRs are formed in parallel between source and drain, which may potentially increase the source access resistance due to limited source contact area [23].

There have been several explanations for the g_m roll-off in the literature, including self-heating effects [122], an increase of the dynamic source access resistance [123], emission of optical phonons [124], and contact barriers [125]. Lee et al [23] proposed that suppression of source access resistance can improve the g_m roll-off behavior in GaN NW HEMTs and demonstrated InAlN/AlN barrier HEMTs where NWs were only formed under the gate region while maintaining planar structure under the source region (figure 10(a)) to enable higher current injection to the channel [23]. The highly scaled (gate length L_G = 70–80 nm, W_fin = 88 nm) devices showed superior current driving capability (3.5 A mm⁻¹ at V_G = 1 V), suppression of g_m and f_T roll-off at higher biases compared to the planar HEMTs (figure 10(b)). A peak f_T of 100 GHz was demonstrated, which is 35% lower than planar devices due to fringing capacitances from the side gate and access region that are wider than the effective channel region [23].

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To improve the g_m roll-off suppression characteristics, Jo et al [126] found that the crystal selective wet etch can improve the sidewall morphology by mitigating the plasma etch damages and hence, increase the contribution of sidewall MOS channel. The positive V_TH of the sidewall MOS channel, along with the negative V_TH of the 2DEG channel, can suppress the g_m roll-off and enable broad g_m-plateau [126]. Moreover, different plasma (fluorine, O₂, N₂O) treatments [127, 128] and self-aligned [129] gate technology can be used to improve the frequency performance and current driving capability of these devices.

Ture et al [130] demonstrated the use of the quaternary InAlGaN and binary AlN barrier layers lattice-matched with AlN spacer to improve the saturation I_D and g_m of trigate HEMTs when compared to the AlGaN-based counterparts [130]. The high Al-concentration InAlGaN and AlN barrier can offer larger polarization difference with GaN and hence, higher 2DEG density [22] and higher I_D,max (3.8 A mm⁻¹ for AlN compared to 2 A mm⁻¹ for AlGaN). In 2017, Ture et al demonstrated a four stage W-band power amplifier using AlN barrier trigate HEMTs for the first time [131]. The power amplifier using trigate devices shows superior output power, gain, and power added efficiency (30 dBm, 12 dB, 6%, respectively) over planar devices (28 dBm, 10 dB, 4%, respectively) in the frequency range of 86–94 GHz [131].

In 2017, Zhang et al [132] first reported the improvement of linearity in large-signal operation due to the suppression of g_m roll-off using T-gate AlGaN barrier trigate HEMT. An on-wafer load-pull measurement at 8 GHz (class AB operation with V_D = 28 V, I_D,Q = 0.1 I_D,max) showed output power P_out = 11.3 W mm⁻¹ (1.66 × higher than planar HEMTs). The P_out enhancement was attributed to the combination of I_D improvement and self-heating suppression in trigate device [132]. The third order inter-modulation distortion (IM3) of FinFET showed a ∼5.5 dBc improvement over a planar device, which is aligned with the suppression of g_m roll-off.

To further improve the linearity performance of GaN trigate devices, Joglekar and Radhakrishna et al [24]. proposed and demonstrated a device-level analog of the circuit-level 'g_m compensation' technique using a composite device consisting of multiple fins with variable widths. The key idea is to minimize IM3, which is proportional to the second derivative of g_m, i.e. ${g^{\prime\prime}_{\text{m}}}$. A carefully designed composite device with multiple parallel fins with variable width (different V_TH) can cancel out ${g^{\prime\prime}_{\text{m}}}$ (figure 11(a)) and lead to a highly linear transistor with very low IM3. Class AB operation of a composite AlGaN barrier device containing five different W_Fin (ranging from ∼150–450 nm) shows a significantly higher P_out at 6 GHz with no saturation for input power P_in up to 15 dBm, delayed onset of second and third harmonic, and 20 dB reduction of IM3 compared to the planar device. A significant reduction in second harmonic (and hence delayed gain compression) is consistent with the fact that the flat-g_m characteristics lead to ${g^{\prime\prime}_{\text{m}}}\, \approx$0 [24]. However, due to the presence of multiple V_TH's in the device, the conduction through the lower V_TH fins can create non-linearity in the composite device current at higher V_G. Moreover, the width of the g_m-plateau cannot be substantially improved for large-signal operations with Fin only architectures (due to limited tunability range for V_TH) and Schottky metal gates (which are susceptible to gate diode turn-on and large leakages at small positive V_G) [25].

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To overcome these challenges, Choi et al [25] adopted a composite MIS-HEMT where the channel is a combination of both planar HEMT and fins with different widths [25], as shown in figure 11(b). The use of the MIS structure allowed a wider range (−0.5 to −4 V) of V_TH tunability. With careful optimization of fin width and number of fins along with T-gate, a composite device with g_m-plateau > 6 V, and ${g^{\prime\prime}_m}$ ≈ 0 in four different V_G values has been demonstrated. Single-tone measurement of the device showed a maximum power-added efficiency (PAE) of 32.3%, and two-tone measurement at 30 GHz showed 3rd order output intercept point (OIP3) and OIP3/PDC of 31 dBm and 8.2 dB, respectively. The high linearity and low noise FOM show the promise of the composite device in mm-wave low noise amplifier application over 20 GHz [25].

Another interesting trigate device structure that can offer high linearity in GaN power amplifier is superlattice castellated FET (SLCFET), which was originally proposed for RF switching applications [133–136]. The superlattice channel of the device consists of stacked 2DEG layers similar to the multi-channel structure shown in figure 1, where the trigate structure is essential for electrostatic control of the buried 2DEG layers. It should be noted this SLCFET predates the multi-2DEG-channel trigate HEMTs later developed for power applications [86, 87]. Due to the presence of multiple channels in SLCFET, g_m shows unique double hump and broad plateau characteristics, which lead to higher linearity. Recently, L_G = 150 nm T-gate SLCFET with f_T = 47 GHz, f_max = 124 GHz, P_out >6 W mm⁻¹, PAE >45%, and OIP₃/PDC = 6 dB at 30 GHz using large-signal measurement have been demonstrated in the second-generation GaN SLCFETs [134].

A planar nano-strip channel structure has been proposed by Xing et al by using partial ion implantation isolation to define fin-like channels under the gate [137]. This structure overcomes the parasitic capacitance issue caused by the gate metals on the fin sidewalls. InAlN/GaN GaN HEMTs with a gate length of 80 nm were reported, with both wrapped-gate fin channels and planar nano-strip channels. The planar-nanostrip-channel HEMTs showed a roughly constant source resistance at different I_D's as well as much flatter g_m and f_T than those in planar HEMTs, as well as an f_T higher than that of standard Fin-HEMTs. Later, Xing et al introduced an MIS gate to reduce the gate leakage current and further increase the device's linearity [138].

In addition to linearity improvement, the trigate structure was also used to make E-mode RF HEMTs. Liu et al reported the E-mode Schottky-type trigate HEMTs with W_Fin below 90 nm [55]. However, the reported f_T and f_max are relatively low due to the large gate length (2 µm) in the fabricated devices.

In 2020, Perozek et al [139] adapted the vertical FinFETs in [32, 34, 94] for use in RF applications. Key design modifications include the use of a highly-insulating substrate instead of bulk-GaN, capacitance reduction, and gate length scaling. Due to the tightened dimensional tolerances of a scaled device, new techniques were necessary for the gate etch and spacer fabrication. Both steps utilize an oxide planarization technique to ensure a high degree of uniformity across the device before performing an etch-back step for vertical patterning. A cross-sectional schematic and SEM image is shown in figure 12. On-wafer RF characterization is made possible by a top-side drain contact. To date, only small-signal data is available with a reported f_T of 5.7 GHz and f_max of 2.8 GHz, although further work is claimed to be necessary for optimized power-handling capabilities.

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Table 3 compares the main device metrics of GaN lateral trigate HEMTs and vertical FinFETs for RF and large-signal applications. There have been a significant number of reports on the g_m roll-off suppression and small-signal frequency performance improvements. However, there are only a few reports on the large-signal characterization. Figure 13 shows the evolution of f_T, f_max and g_m,max as a function of the gate length for different barriers. Aggressive L_g scaling, high Al-concentration barrier, and advanced gate technology (e.g. T-gate) are essential to extend the frequency limits of these devices.

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V_TH is of paramount importance for trigate GaN HEMTs, particularly for power applications where the E-mode operation is essential. Alsharef et al present one of the earliest theoretical investigations of the V_TH in Schottky-type trigate HEMTs [17], taking into account the sidewall Schottky-gate depletion and partial strain relaxation. The work also provided guidelines on choosing material properties to enable a V_TH positive shift with the increased W_Fin.

In trigate GaN MIS-HEMTs, the impact of the fin-sidewall MOS channels is crucial to device characteristics. The accumulation-mode sidewall MOS channel is inherently E-mode; however, if donor-like traps and fixed charges are introduced in the fabrication, it could become D-mode. Takashima et al reported that, without a post-etch treatment in the process, the fabricated trigate MIS-HEMTs show a lower V_TH than planar HEMTs, and their I–V characteristics are dominated by the D-mode sidewall MOS channels [149]. Son et al reported that the acceptor-like MOS traps, although leading to positive V_TH shift, but induce significantly worse SS [150]. These results suggest the importance of optimizing the fin etch and post-treatment processes to enable E-mode, high-performance trigate MIS-HEMTs.

Compact models for trigate GaN MIS-HEMTs have also been reported. Yadav et al presented a macro model that captures the parallel 2DEG and sidewall channel conductions as well as the strongly nonlinear W_Fin dependency on device characteristics [148]. A more complete set of physical models were reported by Ren et al [151], which correlate V_TH and on-state saturation current to device design parameters.

A limitation of the above models is the limited description of the off-state characteristics. In fact, physical models for device BV and off-state leakage current are still lacking. The critical role of the potential barrier height in the 2DEG fin on the device leakage current was initially studied in [56]. The lowest barrier was found to locate at the middle of the fin in the 2DEG plane, and the barrier height is determined by the trigate depletion. The barrier height was simulated in junction trigate and MIS trigate using 3D technology computer-aided design (TCAD) simulation, and it was used to explain the different off-state leakage current and BV in trigate junction HEMTs and trigate MIS-HEMTs [56].

Trigate structures have also been reported to alleviate the current collapse and dynamic R_on issues in GaN HEMTs, which is beneficial to both RF and power applications. An early study on the unpassivated Schottky-type trigate HEMTs reported the current collapse reduction, which was attributed to the reduce E-field crowding at the gate edge [53]. The dynamic characteristics of a Fin-MIS-HEMT were studied in [18], where the reduced current collapse was attributed to the lower gate leakage current and smaller V_TH shift. A recent dynamic R_on study was presented by Ren et al [19] for a trigate MIS-HEMT. It was found that the trigate device shows reduced R_on degradation due to the reduced E-field crowding as well as the faster R_on recovery owing to the quick electron emission assisted by the shallow sidewall traps [19]. Despite these encouraging results, it should be noted that the above devices are all D-mode and do not possess the gate field plates that are widely used in commercial devices; the impact of trigate structures on device dynamic performance needs to be further studied in E-mode devices with good passivation.

Alsharef et al [22] and Zhang et al [152] studied the design space of the fin geometry in lateral trigate GaN HEMTs for optimum RF performances using numerical and TCAD simulations, respectively. Simulations show that f_T and f_max of the planar device are superior over a wide range of L_G. The trigate designs exhibit smaller output transconductance (g_ds) than planar HEMTs, which is a sign of better electrostatic integrity at the expense of higher gate-to-source capacitance (C_GS). The origin of higher C_GS can be attributed to the larger intrinsic and fringing capacitances. Careful geometric optimization can maximize the RF performance and surpass planar HEMTs by minimizing C_GS while maintaining g_ds. C_GS can be minimized by reducing the fin height and fin spacing and increasing the fin width. The narrower fin can increase g_m due to enhanced gate control [153], but it can also deteriorate the linearity [152]. The reduction of fin height may lead to lower g_m and higher g_ds, which are detrimental to RF performance. Alternatively, lower C_GS can be achieved using SiN_x sidewall passivation [22].

Several groups [140, 152, 154] subsequently used small-signal equivalent circuit modeling to understand the RF performance of GaN trigate/FinFET devices. Gate parasitics extracted at high V_DS suggest that increasing V_G has minimal effect on C_GS of planar FETs, leading to a continuous decreasing trend of f_T with a high slope. Whereas for trigate case, sharper reductions in C_GS have successfully been obtained in Fin-FETs with shorter fin length (L_Fin). Moreover, the reduction of L_fin can lower the extrinsic resistances and the peak value of intrinsic transconductance, as well as improve f_T and f_max [152]. The capacitance reduction, accompanied by flatter g_m, enables an f_T boosting and makes it more uniform over V_G. Compared to planar HEMTs, the influences of trigate C_GS were also discovered to be more predominant than the ones of C_GD with higher ratios between on-state and off-state capacitances. In addition, the influence of trigate channels on C_DS is not critical, whereas the g_ds strongly depends on the L_Fin with a declining trend [154].

Compact models (e.g. MIT virtual source GaN FET [24]) calibrated against experimental devices have been used by Joglekar and Radhakrishna et al [24] to evaluate the linearity performance of the composite device. According to the modeling, the V_TH-engineering-aided g_m-compensation technique in an optimized commercial GaN HEMT can potentially yield highly linear RF GaN HEMTs with low signal distortion. These results emphasize the potential of GaN-technology in advanced high-power and high-frequency RF applications [24].

The junctionless vertical GaN Fin-MOSFETs possess very different device physics when compared to the conventional power MOSFETs, JFETs, bipolar junction transistors, and IGBTs. An in-detail tutorial has been provided in [41]. Here we provide a sketch of the interesting physics in vertical power Fin-MOSFETs.

The R_on components in vertical Fin-MOSFETs mainly consist of the source contact resistance, fin channel resistance, and drift region resistance, with a complete analytical model reported in [64]. In the fin channel, the current distribution between the bulk fin and the sidewall MOS channel strongly depends on V_G, bulk fin doping, and mobility, as well as the accumulation MOS mobility and unit capacitance. In the drift region, the current spreading needs to be considered when calculating its resistance. In experimental 1.2 kV GaN Fin-MOSFETs, the drift region was found to be the major contributor in device R_on, followed by the source contact resistance on fins and the fin channel resistance [64].

The leakage and breakdown of vertical Fin-MOSFETs are mainly determined by the potential barrier in the fin channel, which controls the carrier supply, as well as the carrier transport in the thick and lightly-doped drift region [98]. When the potential barrier is sufficiently high, the leakage is very low, and device BV is limited by the peak E-field in the edge termination region. When the potential barrier is low, a lower device BV could be triggered by high leakage current that is related to carrier transport. The leakage current in the drift region is usually dominated by the Poole Frenkel emission [37, 113] or the variable range hopping through dislocations [74, 155]. If the barrier is further lowered at high drain voltage, a large amount of injected electrons are trapped in the drift region and induce space-charge-limited conduction (SCLC), leading to a trap-mediated breakdown [98, 113]. This SCLC mechanism has also been widely reported in vertical GaN-on-Si devices [31, 71, 76, 79, 156].

While the device parameters in the fin region determine the device R_on and BV, the inter-fin region was found to be critical to the device switching performance [116, 117]. In the high-voltage hard switching, the turn-on/turn-off losses are mainly determined by the Miller plateau duration (t_M) when the entire drift region is discharged/charged. Wang et al proposed a split-gate structure, which removes the gate metal in the inter-fin region and exposes the drift layer to the field lines from the source metal (figure 14) [116, 117]. This structure allows a combination of drain-to-source current and gate current to (dis)charge the drift region and thus enables a much shorter t_M. Device-circuit mixed-mode simulations predict 38% lower switching losses in 1.2 kV GaN power Fin-MOSFETs by using the spit-gate inter-fin design [117].

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Very recently, several companies started to commercialize the GaN FinFET and trigate HEMT technologies for power applications. For example, Cambridge Electronics Inc. is commercializing a 3D-GaN technology based on lateral trigate HEMTs [157]. NexGen Power Systems Inc. is commercializing the vertical GaN Fin-JFET technology [36, 37, 158]. The active technology transfers in this field suggest numerous research opportunities and high impact. Here we attempt to present a comprehensive perspective on the challenges and research opportunities for GaN power FinFETs and trigate HEMTs.

Before discussing the challenges facing each type of devices, we point out that a common gap for many GaN FinFETs and trigate HEMTs is their thermal management, which is critical for both power and RF applications. Excellent high-temperature characteristics have been reported in a few devices, including the lateral trigate GaN junction HEMTs [56], vertical GaN Fin-MOSFETs [33], and vertical Fin-JFETs [36, 37]. However, extensive thermal management studies are still lacking in fin-based GaN devices. Note that the device-level thermal management is expected to be tightly related to the device packaging. For example, if junction-cooling is enabled by the package, the fin pitch and interfin materials could be critical factors for device-level thermal performance. In contrast, if heat is extracted from the backside of the wafer, device architecture (e.g. lateral, vertical), substrate material, and chip thickness could matter more.

6.1.1. Lateral trigate power HEMTs.

6.1.2. Vertical power Fin-MOSFETs.

6.1.3. Vertical Fin-JFETs and trigate junction HEMTs.

6.2.1. Lateral trigate RF HEMTs.

6.2.2. Vertical RF FinFETs.

Besides power and RF applications, several GaN fin and trigate based transistors have been proposed for digital applications. For example, Im et al demonstrated the AlGaN/GaN Ω-shaped fin-based MIS-HEMT, in which the gate not only wraps around the fin top and sidewalls but also covers part of the fin foot [177]. With the improved gate controllability, a SS of 62 mV dec⁻¹ and an on–off ratio over 10¹⁰ were reported. Xu et al proposed a sub-60 mV dec⁻¹ AlGaN/GaN FinFET by simultaneous activation of 2DEG and sidewall MOS channels [178]. These results show great prospects of developing GaN FinFETs and trigate HEMTs for digital applications, as well as the potential 'full GaN FinFET' platform where the GaN FinFET based ICs are monolithically integrated with the GaN power FinFET or the GaN RF FinFETs to allow an unprecedented level of integration and system performance [41].

Device scaling is crucial for digital devices, and it has not been well explored in GaN FinFETs and trigate HEMTs. Thanks to the wide bandgap of GaN, ideal GaN devices would expect much lower band-to-band tunneling current as compared to the Si counterpart, therefore holding enormous promise for transistor scaling. However, in most of today's experimental GaN transistors, device metrics are not determined by the intrinsic GaN material properties, making the study of scaling quite difficult. For example, the leakage current in AlGaN/GaN HEMTs is largely dependent on the passivation layer, buffer layer, and AlGaN barrier. The electron trapping/detrapping in these layers result in the time-response of device parameters, such as dynamic R_on [179] and dynamic BV [180]. Several recent works have explored the impacts of electron trapping/detrapping behaviors on the performance of GaN FinFETs and trigate HEMTs using the low frequency noise measurement [181–183]. Some initial studies on the scaling effect in GaN FinFETs have also been reported [184]. These results provide valuable preparations for the future investigations of highly-scaled GaN FinFETs and trigate HEMTs for digital applications.