A Study on Design and Optimization methods in Latch Type Comparator

The current state-of-the-art communication systems require analog-to-digital converters (ADCs) to sample the analog signals in digital representation at high speed and low power consumption with very high accuracy. Performance demand for ADCs directly promote the advancement of their basic component - the comparator. The traditional Strong-Arm dynamic comparator has been widely accepted for its fast decision, but it is limited by its significant voltage headroom and kickback noise. The double-tail latched dynamic comparator mitigates the aforementioned problems by allowing separate stages for the pre-amplifier and the latch so that it can have near- operation. However, energy consumption and propagation delay are still problems to be solved. In this article, we present a review of the recent improvements for the dynamic comparator architecture. The advantages and disadvantages of these techniques are also illustrated with simulation and measurement results.