Germanium epitaxy on silicon

The first attempt to realize Ge epitaxial growth on Si was made by Kasper et al [15]. They reported the short period one-dimensional Ge/Si_1−xGe_x (0 < x < 0.15) superlattice deposition on silicon, and their experiments show that mismatch above 8 × 10⁻³ favors growth by 3D nucleation.

For heteroepitaxial films deposited beyond the critical thickness, misfit dislocations are inevitably generated at the substrate/film interface and typically propagated toward the film surface as threading dislocations. Furthermore, 3D island-like growth leads to high surface roughness, high densities of threading dislocations can significantly deteriorate optoelectronic properties of devices. For example, it will increase the leakage current of a rectifying junction and thus reduce the efficiency of photodetectors. High surface roughness, similarly, will cause difficulties in process integration.

Because of the 4.2% lattice mismatch between Ge and Si, Ge epitaxial layers on Si substrates have high threading dislocation density (TDD) and surface roughness. In order to suppress the 'island-like' growth and surface fluctuation, various methods have been proposed to realize low TDD and smooth surface. A fully relaxed thick graded Si_xGe_1−x layer is often used as a template to match the lattice constant of the underlying layer with that of Ge. Because the surface energy of Si_xGe_1−x is lower than that of Si, and the mismatch between Si_xGe_1−x and Ge is smaller than that of Si and Ge, introduction of graded buffer will result in 2D pseudomorphic growth of upper layers in the Franck–van-der-Merwe growth mode. The compositional gradient of the buffer layer, the misfit dislocation nucleation temperature and the strain level in the structure will contribute to TDD and surface roughness, so optimization of the buffer step grading rate and growth temperature is indispensable [16, 17]. If an intermediate chemical mechanical polishing step is implemented, a low TDD of 2.1 × 10⁶  cm⁻² can be realized [18]. The Sb surfactant mediation technique has also been reported combining the thick graded buffer to achieve very low TDD (5.4 × 10⁵ cm²) and the smooth surface (3.5 nm) in Ge epitaxial layers. One monolayer Sb is found to have an effect to relieve stress caused by large mismatch between Si and Ge [19]. Since the thickness of the graded buffer layer can reach the micrometer order, such a thick graded Si_xGe_1−x layer is complex for material structure and growth control. An ultrathin buffer layer is therefore required from the manufacturing point of view. Nakatsuru et al [20] reported that using an ultrathin (on the order of 10 nm) Si_xGe_1−x buffer layer is really an effective way to deposit pure Ge epitaxial films on Si with very low TDD and smooth surface (root mean square = 0.44 nm). Their results indicate that Si_xGe_1−x buffer layers with two distinct interfaces are effective to absorb strain released by the Ge epitaxial layer upon relaxation and to reduce threading dislocations.

Low temperature (LT) and HT two-step growth of Ge on Si substrates is another practical method frequently reported in recent years to realize high quality Ge flat films. A two-step process means thick relaxed HT Ge layers epitaxially grown on silicon after insertion of a LT-grown Ge buffer layer [21]. In this technique, the low-temperature Ge buffer layer is able to prevent the 3D nucleation of Ge. The LT layer, also called as the Ge seed layer, is ultrathin (30–50 nm), deposited at 300–400 °C to relieve misfit stress and maintain a smooth surface by limiting the mobility of Ge adatoms at lower temperatures. The HT layer, however, is a thick relaxed film grown at 600–700 °C for faster growth rate and higher crystallization quality. Normally the two-step growth approach is combined with thermal annealing to achieve a smooth surface and low defect density. There are several thermal annealing methods reported, including cyclic thermal annealing and multiple hydrogen annealing for heteroepitaxy [22]. Kimerling's group [23] reported their results of the Ge epilayer fabricated with the two-step UHV/CVD process combined with cyclic thermal annealing. In their samples, a pure Ge seed layer as thin as 30 nm was deposited at 350 °C, then the furnace temperature was raised to 600 °C and 1 μm of HT Ge was grown on the seed layer. Finally, the wafers were cyclic annealed between a high annealing temperature (T_H = 980 °C per 10 min) and a low annealing temperature (T_L = 780 °C per 10 min) for ten cycles. The cyclic temperatures of T_H and T_L were optimized to maximize the dislocation velocity. The measured TDD was 2.3 × 10⁷ cm⁻².

Selective epitaxial growth (SEG) techniques, or called epitaxial necking techniques, have already found many applications in semiconductor heteroepitaxy and device fabrication. The techniques involve substrate patterning and epitaxial lateral overgrowth (ELO). SEG has been extensively used recently in the development of GaN devices [24]. In contrast to conventional lattice mismatched growth on planar substrates, SEG of Ge-on-Si is a kind of area dependent multi-step deposition process; it restricts the Ge epitaxial growth in small patterned regions (< 40 μm), and dislocations can glide to the edge of the mesas and annihilate [25, 26]. Small mesas on silicon are formed by etching through dielectric mask layers of SiO₂ and reaching the surface of Si substrates. The dielectric SiO₂ is chosen as a mask layer because the reaction byproducts of GeH₄ or Ge with SiO₂ are volatile GeO₂, which are not stable at the Ge growth temperature (600–650 °C), resulting in the impossibility of poly-Ge nucleation on the SiO₂ layer or side wall. Ge epilayers can therefore be selective grown on the patterned windows [27]. The mechanism of dislocation density reduction in the SEG process is analogous to that of bulk Si Czochralski crystal growth where the seed crystal is first necked to eliminate defects before the boule is pulled. As threading dislocations are not parallel to the growth directions, they are probably arrested by oxide sidewalls, so the SEG process can eliminate defects originated in the seed window interface. Thus in the upper part of the Ge film, especially in the ELO region, TDD will be greatly decreased. Patterned window sizes, the aspect ratio (AR) of the windows, as well as SEG growth technology have a combined contribution to the low-defect density Ge on Si. It is worth mentioning that ELO typically needs much finer patterns than regular SEG. For low defect density, the growth region is often chosen as submicron wide, and the AR is usually much larger than 1.

In the author's lab, a defect density comparison has been made by growing a Ge film on bare Si substrates and on a 70 nm-diameter Si pit with SiO₂ windows; the result is shown in the transmission electron microscopy (TEM) image of figure 4 [28]. Ge grown on planar Si substrates with the typical two-step process has a threading density larger than 10⁸ cm⁻², as shown in figure 4(a). In contrast, defects including threading dislocations and stacking faults originated in the interface of the Ge film and the strained Si_1−xGe_x seed can be rarely found in the SEG region, as shown in figure 4(b). The coalescence process will probably result in twins and stacking faults in the ELO region. Through etch-pit-density counting and TEM observation, the average of the defect density of SEG Ge films is two orders of magnitude lower than the directly grown Ge sample.

Zoom In Zoom Out Reset image size

SEG windows are normally fabricated with dry etched or wet etched patterned thermally grown SiO₂ thin films. Substrate patterning can be performed by conventional lithography technology. But due to the relatively high cost of the lithography process and its limitations to achieve the nanoscale window size, several lithography-free methods have been proposed in recent years to realize nanoscale selective Ge growth. Li [29] reported high quality Ge SEG with nanoscale 'seed pads'. The seed pads were 7 nm wide uniform tiny regions formed by reaction of Ge adatoms with a 1.2 nm thick chemical SiO₂ layer and touchdown on Si substrates. The Ge selectively grew on the seed pads rather than on SiO₂, and the seeds coalesced to form the epilayer. Another lithography-free substrate pattering method uses an ultrathin free-standing porous alumina membrane (PAM) as an etching mask [28]. PAM is fabricated by a typical two-step electrochemical procedure using high-purity aluminum foil as raw material; it has uniform ordered hexagonal-aligned patterns, with controllable pore size and AR. Freestanding PAM can be used to transfer nano-patterns onto Si without introducing any contaminants. The PAM with 60 nm pore size and 300 nm thickness (AR = 1 : 5) can be used to obtain 20 nm patterns on Si by utilizing the shadow effect during the reactive ion etching process. Figure 5 shows TEM images of selective Ge films grown on 20 nm regions and coalesce to form the epitaxial layer, no defects can be observed in the windows, while rare coalescence defects exist in the ELO regions. From the defect-free growth results we can fully verify the theoretical prediction of Luryi and Suhir [30], who proposed in 1986 that if the Si substrate is patterned with tiny regions less than 20 nm, the critical thickness of Ge deposited in such small windows can be extended to infinity, which implies that Ge of arbitrary thickness can be epitaxial grown on Si with no dislocations.

Zoom In Zoom Out Reset image size

Biaxial tensile strained Ge epitaxial layers on Si have potential applications in integrated optoelectronics. Because of strain-induced band structure modification, Ge is likely to transform from the indirect bandgap to the direct bandgap semiconductor with about 1.75% biaxial tensile strain. Furthermore, tensile strain raises the light-hole band, resulting in the increment of optical gain for high injection. Tensile strain in Ge is not only beneficial for optical devices, but also good for electrical devices. Both the electron and the hole mobilities greatly increased under in-plane biaxial tensile strain.

Kimerling's group in Massachusetts Institute of Technology reported their exciting results of the first optically pumped Ge-on-Si laser operating at room temperature in 2010 [31]. The Ge epitaxial layer was fabricated with the SEG process. When the thickness of the epilayer exceeded 200 nm, the Ge fully relaxed at the growth temperature of 650 °C, but a thermally induced tensile strain of 0.24% was accumulated upon cooling to room temperature. A phosphorous doping level of 1 × 10¹⁹ cm⁻³, as well as biaxial tensile strain in the film allowed enhanced light emission from the direct gap of 0.76 eV. An electrically pumped germanium laser was subsequently reported by the same research group 2 years later [32]. Their results have no doubt attracted more attention on strained Ge film growth [33, 34].

However, the thermally induced tensile strain process resulting from the thermal expansion coefficient difference has some limitations. Firstly, it is difficult to precisely control the strain state during the deposition procedure. Secondly, the predicted maximal tensile strain in the Si/Ge system is only 0.3%, far below the predicted value required for direct band gap transition [35]. Aside from thermally induced strain, there are several other methods reported in recent years to achieve controllable and tunable strained Ge films. Ge growth on a large lattice-parameter substrate such as InGaAs or GeSn buffer layers may cause tensile strain in the upper films. Fang et al [36, 37] reported that up to 0.25% tunable tensile strained Ge epitaxial films had been realized using a fully relaxed Ge_1−ySn_y (y = 0.015–0.025) layer as a buffer. As the Sn incorporation into Ge was facilitated by a quite low temperature growth step to suppress Sn surface segregation, the GeSn alloys were therefore deposited on Si at a temperature around 350–380 °C. After cyclic annealing to relieve the residual strain, the buffer layer was found to have a planar surface and lower than 10⁶ cm⁻² threading defect density. The subsequent Ge epilayer was deposited in a manner to enable built-in pseudo surfactant growth behavior. Both measurements of x-ray diffraction reciprocal space maps and Raman spectrum confirmed the strain level of the Ge epilayer. Huo [38] used relaxed step-graded In_xGa_1−x As layers as large lattice constant buffers to provide tensile strain; the graded In_xGa_1−x As layers were deposited on GaAs substrates with a relatively high In concentration of up to x = 0.40. About 2.3% in-plane biaxial tensile strained thin Ge epitaxial layers were achieved with smooth surfaces and low TDD (in the 10⁷ cm⁻² range). The strong photoluminescence (PL) of the highly tensile strained Ge layers suggested that a direct band gap semiconductor had been achieved.

As the Si/Ge heteroepitaxial system has a large lattice mismatch, when the thickness of the initial layer exceeds the value of the critical thickness, Stranski–Krastanov (S–K) growth occurs and energy-quantized self-assembled islands, or called QDs, are formed on the substrates. Unlike flat Ge epitaxial layer growth, the driving force of the 3D island formation is the relief of the elastic strain accumulated in the Ge film due to the lattice-mismatch between Ge and Si. It is found that S–K growth of Ge on Si (100) is initially dislocation free [10] when the island height is below the S–K critical thickness. Furthermore, the quantum confinement effect on excitons in Si/Ge nanocrystals will allow the indirect to direct bandgap optical transition without phonon emission or absorption, offering opportunities for the development of optoelectronic devices integrated on silicon.

Ge/Si QDs exhibit a typical type-II band alignment. The large valence band offset gives rise to an effective confinement of holes within Ge islands while electrons are mostly present in the surrounding Si close to the interface [39]. The dot size, density, shape, Ge content in the dots and even the dot site can have different influences on the dot band structure, resulting in multi-modification of the photoresponse of QD-based infrared devices such as photodetectors and electroluminescent devices. Indeed, fabrication of defect free, as well as dot size, shape and site precisely controlled Ge self-assembled QDs is indispensable to develop novel devices in the telecommunication wavelength.

A conventional Stranski–Krastanov growth starts with the nucleation of 3D islands, and the surface migration phenomenon plays an important role in the 3D island evolution. Germanium 3D growth under thermal equilibrium (with high surface diffusivities or low deposition rates) and kinetically limited (in the form of low surface diffusivities or high growth fluxes) conditions will result in different island morphologies. Growth corresponding to the thermal equilibrium state shows the island size a stable Boltzmann distribution, while kinetic growth induces a coarsening process to take place: some islands continue to grow while others shrink and disappear. The uncontrolled coarsening process often leads to low island density and bimodal distribution of the island size in a wide range of growth conditions, shown in figure 6. Unimodal distribution of Ge islands can be achieved by optimizing growth parameters such as substrate temperature, deposition rate, Ge coverage, as well as annealing temperature and time [40]. Besides size distribution and island shapes, values of the Ge island dimension and island density are also key parameters for application to the actual devices. The quantum confinement effect requires the horizontal and vertical dimensions of isolated Ge islands less than its effective Bohr radius, and the lateral coupling effects between adjacent dots require Ge islands with a high areal dot density of more than 10¹¹ cm⁻². According to theoretical calculation of 3D confinement of an electron–hole pair in an infinite spherical potential, the effective Bohr radius of Ge is estimated to be 24.3 nm [41]. In order to obtain strong confinement of electrons and holes in both horizontal and vertical directions, Ge dots with the lateral size less than 10 nm and heights shorter than 5 nm are required for optoelectronic device applications. Self-assembled Ge dots based on S–K growth mode on silicon usually have a multifaceted dome shape with relatively large base dimensions and broad size distribution of 50–100 nm, short heights of 5–10 nm and a low dot density of 10⁹–10¹⁰ cm⁻². Such self-assembled dots have poor lateral carrier confinement, and the lateral coupling between dots is also weak.

Zoom In Zoom Out Reset image size

Considerable efforts have been devoted to control the size uniformity, density and positioning of self-assembled nanostructures in recent years. Among these methods ever reported, the Si surface covered with an ultrathin oxide layer [42] is particularly a promising candidate as a substrate for growing Ge QDs with sufficiently high density and small size. Si(111) with a 1.5 nm thick chemically oxidized SiO₂ layer was used as a substrate, and Ge of an equivalent thickness of 3–13.5 nm was deposited directly on a SiO₂ layer at 400–700 °C with MBE growth. Under optimized growth parameters, small (10 nm), uniform and densely packed (3.5 × 10¹¹ cm⁻²) QDs were obtained. The high uniformity in the dot size and the high density of dot distribution were ascribed to the dense nucleation windows formed by reaction between Ge adatoms and ultrathin SiO₂.

The growth of self-assembled QDs performed on planar substrates leads to random nucleation of dots. Thereby size control and exact placement of dots are hard to achieve. More recently, selective growth of islands in the patterned nanoscale region, or pattern guided growth, has been proposed and has attracted considerable attention. Patterned assisted QDs with precisely controlled site placement, size distribution and dot density have been realized in various nanostructures, including buried dislocation networks [43], stripe mesas [44], 2D hexagonal pits array [45] and lithography-based optical interference patterns [46]. Due to ordering of growth patterns, 2D and 3D QD arrays with perfect site periodicity and size distribution can be obtained provided that the growth parameters are optimized. Lateral and vertical coupling of QDs in ordered dot arrays will probably lead to some unexpected phenomena. Grützmacher et al [47] employed the extreme ultraviolet interference lithography (EUV-IL) technique at a wavelength of 13.5 nm to fabricate prepatterns on Si substrates. EUV-IL allowed an excellent precision of pattern control in the subnanometer regime; it also allowed for the formation of patterns with less than 30 nm periodicity. Nearly perfect three-dimensionally ordered SiGe QD crystals with small dot sizes and periods both in lateral and vertical directions had then been grown by MBE, as shown in figure 7. Temperature-dependent PL spectra showed the strong PL line centered at 746 meV at low temperatures, the PL line shifted to higher energies while increasing the temperature and the PL persisted up to room temperature. The relatively strong PL in 3D Ge QD arrays was attributed to precisely located dot cites, uniform size distribution, low defect densities, as well as excellent crystalline perfection.

Zoom In Zoom Out Reset image size

With the rapid development of on-chip optical interconnects, the efficient silicon light source is one of the most important photonic integrated devices on the Si platform. Among a lot of solutions to light emitting devices proposed lately, Ge self-assembled QDs are considered as effective candidate materials due to compatibility with CMOS technology. However, the light emission efficiency from Ge dots is still insufficient and the spectrum purity is poor. Embedding Ge self-assembled QDs into microcavities and microdisk resonators has been reported, and strong room-temperature resonant PL from microcavities [48], as well as current injected light emitting from the microdisk [49] have been observed, respectively. Figure 8 shows the schematic structure of the fabricated current-injected Si-based light emitting device. Stacks of Ge self-assembled QDs and silicon spacer layers were embedded into a Si microdisk resonator on SOI with a vertical p–i–n junction for current injection. Under forward bias, three whispering gallery mode resonant electroluminescence (EL) peaks located at 1.191, 1.241 and 1.296 μm were clearly seen at room temperature in figure 9. They are verified as transverse magnetic (TM) polarized modes with orders of TM0₂,₂₇, TM0₃,₁₂ and TM0₃,₁₁, respectively. The room temperature EL peaks might be originated in current injected light emission of Ge QDs in the Si microdisk resonator, but the possibility that the peaks are from the defects in Ge layers is not precluded; further measurements to clarify the luminescence origin are needed. The result showed a possible route to develop a Ge QD-based integrated light source on the Si platform.

Zoom In Zoom Out Reset image size

Zoom In Zoom Out Reset image size

It is worth noting that the intermixing effect cannot be ignored when growing Ge dots on silicon substrates. During the deposition process, Ge will intermix with the substrate to form a layer of strained SiGe alloy. Ge islands nucleating and growing on such alloys will have a substantially different composition from the alloy layer [50]. Such stress-induced segregation consequently affects the optoelectronic properties of devices based on Ge dots.