Table of contents

High voltage lateral DMOS transistors are very difficult to model due to the complex structure. As a result of complexity and the range of variation in transistor structure no general LDMOS model exists. Standard SPICE models of MOSFETs, JFETs together with a resistor have been used in the sub-circuit model. Self-heating effects have been included in a specially design unit. The model shows good overall accuracy.

The breakdown mechanism of constant-voltage stress in MOSFETs has been investigated. The results show that the transient evolution of stress current dominates the breakdown mechanism of the thin oxide. Due to the stress current decreasing with time induced by trapped charges, the trapped charge increases with stress time, i.e. proportional to T_s^0.4. As the results indicate, the relation between trapped charges and time-to-breakdown, the trapped charge generation rate could be obtained. By investigating stress-induced degradations, the impacts of positive constant voltage stress and negative constant voltage stress for device degradation are also analyzed and compared.

In this paper, we present numerical studies of the high frequency performance of a submicron MOSFET in 2H-, 4H- and 6H-SiC. The studies are based on simulations where commercial two-dimensional drift-diffusion and hydrodynamic carrier transport models have been used. The results have been compared with those obtained from full band Monte Carlo simulations. The Monte Carlo carrier transport model is based on data from a full potential band structure calculation using the Local Density Approximation to the Density Functional Theory. In 6H-SiC the bulk transport properties in the direction perpendicular to the c-axis, are slightly lower than in 2H- and 4H-SiC. However, in the direction parallel to the c-axis the transport properties are considerably less favourable than in the other two polytypes. The effects of these differences, on surface mobility, device performance and carrier energy, have been studied.

We propose a multi-resurf SOI (Silicon-On-Insulator) LDMOS (Lateral Double-diffused MOSFET) structure with recessed gate to improve the breakdown voltage (BV) and on-resistance (R_on). Recessed gate and trenched drain are employed to obtain uniform drift current. The characteristics of the proposed LDMOS are verified by the two-dimensional process simulator TSUPREM-IV and the device simulator MEDICI. The numerically calculated R_on of the proposed LDMOS is 0.2487 Ω-mm² at BV = 214 V, yielding 70% improvement of R_on in comparison with that of the conventional LDMOS at the same BV. The proposed LDMOS shows better trade-off characteristics than the conventional one.

The effect of epitaxial growth induced surface roughness on the electrical properties of Si/Si_1-xGe_x channel pMOSFETs was investigated. Grown by chemical vapour deposition for selective epitaxy, the surface of the channel region was considerably rougher for the channel structures with a buried Si_1-xGe_x layer with x = 0.16-0.20 than for those with only Si. Although the increased surface roughness, determined by means of atomic force microscopy, resulted in a doubled interface charge density, the density remained low at the mid-10¹⁰ cm^-2 eV^-1 level. Furthermore, identical transconductance values were found for the MOSFETs with and without the Si_1-xGe_x layer. Since the inversion charge was confined predominantly within the surface Si layer, the surface roughness apparently had little effect on the transconductance. However, the subthreshold slope was found to increase from 78 mV/decade for the Si-only channel MOSFET to 105 mV/decade for the Si/Si_1-xGe_x channel MOSFETs.

With some newly developed procedures it has become possible to grow ultra thin oxides on silicon in a series of steps operated at low temperature to achieve a good control of the interface properties. The growth mode is linear between 0.3 nm and 10 nm with a precision of one "atomic" layer (0.25 nm) pr. step. This includes the thinnest possible oxide-like layer that can be grown (0.3 nm) which has a non-uniform vertical chemical composition. The structural and chemical characterization of the oxides grown is done with synchrotron-induced photoemission, which also allows one to monitor the silicon band bending. To show the usefulness of these oxides for practical devices, the electrical properties of the interface and the charges in the oxide must be made accessible to measurements. An in-situ characterization is possible just after growth through photoemission, by depositing and contacting a metal (here silver) film on top of the oxide. In the conventional MOS capacitor model the silicon surface potential (band bending) with zero external bias should be equal to the negative of the "flat band voltage". Deposition of silver is also used to detect if the oxide is not covering the surface uniformly, in which case there would be significant local variations in the band bending where silver gets in contact with clean silicon.

Metal-oxide-semiconductor (MOS) structures in which the oxide has been implanted by silicon ions are presented and investigated by electrical measurements. Two different designs of the structures have been studied and the reasons for leakage and instability of current have been found. Improvements of the electrical properties of the MOS structures are presented.

Polycrystalline silicon (poly-Si) thin film transistors (TFT's) have been fabricated by ion beam sputtering (IBS) and XeCl excimer laser annealing (ELA) at 100°C. The amorphous silicon (a-Si) films to be crystallized into poly-Si were deposited by IBS and they had very low argon content (less than 1 at. %). No explosive gas evolution was observed during the instantaneous crystallization of the a-Si film by ELA, while the a-Si film deposited by conventional RF/DC magnetron sputtering or PECVD underwent severe silicon film ablation due to the explosive argon or hydrogen evolution during ELA. The poly-Si TFT fabricated by IBS and ELA exhibited an ON/OFF current ratio of 4 × 10⁴. The measured sheet resistance of the n⁺-doped source/drain resistance was less than 700 Ω/sq. and the output I_D-V_DS curves showed that good ohmic contacts were formed

Self heating effects in silicon-on-insulator (SOI) high power Vertical Diffused MOS (VDMOS) transistors have been investigated by electro-thermal simulations. Unlike other conventional VDMOS devices, here we work on a modified VDMOS transistor with drain contacts at the surface. In this work we study two different aspects of this transistor namely: (1) Effect of self heating on the device performance and (2) effect of the elevated temperature on the device characteristics. Our simulation results indicate that the temperature distribution is concentrated at the drift region under the gate area and spreads down toward the drain area. The self heating effect gives a notable effect on our newly proposed VDMOS in the on-state (when Vg > Vt), and the breakdown point decreases. As we increase the ambient temperature the breakdown point decreases further.

Relaxation of SiGe layers grown selectively or non-selectively on oxide-patterned substrates using reduced pressure chemical vapor deposition was investigated. The influences of the buffer layer, the polycrystalline layer on the oxide and the opening size on the critical thickness for relaxation of SiGe layers have been studied in detail. High resolution reciprocal lattice mapping, atomic force microscopy and Normanski optical microscope have been used as the main characterization tools.

The growth of heterojuntion bipolar transistor structures using chemical vapor deposition has been investigated. Generation of defects in selectively or nonselectively grown collector layers using arsenic as the dopant has been studied. Minimizing the defect density in SiGe base layers by optimizing the growth rate has also been investigated in detail. High resolution reciprocal lattice mapping, atomic force microscopy and secondary ion mass spectrometry have been used as the main characterization tools.

Stacked gate nonvolatile memory cells were tested with a molybdenum gate BeCMOS process. Writing and erasing with Poole-Frenkel conduction and writing with drain avalanche injection are characterised. The measured endurance was found to be more than 10 000 cycles and the estimated retention more than 10 y. These properties are comparable to polysilicon gate devices.

RF behavior improvement suggestions to the MOSFET models were studied using mostly BSIM3v3 and Philips MOS Model 9 (MM9). Different substrate resistance model topologies were compared. Also distributing the gate, source and drain resistance was studied as well as the use of an additional capacitance C_g in parallel with the gate resistance. The basis for the AC improvement studies is an accurate DC and AC extraction of the basic device model. Scalable MOSFET parameter extraction was done using the APLAC circuit simulator and by programs written with APLAC description language. The device characterization set included gate widths down to 0.4 μm. The parasitics of the pads and wires were carefully removed utilizing de-embedding techniques. A gate resistor was used for both MM9 and BSIM3 and also C_gb0 zero-bias capacitance was added to MM9.

A new vertical channel LDMOS, which decreases the on-resistance without sacrificing the breakdown voltage, is proposed and verified by numerical simulation. In the proposed vertical channel LDMOS, the channel and the drift region are located in the trench between the source and the drain. The total cell pitch of the proposed device is decreased to 4 μm which is about a half of the conventional LDMOS when the breakdown voltage is 60 V. Simulation results show that the on-resistance is 0.45 mΩ · cm² for a 60 V breakdown voltage which is very low compared to that of the conventional LDMOS.

Calculation of three-dimensional recombination effects in homogeneous silicon wafers is performed. The current continuity equation for minority carriers with surface recombination boundary conditions is solved in cylindrical coordinates. The two most important three-dimensional recombination effects are discussed. Lateral diffusion of minority carriers gives rise to a characteristic decay inversely proportional to time. Shell surface recombination should be taken into account when measuring within the minority carrier diffusion length from the wafer edge. The discrepancy between the one-dimensional and the three-dimensional models is discussed.

A new collector technology intended for an integrated high-speed SiGe heterojunction bipolar transistor (HBT) is reported. The collector was fabricated by selective epitaxial growth (SEG) using chemical vapor deposition at 770°C under reduced pressure (20 torr) using SiH₂Cl₂ as silicon precursor and PH₃ as n-type dopant source. Chemical-mechanical polishing (CMP) was applied to the overgrown SEG collector in order to achieve a smooth surface in level with the surrounding oxide. Finally, a SiGe base doped with boron was deposited using non-selective epitaxial growth (NSEG) at 650°C. The topography of the collector is inspected after each process step by atomic force microscopy and the topography of the completed collector/base stack indicates that this structure is promising for fabrication of the emitter window. A further advantage with the CMP procedure is the elimination of phosphorous segregation as evidenced by secondary ion mass spectroscopy of the base-collector stack.

For extracting the parasitic resistances of GaAs MESFET's a method presented by P. Debie, L. Martens and D. De Zutter has been used. The method is based on three simple DC measurements and the resistance values are received through numerical iterations. It is illustrated in this paper that the parasitic resistances of MESFET's can be calculated analytically using the given method. Therefore, numerical iterations are avoided and the extraction becomes faster. The resistance measurements show that the method is sensitive to the accuracy of the measured voltages. The repeatability can be increased by data processing the measured data.

When on-wafer high frequency characterization of MOSFETs is performed, influences of the substrate coupling arising from metal bonding pads have to be considered in order to de-embed the characteristics of intrinsic transistors at high frequencies. In this work we examine different metal pad configurations used for the de-embedding procedure, i.e. pad compensation. Lumped circuit models are used to account for the effects of the metal pads and the substrate beneath. Good agreement is found between the Y-parameters of the proposed models and the measured data up to 18 GHz. With the guidance of the models we discuss designs of metal pad configurations, substrate resistivity, substrate isolation and layout of MOSFETs in order to improve the accuracy of the pad compensation.

Silicon carbide MESFET devices are well suited for high speed, high power and high temperature electronics due to high saturation velocity, high critical electrical field, good thermal conductivity and large band-gap. Optimization of a high performance device demands a substantial number of numerical simulations, where several different design parameters have to be investigated thoroughly. In this work, we optimize the geometry of lateral MESFETs for maximal unity current-gain frequency (f_T) using iterative 2-dimensional simulations. We also present a comparison of performance for individually optimized devices, realized with lithographic resolutions ranging from 0.2 to 2 μm in different SiC polytypes.

GaN grown by MBE is characterised and compared with a high-quality MOVPE-grown GaN-sample. The concentration of oxygen in the MBE-material was found to be 3.1 × 10¹⁸ atoms/cm³ compared to 4.1 × 10¹⁸ atoms/cm³ for GaN grown by MOVPE. The MOVPE-sample had twice as high carbon concentration as the MBE-grown layer. GaN grown by MBE shows high concentrations of unintentional arsenic, 1.1 × 10¹⁸ atoms/cm³, and boron, 3.0 × 10¹⁷ atoms/cm³, where the boron incorporation shows a dependence on the power of the plasma source. Using XRD, the Ω-rocking curve FWHM of the symmetric [0002] and asymmetric [10 5] reflections for the MBE-material were above 1200 arcsec as compared to about a factor of three lower values for GaN grown by MOVPE. Photoluminescence emission from both materials shows a strain-shifted shallow donor bound exciton at 3.48 eV and a shallow acceptor with LO phonon replicas at 3.27, 3.18 and 3.09 eV, respectively. Emission due to a 2DEG was seen from the MBE-sample. Three unknown peaks were seen at 2.82, 2.99 and 3.42 eV from GaN grown by MBE.

A novel approach to create radioactive, substitutional and interstitial ⁵⁷Fe atoms in silicon at elevated temperatures is reported, which allows for Mössbauer studies of the emitted 14 keV γ-radiation. Radioactive ⁵⁷Mn ⁺ (T_1/2 = 1.5 min) ions have been implanted at the ISOLDE facility at CERN with 60 keV energy to fluences <10¹²/cm² into silicon crystals held at 400–800 K. As a result of the annealing of the radiation damage during the ⁵⁷Mn lifetime, the Mn atoms are found on substitutional lattice sites. In the subsequent decay of ⁵⁷Mn to the Mössbauer state of ⁵⁷Fe an average recoil energy of 40 eV is imparted on the daughter atom. This leads to a relocation into interstitial sites for the majority of the Fe atoms, the remainder remains on substitutional sites. Thus the Fe electronic and vibrational properties on both lattice sites can be studied. A few diffusional jumps of interstitial Fe during the lifetime of the Mössbauer state (T_1/2 = 100 ns) have been observed by a broadening of their Mössbauer line at >450 K. At the highest temperatures a new line occurs in the spectra, the possible nature of this line will be discussed.

The charge carrier lifetime in iron contaminated boron doped silicon wafers was determined by surface photovoltage, SPV, and microwave photoconductive decay, μPCD, techniques. Our results show that the charge carrier lifetime in boron doped silicon wafers depends on the boron concentration when the lifetime is limited by iron-boron pairs.

We apply time-resolved photoluminescence with 1.5 μm spatial resolution for characterization of carrier trap distribution in semi-insulating Ga_0.51In_0.49P:Fe layers regrown around GaAs/AlGaAs circular vertical cavity surface emitting laser mesas using hydride vapour phase epitaxy. The carrier trapping times are in the range from 10 to 15 ps and quite uniformly distributed throughout the burying GaInP:Fe layer, suggesting that the layer is semi-insulating everywhere. Simulations show that, in addition to the Fe dopants, the layer contains other, unintended carrier traps. The photoluminescence spectra reveal that the regrown GaInP:Fe material has several distinct regions with different band gaps. This is attributed to differences in the In/Ga composition and/or CuPt ordering of the GaInP.

A fabrication process to realise very short period grating structures in silicon has been developed. The period of a first order Bragg grating operating at a wavelength of 1.55 μm is 230 nm. The grating structures have been directly written to PMMA resist using an electron beam pattern generator. The grating pattern in PMMA is transferred into a silicon dioxide masking layer using plasma etching and into silicon using an inductively coupled plasma etching. An etch depth of 0.6 μm has been achieved. The integration of the grating structure with a large core size silicon-on-insulator rib waveguide is presented.

A solar cell process with two mask levels has been developed and the fabrication process is described in this paper. Texture and selective emitter are implemented with one lithographic step and the second mask level is needed for front contact grid formation. Texturing has been realized with an inverted pyramid structure, which has proven to be effective in reflection reduction. A solar cell efficiency of 16.4% has been achieved with the simple two mask level process.

Stimulated emission in homoepitaxial GaN layers was studied by measuring luminescence spectra in backward and lateral configurations at room temperature. The dynamics of the spectra was investigated under excitation of carriers with different excess energies and by changing the excitation intensity. Two bands of stimulated emission caused by recombination in electron-hole plasma at the sample surface and in the dense exciton system located deeper in the layer were simultaneously observed. This is explained by large diffusion lengths for carriers (excitons) and low density of structural defects and cracks. Influence of carrier heating on the stimulated emission is demonstrated.

Photoluminescence at 1.54 μm from Er in Si has received much attention because of the possible uses in optoelectronics. Incorporating Er in porous silicon (PSi) might lead to efficient luminescence at this wavelength. We have prepared porous silicon layers by anodic etching of p-type silicon single crystal wafers in an electrolyte consisting of hydrofluoric acid and ethanol. Thereafter Er has been incorporated into the PSi layers by immersing the PSi layers in a solution of ErCl₃ in ethanol in an electrochemical cell with positive Pt electrodes and the Si wafer as the negative electrode. The distribution of Er and Cl in the porous layer has been examined using a scanning electron microscope with an energy dispersive X-ray spectroscopy system. After immersing the PSi layers in the ErCl₃ solution it is observed that both Er and Cl are present in the porous silicon layer. These elements are also present in the PSi layer for samples prepared with no bias or current flowing in the electrochemical cell and the bias seems to have no significant effect on the amount or distribution of the elements. After annealing the samples at 800°C for 60 min in a 20% O₂/80% N₂ atmosphere practically all the Cl has escaped from the PSi layer while much Er remains.

Photonic crystal (PC) etching in InP/GaInAsP using two different processes, namely Ar/CH₄/H₂ based Reactive Ion Etching (RIE) and Ar/Cl₂ based Chemically Assisted Ion Beam Etching (CAIBE), is investigated in detail and the results are compared. Our goal was to identify the limits of the processes and to optimize process parameters for PC etching. With Ar/CH₄/H₂ RIE, we obtained PC holes with smooth profiles. However, the etch depth depends strongly on the hole diameter; the smaller the hole diameter, the smaller is the obtained hole depth. This together with the obtained hole profiles indicates the presence of an etch-limiting mechanism and is attributed to inefficient removal of etch-products. In the case of Ar/Cl₂ CAIBE, we find that both shape and depth of the holes, depend on sample temperature, Cl₂ flow and etching duration. By optimizing the process parameters, we show that it is possible to balance the physical and chemical components in the etch process. We demonstrate that Ar/Cl₂ CAIBE is a promising process for PC etching in InP. With this process, we can obtain sufficiently deep holes (2.3–2.5 μm) even for hole diameters as small as 220 nm.

Synchrotron radiation photoemission in combination with optical second-harmonic generation has been used to study thin Ag films grown at 170 K on Si(111)7 × 7. Spectra recorded before and after room temperature annealing are compared. Core level spectra show that a compact film is formed at low temperature. Room temperature annealing transforms the film into large atomically flat domains. Such films show oscillations in the otherwise structureless sp-part of the Ag valence band spectrum due to quantization perpendicular the surface. The variation of peak positions with film thickness is well described in terms of a phase accumulation model. Oscillating second-harmonic generation signals with film thickness due to resonant excitation of quantum well states are demonstrated for various combinations of incident and output polarizations.

We report on a photoluminescence (PL) study of highly compensated Si-doped GaAs. Si-doped GaAs layers were grown p-type at 700°C by liquid phase epitaxy and subsequently converted to n-type by thermal annealing at temperatures above a transition temperature of about 840°C. Annealing at temperatures close to the transition temperature resulted in a very high degree of compensation. This is verified by a large shift of photoluminescence bands with excitation intensity, up to 24 meV per decade of increase in the excitation power density. We attribute the shift to the presence of potential fluctuations which we correlate with a possible site-switching of Si from Ga sites to As sites. Our results strongly suggest that the type conversion from p- to n-type is in fact caused by site-switching of the Si impurity.

Plastic optical fibres, which have a local attenuation minimum at 650 nm, have attracted much interest for low-cost short-haul communication systems. Red vertical-cavity surface-emitting lasers (VCSELs) and resonant cavity light emitting diodes (RCLEDs) provide a potential solution as light sources for these systems. The operation principle of vertical cavity emitters is based on a Fabry-Perot microcavity, which is formed by placing an optically active region inside of two parallel mirrors. The RCLEDs with emission windows of 84 μm in diameter, suitable for standard POFs, exhibit bandwidths up to 200 MHz and light power of 3 mW (cw). The maximum external quantum efficiency is 9.5%. Larger devices, ø500 μm in size, launch light power up to 15 mW. Record high transmission rates, 622 Mbit/s, with bit-error-rate <1  ×  10^-11 have been demonstrated for a 1-m-long step-index POF. Neither sudden unexpected failure, nor gradual power degradation has been observed after operation under accelerated ageing conditions for about 100 000 device-hours. The alignment tolerance of the coupling efficiency is found to be very large, ±0.5 mm in all directions x-y-z, suggesting that the fibre pigtail packaging is inexpensive. First MBE-grown visible AlGaInP vertical-cavity surface-emitting lasers have been demonstrated. A laser with a 10-μm emitting window has external quantum efficiency of 6.65% under continuous wave operation and it is still lasing at 45°C. Furthermore, a threshold current less than 1.0 mA is obtained for a device, which has an 8-μm emitting window.

Silicon nanostructures present a new class of material systems that possess electrical and optical properties distinctly different from bulk silicon. Fabrication process for silicon nanopillars has been described earlier. Now we present optical studies of nanostructures based on silicon nanopillars. Properties of silicon nanostructures were investigated by photoluminescence (PL) and cathodoluminescence (CL) techniques. For electroluminescence (EL) measurements the pillar based device described in [A. G. Nassiopoulos et al. Appl. Phys. Lett. 69, 2267 (1996)] was used. Electroluminescent devices, based on silicon nanostructures were made after planarisation and top electrode formation. Obvious distinctions between PL and EL spectra show that the PL and EL of the pillars are caused by various luminescent centers, located in different parts of the pillars. EL originates from the top contact part of the pillars. The origin of PL is connected to the combined effect of a texturised surface and nonuniform sidewall composition of the pillars.

We have experimentally investigated the performance of external cavity mode-locked semiconductor lasers employing reverse biased saturable absorbers. We have measured the magnitude of trailing pulses when varying the chip length and studied the pulse quality when changing the driving conditions. The observed behavior is explained and we conclude on the optimum operating parameters

We propose and demonstrate a technique combining micro-photoluminescence imaging with scanning photolithography at cryogenic temperatures for creating photoresist masks at designated locations relative to single selected self-assembled quantum dots. The technique is demonstrated by producing a photoresist mask on top of a single selected InP quantum dot imbedded in GaInP. A mesa containing the quantum dot is then created by wet chemical etching. The combination of micro-photoluminescence and scanning photolithography relies on the use of two different lasers with a micro photoluminescence setup, each laser having different power, focusing and wavelength. The resulting structure enables many experiments and applications in the emerging field of single quantum dot physics.

We have investigated the far-infrared (FIR) responses of an array of quantum dots in modulation doped GaAs heterostructures in an external magnetic field. In accordance with the extended Kohn theorem FIR-radiation can only excite the center-of-mass modes of harmonically confined electrons in a dot. In a perpendicular magnetic field the single absorption peak corresponding to the Kohn mode splits in two peaks separated by the cyclotron frequency. We observe novel modes at frequencies below the higher frequency Kohn mode. Comparison with Hartree-RPA calculations show that these modes arise from the flattened confining potential in our field-effect quantum dots. They reflect pronounced relative motion of the charge density with respect to its center-of-mass.

It is demonstrated that the photoluminescence spectra of single self-assembled quantum dots are very sensitive to the experimental conditions, such as excitation energy and crystal temperature. A qualitative explanation is given in terms of the effective diffusion of the photogenerated carriers, determined by the experimental conditions, which influence the capture probability and hence also the charge state of the quantum dots. This is proposed as an effective tool to populate single quantum dots with extra electrons, by purely optical means, in order to study phenomena involving charged excitons.

We report the first direct measurements of dephasing in III-V semiconductor quantum dots at low temperature using degenerate four-wave mixing. At 0 K, the coherence time is limited by the population lifetime whereas pure dephasing due to exciton-phonon interactions appears only at finite temperatures. We observe a striking discrepancy between the homogenous linewidth derived from the dephasing times and the measured photoluminescene linewidth of individual quantum dots, indicating the presence of an additional inhomogenous broadening mechanism in photoluminescence measurements of single quantum dots.

We report on a theoretical study of the electronic structure of silicon nanocrystals with a shape of the regular rhombic dodecahedron, based on a tight-binding method. The energies of the lowest unoccupied state and the highest occupied state have been calculated. We have shown that the six-fold degenerate conduction band minima of the bulk silicon crystal are split into a non-degenerate A₁ state, a double-degenerate E state and a triple-degenerate T₂ state and that the ordering of the energies of these states depends on the size of the silicon nanocrystal. Thus the lowest unoccupied state of the silicon nanocrystal can have different symmetries at different nanocrystal sizes. However, as the size of the nanocrystal changes, the symmetry of the highest occupied state remains the same; it is T₂ symmetric. The wave functions of the lowest unoccupied and highest occupied states have also been calculated. It is shown that these states have very different localization properties. The wave function of the lowest unoccupied A₁ state is largely localized on the central atomic site and on its nearest neighbors. In contrast, the wave function of the lowest unoccupied E state has no contribution from the orbitals of the central atom. Furthermore, the wave functions of both the lowest unoccupied and the highest occupied T₂ states are distributed more evenly over a large portion of the silicon nanocrystals.

The 0.7 (2e²/h) conductance anomaly is studied in strongly confined, etched GaAs/GaAlAs quantum point contacts by measuring the differential conductance G as a function of source-drain bias V_sd and gate-source bias V_gs as well as a function of temperature. In the V_gs- V_sd plane we use a grayscale plot of the transconductance dG/dV_gs to map out the bias dependent transitions between the normal and anomalous conductance plateaus. Any given transition is interpreted as arising when the bias controlled chemical potential μ_d (μ_s) of the drain (source) reservoir crosses a subband edge ε_α in the point contact. From the grayscale plot we extract the constant normal subband edges ε₀, ε₁,... and most notably the bias dependent anomalous subband edge ε'₀ (μ_d) split off from ε₀. We show by applying a finite-bias version of the recently proposed BCF model, how the bias dependence of the anomalous subband edge is the key to analyze various experimental observations related to the 0.7 anomaly.

Electron waveguide Y-branch switches have been fabricated in a GaAs/AlGaAs heterostructure. These are controlled by Pt/GaAs Schottky contacts, which were realized by an in-situ electrochemical process. In this paper we describe the fabrication process as well as present results from conductance measurements in the fabricated devices.

The dynamical properties of InGaAsP multi-quantum-well electroabsorption modulators are investigated using a comprehensive numerical device model. We calculate the time-dependent sweep-out of photo-generated carriers and the corresponding time-dependent absorption change. The sweep-out is influenced by carriers being recaptured into subsequent wells as they move towards the contacts. This process drastically increases the sweep-out time in our ten-well structure (~25 ps) compared to the pure drift-time (~1 ps). We also compare the saturation properties of two components with different separate-confinement heterostructures.

We have studied theoretically the magnetotransport in a ferromagnetic resonant tunneling diode (FRTD), where alternating magnetic Ga_1-xMn_xAs and non-magnetic GaAs and AlAs layers give rise to strongly spin-polarization dependent electronic transport. We have studied a FRDT structure having a non-magnetic quantum well between magnetic emitter and collector layers. The infinite order correction to the energy of the band edge due to the exchange interaction between the charge carrier spin and the magnetic moments of the Mn ions is calculated by using Zubarev's double time Green's functions. Then the current-voltage characteristics of the FRTD is calculated as a function of temperature and magnetic field by using a modified Tsu-Esaki formula. In a FRTD the transport depends strongly on the spin- polarization of the magnetic lattice, and in a certain bias voltage range near the negative resistance region the model predicts colossal magnetoresistance at temperatures close to the Curie temperature.

We have studied the theory of spin disorder scattering in Mn-doped GaAs by calculating in the weak coupling limit the charge carrier mobility limited by the critical scattering. The theory is developed by using Matsubara's temperature Green's functions and treating the exchange interaction between the carrier spins and the localized magnetic moments of the Mn-ions as a perturbation. The carrier life-time and the perturbed band energy are both calculated from the second order self-energy in a self-consistent manner in the sense that first the infinite order correction to the band energy is calculated by iterations, and then the corrected energy is inserted in the expression for the carrier life-time. Adding a contribution from the impurity scattering the total hole mobility can be estimated. Comparison of the calculated results to the experimental magnetotransport data shows good agreement. However, the measured resistivity peak near the Curie temperature is broader than the calculated one, which together with the large exchange parameter calls for an extension of the present theory to the intermediate or strong coupling cases.

We present a theory for Coulomb drag between two mesoscopic systems which expresses the drag in terms of scattering matrices and wave functions. The formalism can be applied to both ballistic and disordered systems and the consequences can be studied either by numerical simulations or analytic means such as perturbation theory or random matrix theory. The physics of Coulomb drag in the mesoscopic regime is very different from Coulomb drag between extended electron systems. In the mesoscopic regime we in general find fluctuations of the drag comparable to the mean value. Examples are vanishing average drag for chaotic 2D-systems and dominating fluctuations of drag between quasi-ballistic wires with almost ideal transmission.

In this paper we introduce a lithography method for AZ5214E resist that adds three dimensionality into the standard optical lithography. With the method we are able to define, e.g., shallow air bridges and metal cross-overs in a single lithography step thus simplifying the device prosessing considerably. The main aim of the original process is towards metallization of nano- and micrometer scale vertical structures with device height of about 1 micrometers or less. Our method for doubly patternable planarizing lithography with AZ5214E resist relies on utilizing optically sensitive AZ5214E in both planarizing layer and top layer in a way that the planarizing layer is patternable separately. The planarizing layer is patterned in the image reversal mode of the resist, and the associated lithography steps are integrated with top layer processing such that the overall lithography is kept simple and reproducible. The typical thickness of the planarizing layer is 1,4 μm, which forms the upper limit for the vertical height of structures defined with the planarizing layer. We demonstrate the applicability of the doubly patternable lithography with an implementation to our heterojunction bipolar transistor process. The process included air bridged metal cross overs and air bridges for smooth entrance into the transistor active area. Finally, the applicability of our process towards small 3D structures is briefly discussed.

The sacrificial oxide etching is one of the key steps in fabrication of micromechanical devices on bonded silicon on insulator (SOI) wafers. The determination of the etch rate of buried oxide layers in bonded SOI wafers from scanning electron microscopy (SEM) cross-sections is a rather tedious and time consuming task. However, the knowledge of the etch front propagation is essential for ensuring the success of etch release and thus the device operation. In this paper a fast and non-destructive method for measurement of sacrificial oxide layer etch rates is described. The pattern and time dependencies of SOI structure etching in concentrated hydrofluoric acid are studied by near infrared microscopy. The etch length of the SOI can be accurately measured with IR microscope. The measurement results were also verified by SEM cross-sections. The observed variation in etch rates can be explained by the SOI interface quality and not by any aspect ratio dependency caused by varying structure layer thickness. In the used etch times for etching of the thermal oxide the etch-rate seems to be limited by the bonded interface quality and not by transport limitations. The results of these experiments and some application examples are shown. Other possible applications, limitations and error sources of this method are discussed.

A new polysilicon TFT has been proposed and fabricated employing air-cavities at the edge of the gate oxide in order to suppress the large leakage current and to improve the electrical stability. The air-cavity reduces the high peak electric field near the drain due to a low dielectric constant. The new device structure can be easily implemented without any additional mask step. The device degradations such as the threshold voltage shift and leakage current variation after gate bias stress is relatively decreased, which may be attributed probably to the fact that the carrier injection into the gate insulator is suppressed near the drain.

We investigate the properties of equivalent-circuit models of squeezed gas film damping. The equivalent may be represented by an infinite ladder-like circuit, with the elements described analytically. We have developed an approximate representation of the ladder which only requires a small number of elements. This is done through a careful selection of elements and including suitable weighting factors. Finally, we classify some mass/spring systems and discuss what consequences the different systems will have upon the modeling.

The article describes methods, that can be used to concentrate ultra pure water for the detection of metallic trace impurities. A few possibilities for the concentration step are discussed. A new alternative, namely the vaporization on a silicon wafer combined with the vapor phase decomposition (VPD) technique is found to be a suitable candidate. The analysis of metallic impurities with the total reflection X-ray fluoresence (TXRF) and graphite furnace atomic absorption spectroscopy (GF-AAS) is shown to be extendable well into the sub-ppt regime.

Chemical Mechanical Polishing (CMP) has become a more and more important process for planarization in IC technology. For planarization, stacked pads with a hard top pad (for high planarization efficiency) and a softer sub pad (for acceptable uniformity) are used. In this work, the focus is to investigate CMP using a soft poromeric pad. Possible applications could be to create rounded structures for microptical devices or corner rounding to reduce stress in microstructures. Surface profile evolution during CMP of both inlaid and protruding pattern of line arrays completely etched in silicon dioxide is investigated. It is found that there is an exponential dependence of the step height in the arrays on the polish time. Also, wide silicon areas were open through the silicon dioxide. It is found that the soft pad allows polishing on the open silicon areas. Due to the selectivity of the slurry between silicon and oxide, the step height increases even though the silicon areas are situated below the oxide.

We developed a new method for lifetime control in silicon power devices, which employs low energy (270 keV) electron irradiation and hydrogen annealing. This method can reduce irradiation cost significantly compared to a conventional method using high energy (2 MeV) protons or electrons. In our measurements, electron-irradiated silicon pn diodes show different turn-off characteristics, after they are annealed in nitrogen or hydrogen atmosphere. Hydrogen-annealed diodes show higher forward voltages and smaller turn-off charges. These results suggest that the defects introduced by low energy electron irradiation are converted to different defects by hydrogen annealing, and that the minority carrier lifetime is reduced due to the new defects.

The properties of 4H-SiC chemical vapor deposition epitaxial layers were studied by different methods. The effects of structural defects in 4H-SiC epitaxial layers on electrical and luminescence properties of Al high dose ion implanted p⁺-n junctions were studied. It has been shown that the structural imperfections of low-doped layers affect some electrical characteristics of the ion doped p⁺-n junctions created in these epitaxial layers.

Several edge-coupled coplanar waveguide bandpass filters centred at 30 GHz and 60 GHz are designed and fabricated. Filters are measured with and without bond-wires connecting the ground planes in order to see the influence of the unwanted coupled-slotline mode. Filters with bond-wires show remarkably better performance. Furthermore, filters where bond-wires are placed not only at the discontinuities but also in the middle of the couplers show better performance than filters where bond-wires are placed only at the discontinuities.

This work describes the modelling of a planar integrated inductor on silicon. In this case modelling means that we try to build a subcircuit model for circuit design purposes. The goal of the model is that all its elements could be derived from process parameters and layout geometrics rather than measured performance. This model has been programmed to operate as a defined model component of the APLAC circuit simulator, and it is optimized for integrated inductors having non-tapered, squared and full turns. Matching of the developed model with measured results is very good a wide range of inductance, but the model needs still four parameters to be determined empirically from process test structures.

An analytical model for calculating the forward voltage of a conventional NPT-IGBT (Non-Punch Through Insulated Gate Bipolar Transistor) is presented, taking into account decrease of the current densities in the epi layer near the cathode junction. Simulation results of the temperature dependent forward voltage and emitter injection efficiency for an IGBT with blocking capability of 1700 V are shown to support the model developed with temperature dependent mobilities. The present model allows a good agreement with the simulation results within 10% in error.

We investigated the maximum controllable current (MCC) characteristics of a new BRT entitled Corrugated p-Base Base Resistance Controlled Thyristor (CB-BRT), which suppresses the snap-back effectively and increases the maximum controllable current. Experimental results exhibit that the MCC of the CB-BRT is less sensitive to various fabrication parameters compared with conventional BRT. Experimental results show that the variation of the MCC in CB-BRT is only 20% of that of the conventional BRT when the n⁺ cathode width is 5 μm and the process parameters change, and the MCC of the CB-BRT is increased by about 50% compared to that of the conventional BRT.

The improvement in SC-1 bath lifetime was studied by adding complexing agents: TEA, EDTA, CDTA, DTPA and DTPMP, to a bath, which was intentionally contaminated with a multimetal standard solution. The decomposition of hydrogen peroxide in the bath was monitored in situ by an optical analyzer. Adsorption of metals to wafers was analyzed by spinning cleaning solutions, containing metals and complexing agents, on wafers. Metal concentrations were measured by TXRF and GFAAS combined with VPD sample preparation.

In this work we report the characteristics of Au/AlGaN Schottky diodes as a function of Al content. The materials were grown by MOCVD and have different free electron concentration and alloy composition. A variety of electrical techniques such as current-voltage (I-V), capacitance-voltage (C-V) and deep level transient spectroscopy (DLTS) measurements were used to characterize the diodes. Although the samples received the same treatment prior and during the Au evaporation process, their I-V and C-V characteristics seem to depend significantly on the Al content x. We obtained a lower value for the Schottky barrier height than that predicted by the Schottky rule for the sample with x = 0.3, along with a departure from unity of the ideality factor. Also we observed a hysteresis in the C-V characteristics in the same sample. The DLTS measurements showed the presence of a density of defects at the Au/AlGaN interface which increases with Al content. We believe that these defects, inherent to the material, cause the lowering of the barrier height and the observed hysteresis. They result from a roughness of the surface due to a high Al content. This also induces spatial fluctuations in the barrier height at the surface.

Closed-form expressions for breakdown voltage and on-resistance of linearly doped pn diodes are derived in terms of the concentration ratio of the final to the initial value of a linearly doped epi layer. Analytical results for the maximum depletion width, critical electric field, and breakdown voltage are verified by the device simulator MEDICI. The minimum on-resistance is found to occur when the concentration ratio approaches 2.2, yielding a reduction of 8.3% in the on-resistance compared to that for the uniformly doped pn diode.

A new Dual-Channel Emitter Switched Thyristor (DC-EST), which suppresses the inherent parasitic thyristor operation effectively by employing a self-aligned trench contact, has been proposed and verified by numerical device simulations. Simulation results show that the maximum controllable current density of the proposed DC-EST is about three times larger than that of the conventional DC-EST because the self-aligned trench contact reduces the resistance under the n⁺ cathode. It is noted that the forward voltage drop of the proposed DC-EST is lower than that of the conventional one by 0.2 V by reduced cell pitch.

This volume contains the Proceedings of the 19th Nordic Semiconductor Meeting (NSM19), which was held in Copenhagen May 20–23, 2001, hosted by Mikroelektronik Centret and Research Center COM, The Technical University of Denmark.

NSM19 followed the tradition of highlighting research in semiconductor physics and technology of particular interest within the Nordic countries. At the same time, the meeting incorporated new fields of research related to or originating from semiconductor research, particularly within the realm of nanoscience and nanotechnology.

There were 114 registered participants from 15 countries at the meeting presenting a total of 103 scientic contributions whereof 15 were invited talks. From these contributions 60 manuscripts have been accepted for publication in the proceedings representing the broad field as well as the high quality of the meeting. At the meeting, the presentations were supplemented by lively discussions at the oral as well as the poster sessions.

Many people have contributed to the success of the meeting and should be thanked: the advisory committee, the local organizing committee and not least the program committee, who are also the editors of this volume. They share together with the authors the credit for the high scientific standard of the meeting as well as its proceedings.

The organization of this meeting would not have been possible without the support from Mikroelektronik Centret (MIC), Research Center COM and the Danish Natural Science Research Council (SNF), and the generous sponsorship by NKT Research and Innovation A/S, Lucent Technologies Denmark, Tellabs Denmark, Plougmann and Vingtoft, and Keithley Instruments Ltd.

On behalf of the Organizing Committee, I would like to express our gratitude to everyone contributing to the success of NSM19.