Abstract
RF behavior improvement suggestions to the MOSFET models were studied using mostly BSIM3v3 and Philips MOS Model 9 (MM9). Different substrate resistance model topologies were compared. Also distributing the gate, source and drain resistance was studied as well as the use of an additional capacitance Cg in parallel with the gate resistance. The basis for the AC improvement studies is an accurate DC and AC extraction of the basic device model. Scalable MOSFET parameter extraction was done using the APLAC circuit simulator and by programs written with APLAC description language. The device characterization set included gate widths down to 0.4 μm. The parasitics of the pads and wires were carefully removed utilizing de-embedding techniques. A gate resistor was used for both MM9 and BSIM3 and also Cgb0 zero-bias capacitance was added to MM9.
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