With sub-22 nm technology nodes, the short channel effects (SCEs) arose in FinFETs, which hindered the further scaling of devices. The leakage currents became detrimental with scaling of the gate oxide thickness below 2 nm, hence the demand for control of leakage currents due to corner effects in the sidewalls of FinFETs. Research suggested use of gate underlap (GUL) architectures to suppress the leakage currents. The objective of this paper is to utilize a GUL structure in a 10 nm gate length Heterostructure-On-Insulator (HOI) FinFET, encompassing a three layered strained channel architecture to enrich the drive currents. Different structures with GUL lengths of 1 nm, 3 nm and 5 nm are designed to study the electrical characteristics besides the effects of leakage currents and other SCEs. A noteworthy decrease is observed in the leakage currents with increasing GUL lengths. However, it also leads to decrease of drive currents of the devices. A trade-off between the enhanced dimensions of source/drain along with an optimized GUL length proves beneficial in the strained silicon channel devices. The 10 nm HOI device employing a 3 nm GUL with height/width of source/drain at 8 nm provides drive currents and leakage currents at par with the 10 nm HOI device with no underlap. But with higher Ion/Ioff current ratio and lower SCEs, this device with 3 nm underlap decreases corner effects and is observed from the electron velocity and total current density contours leading to faster switching speeds and optimized device performance towards semiconductor industry.
Focus on Advanced Nanoscale Devices for Integrated Circuit Design
Guest Editors
Arpan Deyasi, RCC Institute of Information Technology, India
Angsuman Sarkar, Kalyani Government Engineering College, India
Scope
This special issue focuses on analytical modelling, simulation and experimental characterization of low-dimensional structures and devices, which are now becoming an integral part of modern ultra large-scale integration design.
This special issue will cover the fabrication and characterization of quantum devices along with theoretical novel findings designed in high frequency spectra.
In the last few years, extensive research has been carried out on microelectronic technologies, corresponding device characterization as well as its analytical modeling and simulation. Scientific discoveries and technological advances related to low-dimension devices have become a promising field due to the requirement of industry, and therefore researchers are keen to engineer novel architectures and devices which can solve the integration demand. Novel combination of materials and complex geometries are therefore leads to the path of innovative device design and estimating the performance for applications in circuits/systems is crucial.
With extended version of selected papers from EDKCON 2022, this collection presents cutting-edge research related to low-dimensional devices which will lead to future integrated circuit design. The subtopics to be covered within this issue are:
- Modeling and simulation of quantum-mechanical devices
- Design, fabrication and characterization of novel nanoscale architectures
- Emerging non-CMOS devices
- Modeling of photonic devices
- Physics and modeling of submicron microelectronic devices
- Mathematical models of novel electronic device structures
- Novel MOS devices
- Applications of numerical methods to the modeling and simulation of devices and processes
The submission deadline is February 28 2023, and you can can submit here.
Papers
The current manuscript for Asymmetric Junctionless Dual Material Double Gate MOSFET (AJDMDG MOSFET) biosensor reports improved sensitivity for both threshold voltage and ON-current. In the presence of high-K dielectric material, the device was built using both neutral and charged biomolecules. After calculating the minimal surface potential, the threshold voltage is calculated by solving the 2D Poisson's equation using a parabolic-potential configuration under realistic boundary circumstances. Analytical results show good agreement with TCAD simulation, prompting an exploration of threshold voltage sensitivity with front-gate voltage changes of all possible dimensions. Corresponding drain current sensitivity with a higher ON-to-OFF current ratio is theoretically estimated and compared with identical DGFET architecture, resulting in a significant improvement for all possible step patterns when steric hinderance is considered for moderately filled cavities; this aids in detecting both labelled and label-free electrical species at lower concentration levels.