Table of contents

Ultra-wide bandgap (UWBG) semiconductor devices have the potential to operate more efficiently than, and could enable applications that cannot be realized with, SiC or GaN devices because the larger bandgap, E_G, provides a larger critical electric field, ξ_C. This enables the semiconductor to be doped more heavily for a given breakdown voltage, V_B, so the internal resistance, R_ON, and therefore heat loss, will be smaller provided that the probability of premature breakdown has not been significantly enhanced, mobility of the carrier has not been substantially degraded, charge carriers from the dopant states can easily access a conducting band at room temperature, and dopant and electrically active impurity and point defect concentrations can be adequately controlled. If these problems can be addressed, then devices used for continuous power applications such as high power electronic inverters can be built to run more efficiently, or RF HEMTs with more output power can be fabricated. In addition, pulsed power devices such as those that could be used for electronic armor, that do not currently exist, could be built.

GaN transistors should be able to operate more efficiently than those made from SiC primarily because its 2-dimensional electron gas, 2DEG, created at the AlGaN/GaN interface has a carrier concentration that is 10X larger and an electron mobility that is 50X larger than that of SiC/oxide inverted surface; the bulk mobility is also 20% larger. However, SiC can be controllably doped at ~5x10¹⁴ cm^-3, whereas background Si, O, and C impurity densities often exceed 10¹⁶ cm^-3 in GaN. Si and O are shallow donors, and it has been suggested that their sources are the NH₃ reactant gas in CVD growth and the NH₃ or N₂ reactant gas in MBE growth. Given the higher growth temperature, the quartz reactor used in CVD growth is also thought to be a source. C is amphoteric, but for n-type material it is thought to occupy a N site where it is a deep acceptor. The reactant gases containing N are thought to be a source for all types of growth; the SiC platen is thought to be a source for all types of CVD, and the metal reactant in MOCVD growth is yet another source. Si forms a DX center, O forms a deep donor, and C forms a deep acceptor in AlN so it is unlikely that AlN will be an active semiconductor in HPE devices. However, the C background concentration will be a problem for AlGaN with enough Ga so that Si acts as a shallow donor, ~ 20%. Thus, AlGaN has the advantage that it can be "tuned" over a wide range of compositions for this Ga content and above. However, alloy scattering in the 2DEG and the bulk will have to be determined to discover if the increase in the allowed maximum carrier concentration enabled by the larger E_G can be more than offset by the reduction in the mobility caused by the alloy scattering. Researchers will also have to deal with the problem of lattice mismatch between the substrate and device structure. The problem is made more challenging by the facts that for structures with low Al content in the bulk layer, will be in tension because the substrate of choice is GaN, and for the high Al content structures, the drift region will have an Al content at least 30% less than the AlN substrate.

Diamond is an attractive material because both electrons and holes have a large mobility, its ξ_C is almost as large as it is for AlN, and it has a larger thermal conductivity. However, both the P donor and B acceptor are very deep. Also, someone will have to identify a dielectric whose band structure properly matches it to create a 2DEG with a reasonable mobility. An alternative approach could be to fabricate a bipolar junction transistor, which is made more palpable by the fact diamond has an indirect bandgap Also, methods will have to be developed to grow high quality, larger area structures.

High quality, large area, relatively inexpensive wafers of β-Ga₂O₃ are already available, and Si or Sn form shallow donors. However, the facts that it cannot now be doped p-type, the electron mobility of 200 cm²/V·s is quite small, its thermal conductivity is ~100X less than the other UWBGs, and its complex rhombohedral structure could create complicated point defect structures and not be compatible with materials with simpler crystal structures. Currently, the best HPE device option appears to me a MESFET.

1. Introduction

With its proven ability to reduce size (form factor) and save energy (high efficiency) Gallium Nitride (GaN) is now no longer a nice to have, it is a must-have for power conversion. In applications ranging from sub 100 watt to multi kilowatt highly efficient power converters and inverters, GaN HEMTs high switching speed and low efficiency make it a natural choice of Silicon based devices reaching their physical limits of performance. Transphorm has already commercialized JEDEC qualified GaN HEMT power switches manufactured in an automotive grade 6 inch Si CMOS fab [1]. With this strong base and its ability to reduce size, weight and improve miles per gallon, GaN HEMTs are now increasingly being investigated for EV & HEV applications such as on board chargers and other auxiliary power conversion within the automobile under 10 kW. We will review the first ever Automotive (AEC Q101) Qualification for GaN and also discuss results for highly stressed robustness tests, FIT rates & lifetime testing.

2. GaN Products and Qualification

Normally off GaN devices (Fig. 1) are achieve through integration of a low voltage Si-MOSFET input device with a high voltage depletion mode GaN device offering the best combination of input gate interface and the most robust high voltage GaN platform [2]. Electrical characteristics of the normally-off GaN power switch are summarized in Table 1 with a Low Rds(on), low gate charge (Qg) and low capacitance (Coss) that enable high efficiency, small form factor power systems. The Ron *Qg or Ron * Coss figure of merit is already better than mature Silicon Superjunction MOSFETs and achieved simultaneously with superior reliability performance. We have successfully passed (on multiple products and generations) the full suite of JEDEC qualification tests [3], as shown in Table 2.

3. Robustness, Long Term Reliability and Lifetime of High Voltage GaN

To further establish confidence in long term reliability and operation in the field with low FIT rates, we have extended JEDEC qualification to 3-5x the stresses, for e.g. 5,000 hours of HTRB (5x JEDEC stress) with no degradation in resistance, threshold or leakage (Fig 3). Systematic high voltage off-stage (HVOS) acceleration at over 1100 volts was done to determine intrinsic lifetime (MTTF) of over 100 Million hours and 1% failure of more than 1M hours (Fig 5). Similarly through accelerated high temperature on-state testing of GaN, a high temperature MTTF of over 100 Million hours at 175C was determined. Recently, in March 2017, we completed the first ever successful AEC-Q101 standard qualification of GaN products [4]. These will be discussed in detail at the conference.

4. GaN Products and Qualification

The comprehensive suite of data and results with a 3 year manufacturing history on over 3,000 wafers in a high volume commercial 6-inch Wafer fabrication facility unequivocally demonstrate that GaN power switches are now reliable and ready for a wide array of consumer & communication, industrial & renewable energy as well as automotive applications. The next milestones which are now happening include announcement of a variety of end system products (Titanium rated data server power supplies, PV Inverters, Telecom power supplies and Servo motor drives), paving the way for an exciting era in highest efficiency, highest reliability power conversion with GaN.

5. References

• P. Parikh, et. al., "Commercialization of 600V GaN HEMTs," 2014 SSDM, Tsukuba, Sep., 2014.

• Power GaN Devices- Materials, Applications and Reliability, Edited by M. Meneghini et. al., Springer International Publishing, 2017.

• T. Kikkawa, et al. 600 V JEDEC-Qualified Highly Reliable GaN HEMTs on Si Substrates," IEEE IEDM, San Francisco, Dec. 2014.

• APEC 2017, http://www.transphormusa.com/news/transphorm-announces-first-automotive-qualified-gan-fets/

Figure 1

AlGaN is of high interest for high-power electronics based on vertical structures due to its high breakdown field and electron mobility. Recent studies in GaN based p-n junctions indicate a dielectric strength in the range of 3.3–3.75 MVcm^-1, resulting in a Baliga's figure of merit several times larger than that of SiC. However, high breakdown voltages (>4kV) are currently confined to GaN p-n junctions indicating GaN and AlGaN surface instabilities. Consequently, defect-free metal-nitride interface and passivation of Al/GaN are necessary for breakthroughs in high power vertical Al/GaN Schottky diodes.

Accordingly, we report defect-free behavior in Ni/GaN Schottky diodes with unity ideality factor and fabricated by photolithography. They also exhibit high temperature stability (>600 ^oC) and low leakage with forward and reverse I-V-T characteristics successfully modeled by a single homogeneous barrier (0.7 eV) by ATLAS simulations. It is significant that the forward and reverse characteristics could be modeled by a common set of parameters without a defect based second diode to model the reverse leakage. XPS chemical and electronic analysis was employed to determine the surface treatment necessary to obtain such a Schottky interface. Consequently, we demonstrate the suitability of GaN surface and interface with metals for high power electronics.

Although a near-ideal diode may be obtained on GaN, the relatively low barrier height limits the GaN Schottky diode to operating voltages <1000V. Increasing the barrier by controlling the Fermi level pinning and producing a camel junction by surface Mg doping is possible.

Passivation is the next challenge to implementing Al/GaN based high power electronics. Silicon nitride has emerged as the standard passivation material for GaN and low Al composition Al_xGa_1-xN (x<0.3). However, the bandgap of silicon nitride is lower than AlGaN for x>0.75 and the feasibility of silicon nitride functioning as an insulating dielectric (by providing appropriate electron/hole barriers) in Al rich AlGaN and AlN is uncertain. Similarly, reduction of surface states by silicon nitride passivation has not been reported for Al rich AlGaN (x>0.3).

In this work, we have employed X-ray photoelectron spectroscopy to determine the band offsets and interface Fermi level at the hetero-junction formed by stoichiometric silicon nitride deposited on metal polar Al_xGa_1-xN (of varying Al composition 'x') via high temperature low pressure chemical vapor deposition. Silicon nitride is found to form a type II staggered band alignment with AlGaN for all Al compositions (0<x<1) and presents an electron barrier into AlGaN even at higher Al compositions where E_g(AlGaN)>E_g(Si₃N₄). No band bending is observed in AlGaN for x<0.6 and indicating excellent passivation beyond x=0.3. Further a reduced band bending (by 1 eV relative to free surface) is observed for x>0.6. The Fermi level in silicon nitride is found to be at 3 eV with respect to its valence band and is likely due to silicon (≡Si0/-1) dangling bonds. The presence of band bending for x>0.6 is seen as a likely consequence of Fermi level alignment at Si₃N₄/AlGaN hetero-structure and not due to interface states indicating likely passivation on AlGaN beyond x=0.6. Photoelectron spectroscopy is corroborated by capacitance-voltage measurements. A shift in the interface Fermi level from the conduction band in Si₃N₄/n-GaN to the valence band in Si₃N₄/p-GaN is observed which strongly indicates no or greatly reduced mid-gap interface states. Further, required compensation of spontaneous polarization charge is typically performed by oppositely charged surface states/defects on free surface is hypothesized to be replaced by oppositely charged silicon dangling bonds (≡Si^0/-1) after passivation. This hypothesis is supported by characterization of silicon nitride on N-polar GaN. In conclusion, HT LPCVD silicon nitride is found to be a suitable passivation for Al rich AlGaN.

Owing to low conduction/switching loss, high switching frequency and high operating temperature, wide bandgap SiC and GaN power devices are attractive for next-generation power electronic systems with increased efficiency and power density. Because of the superior performance, SiC and GaN power devices could be in position to compete with the mainstream Si power devices in a variety of applications, including household appliances, photovoltaic inverters, electric vehicles, data centers, etc. Despite numerous research efforts devoted to material growth, device fabrication and circuit demonstration in the past decades, wide bandgap power semiconductor devices are still confronted with challenges that need to be addressed through new structure design and advanced process development. In this talk, we will review recent progress in SiC and GaN power devices, including the following. (1) High-density of interface traps usually exist at the gate-oxide/SiC interface in SiC MOSFETs, presenting a critical challenge to the channel mobility and device stability. Interface engineering techniques for SiC MOSFETs (e.g. NO/N₂O annealing, P incorporation, metal interfacial-layer, high-k dielectric deposition, etc.) and their impact on interface trap distribution as well as channel mobility will be discussed. (2) Long-term reliability of SiC MOSFETs with special focus on time-dependent dielectric breakdown (TDDB) will be presented. (3) We will introduce our latest progress in design and fabrication of super junction SiC devices, which can break the fundamental limit of the conventional unipolar devices. (4) In GaN-based lateral power devices, the 2DEG channel is an inherent normally-on channel, due to the spontaneous and piezoelectric polarization effects. To achieve fail-safe operation and simpler gate drive circuit, normally-off device technology including p-(Al)GaN cap, barrier recess and plasma treatment in the gate region will be introduced and compared. (5) Gate stack engineering techniques toward high-reliability GaN MIS-HEMTs/FETs will also be presented.

GaN is an important wide band-gap semiconductor in electronics and optoelectronics. In its porous form is particularly interesting for developing optoelectronic devices with improved efficiency, such as LEDs with enhanced efficiency and sensors with enhanced sensitivity.

Through chemical vapour deposition (CVD) [1], we have shown that it is possible to produce nanoporous GaN without any etching or chemical post-growth treatment, with the porosity being present only on the (0001) face of the material. Low resistivity ohmic Pt and Au metallic contacts were demonstrated on porous n-type GaN by the formation of intermetallic seed layers through the vapour-solid-solid (VSS) mechanism [2]. Also, we have been able to develop p-type porous GaN by doping with Mg, with a charge carrier concentration of the order of 10¹⁸ cm^-3 [3]. By tuning the concentration of Mg, introduced as Mg₂N₃ in the CVD system, it has been possible to form a polycrystalline high-k oxide between an ohmic metallic alloy interlayer contact and the porous GaN, while maintaining a clean interface, that allowed to fabricate a MOS-type diode on silicon in a single growth regime [4].

Through the careful selection of the substrate it has also been possible to produce porous GaN epitaxial layers [5] that allow for the fabrication of high quality partially and fully porous GaN rectifying p-n junctions, through a two step CVD process, and show their behaviour as diodes with effective uniform conduction under a green technology [6]. Here, we will also present the recent results we obtained in the light emission of these structures. Thus, these porous junctions have potential applications in high brightness unencapsulated LEDs with enhanced light emitting properties and high surface area sensors with improved sensitivity.

[1] Carvajal & Rojo, Crystal Growth Des., 9 (2009) 320

[2] Bilousov et al., ACS Appl. Mater. Interfaces 4 (2012) 6927

[3] Bilousov et al., Appl. Phys. Lett. 103 (2013) 112103

[4] Bilousov et al., Chem. Mater. 26 (2014) 1243

[5] Bilousov et al., CrystEngComm 16 (2014) 10255; Bilousov et al., ACS Appl. Mater. Interfaces 6 (2014) 17954

[6] Carvajal et al., ECS Transactions 66 (2015) 163

Figure 1

AlGaInN epi structures are used for manufacturing white LEDs, UV, blue and green laser diodes (LD) and high-power/high-frequency transistors. In this work, we will show our proprietary and patented technology of lateral patterning in which we fabricate GaN substrates with locally variable off-cut (variable atomic step width). Such substrates are used for InGaN and AlGaN growth of 3-dimensional epi structures. The GaN off-cut influences a number of AlGaInN characteristics: Indium incorporation (smaller for a higher off-cut), Ga and N vacancies concentration, critical conditions for relaxation, decomposition rate, and some others. Therefore, using the GaN substrates after such lateral patterning, we may fabricate nano-wires which would be used for electronic device manufacturing. Unfortunately, AlGaInN epitaxial layers contain a large number of defects (dislocations, trench defects, In-clusters, and some others) which disturb the step-flow. We will show a comparison of results obtained using different GaN crystals: thick layers on sapphire and SiC (dislocation density higher than 10⁸ cm^-2), bulk crystals grown by various methods having dislocation density between 10⁷ cm^-2 and 10⁴ cm^-2. Then, we will present how the growth conditions (temperature, pressure, flows of reactants, presence of hydrogen in the carrier gas) influence the nanowire formation. One of the big issues in nitride technology is InGaN decomposition during the p-type growth at temperatures higher than those used for InGaN growth. Therefore, part of the presentation will be devoted to that issue, in particular, how lateral patterning may influence this decomposition.

A Nanostructured GaN Device Architecture for Power Applications

Z. John Shen, Gourab Sabui, Vitaly Z. Zubialevich, Mary White, Pietro Pampili, Peter J. Parbrook, Mathew McLaren, Miryam Arredondo-Arechavala

Gallium nitride (GaN) has emerged as a promising material for development of power semiconductor devices owing to its high critical electric field, large bandgap and superior transport properties. The unique properties of GaN have prompted realization of power devices both in a lateral (high electron mobility transistors (HEMTs)) and a vertical layout (bulk GaN on GaN devices). GaN power devices show extremely low conduction and switching losses and holds the key to extremely low-loss and high-efficiency power converters of the future. However, GaN power devices have been plagued with several inherent drawbacks preventing a ubiquitous adoption of GaN as the material of choice for power switches. The most critical trade-off has been the choice of substrate for the growth of GaN epitaxy: a high performance, high-cost native substrate against a low-cost, non-native substrate with associated reliability issues. For GaN to thrive as a superior successor to Si, a low cost, high performance epitaxy with improved reliability is expected moving forward. Current lateral HEMTs and vertical GaN on GaN devices are inadequate to address this trade-off.

A novel nanostructured approach to GaN power devices is proposed in this paper. The unique property of GaN nanowires is its ability to elastically relax in the lateral direction, and accommodate lattice mismatch with non-native substrate through pseudomorphic growth without dislocation formation as compared to thin-film heterostructures. Experimental studies have shown self-induced GaN NWs grown with a high surface to volume ratio on a Si substrate have a non-polar side face and is virtually free of threading dislocations and other structural defects. Power devices grown on a nano-GaN epitaxy theoretically have the potential to bypass the reliability concerns associated with a non-native substrate but still deliver comparable or even superior performance, albeit at a low-cost.

Schottky barrier diodes are designed and fabricated based on the nano-GaN concept. Fabricated diodes grown on a Sapphire substrate show distinct rectifying properties blocking voltages of 100 V. Despite repetitive biasing, the devices did not show any sign of current collapse. Design optimization of the nanowire Schottky barrier diode (NWSBD) is performed using 3D TCAD drift-diffusion simulations and semiconductor-oxide interaction was utilized to push the performance of the NWSBDs beyond the unipolar limit of GaN. The optimized NWSBD show the potential to block voltages upwards of 650 V working under present fabrication constraints of doping concentrations and pillar height. Simulated characteristics predict superior V_RB²/R_ON FoM, outperforming both the lateral HEMTs and the vertical GaN on GaN devices.

A fully controlled, three terminal nanowire field effect transistor (NWFET) is also investigated using 3D TCAD drift-diffusion modeling. The NWFET can be operated in both normally-off and normally-on modes based on design and requirements. The 3D gate around the nanowires coupled with a strong dielectric REduced SURface Field (RESURF) effect allows this architecture to block voltages beyond the 1D unipolar material limit of GaN in the reverse bias. With proper design, highly desirable linear voltage to pillar height scaling can be achieved for the NWFET. Breakdown voltages of more than 900 V is predicted, with superior V_RB²/R_ON and Q_GD x R_DS(ON) figure of merits. Despite lacking a body-diode, the NWFETs being quasi-symmetrical enables current conduction in the 3^rd quadrant itself by self-commutated reverse conduction with a very low voltage drop.

The nanowire architecture holds great potential to produce power rectifiers and controlled FETs with high performance, improved reliability and ruggedness and in a cost-effective way.

There are a number of potential reliability issues associated with SiC power MOSFETs, including threshold-voltage stability, gate-oxide reliability, body-diode robustness, short-circuit current robustness, and radiation effects. This talk is primarily focused on threshold-voltage stability and the need for an improved test method to unambiguously separate out good devices from bad ones. Threshold-voltage stability is affected primarily by active charge traps in the near-interfacial region of the insulating gate oxide. Their close proximity to the semiconductor interface leads to a strong time dependence in the direct-tunneling mechanism in response to changes in gate bias. This time dependence is not properly accounted for in the existing test methods for assessing high-temperature gate-bias (HTGB) effects, which allow temporary removal of bias during cool down and significant un-biased delay (up to 96 hours) before the post-stress measurements are performed. However, this delay, introduced to accommodate the practical constraints of industrial testing, renders this test practically meaningless due to the significant recovery that occurs in the charge states of the near-interfacial oxide traps. This difficulty can be overcome by reapplying the gate bias for a brief period of time before measuring. Details of the nature of the near-interfacial oxide traps will be discussed, including their activation energy. All this work will be presented within the context of standards development within JEDEC, and a new SiC power-devices qualification working group.

With the current needs towards achieving significantly higher power density and energy efficiency of power conversion, the industry is highly interested in replacing mature Silicon devices with the emerging Silicon Carbide (SiC)-based technology in the new generation of power electronics systems. Multi-physics modelling represents a very important design step used to evaluate and confirm the potential of SiC devices in a wide-range of power electronics applications before any prototypes are constructed. It enables a detailed assessment of SiC technology with respect to different performance aspects including dynamics, thermal capabilities, and robustness against abnormal operating conditions. As a prototypical example, this paper presents a highly accurate modelling procedure for analyzing short-circuit (SC) capabilities of a commercial SiC power MOSFET (80mΩ, 1.2kV). First, the actual MOSFET structure is modeled in Synopsys Sentaurus TCAD tool suite and calibrated to match the I-V and C-V MOSFET characteristics, taking into account the mobility degrading effects and interface states at the SiC/SiO2 interface. In the next step, TCAD mix-mode simulations are performed using the developed physical model to gain a better understanding of the design parameters like cell pitch, channel length and p-base doping concentration and their impact on the MOSFET SC and dynamic characteristics considering temperature dependencies and design constraints. Accordingly, a trade-off analysis between improved SC capabilities and a good MOSFET dynamic performance will be discussed, which can be further used as a guideline for developing an optimized MOSFET structure. Moreover, a detailed three-dimensional electromagnetic model of the SC measurement setup will be presented in order to identify the influence of the circuit parameters on the current profile of the Device-Under-Test (DUT) during the SC events and to optimize the measurement setup. For a comparison between the measured and simulated MOSFET waveforms, coupling of electrical and electromagnetic domains will be performed in LTSpice, Saber and TCAD mix-mode tool. As a result, this paper will demonstrate the accuracy of three device models side-by-side: the compact device model implemented in LTSpice, the behavioral model of Saber, and the TCAD numerical model. Finally, the paper emphasizes the requirements for a very accurate and efficient multi-domain modelling procedure that can be integrated in the overall development process of SiC power MOSFETs.

Fig. 1 A comprehensive analysis of short-circuit (SC) capabilities of a commercial SiC power MOSFET (80mΩ, 1.2kV) based on a multi-physics modelling approach.

Figure 1

In 4H-SiC electronic devices, Al⁺ ion implantation is often used to obtain selected regions of desired p-type conductivity in n-type epitaxial layers. A mandatory high temperature annealing is necessary after the implantation process for the electrical activation of the implanted Al. The temperature of the former and the density of the latter vary in the range 1600-1950°C and 10¹⁷-10²⁰ cm^-3, respectively. The switching properties of the so obtained bipolar junctions depend on carrier life-time in the n-type 4H-SiC epitaxial layers after processing.

In the literature, it has been shown that carbon vacancy V_C in n-type 4H-SiC epi-layers is a carrier life-time killer defect and that its concentration, after high temperature treatments in the range 1500-1950°C, saturates on values that are higher the higher are the applied temperature and cooling rate [1]. It has been also shown that, in the case the thermally treated 4H-SiC epi-layers were ion implanted, and whatever is the implanted ion species, V_C annihilation took place from 1000°C till 1500°C, while at 1600°C the phenomena of V_C annihilation and V_C formation seem to compete [2], suggesting that up to 1500°C, a carbon interstitial I_C's injection from the implanted near-surface layer into the epi-layer can be sufficient to make dominant V_Cannihilation, but this is not the case at 1600°C.

Our previous studies on carrier life-time in Al⁺ implanted p⁺-n-n⁺ diodes, with 6×10¹⁹ cm^-3 and 2×10²⁰ cm^-3 Al⁺ implanted emitters after 1600 °C/20 min without carbon-cap (C-cap) and 1950 °C/5 min with C-cap post implantation annealing, respectively, have shown longer carrier life-time for diodes annealed at the lower temperature, about 700 ns against 170 ns [3], as measured by open circuit voltage decay (OCVD). The diodes annealed at the higher temperature have shown, by DLTS spectroscopy, a V_C concentration lower by a factor ~ 3 relative to that in as-grown epi-layers subjected to almost the same thermal annealing (1950 °C /3 min) [1]. If the ion dose is sufficiently high, it is reasonable that injection of I_C's from the implanted layer into the epi-layer bulk takes place even at temperatures as high as 1950 °C but thermal generation of V_Cstill remains the prevailing process.

Taking into account the above results, it sounds reasonable to deserve efforts to the investigation of an ion implantation technology for bipolar junction in 4H-SiC where the electrical activation of the implanted species is achieved by a high temperature treatment and the degradation of the carrier life-time in the device drift layer is rescued by a subsequent low temperature treatment. The first step towards such a technology is to verify that during the thermal treatment for carrier life-time rescue, none or negligible deactivation of the electrically activated dopant takes place. This is the purpose of this study.

4H-SiC materials, both high-purity-semi-insulating (HPSI) and low doped n-type, have been implanted with Al⁺ ions so to obtain a homogenous doped layer next of the wafer surface. Post implantation annealing has been performed at 1950°C for different times in the range 5-40 min. Some samples have been also thermally treated at 1500°C for 40 min or for 240 min. During every annealing, the sample were protected by a pyrolyzed resist film (C-cap), that was removed after the last thermal treatment. The implanted Al concentration was 1×10²⁰ cm^-3, that is lower than Al solubility in 4H-SiC at 1950°C, and higher than the expected, but never measured, Al solubility in 4H-SiC at 1500°C [4].

Van der Pauw devices were used for Hall effect and sheet resistance measurements in the temperature range 180-680 K. The temperature dependences of these data show that the 1500°C treatment has an effect ranging from "neutral" to "beneficial" on the electrical transport of the Al⁺implanted 4H-SiC layer submitted to a 1950°C annealing immediately after implantation.

This result opens the way towards the fabrication of bipolar diodes with p-type emitters of almost identical hole density but different thermal treatments after implantation, thus with drift layers that might have very different current transport properties.

[1] H. M. Ayedh, V. Bobal, R. Nipoti, A. Hallén, B. G. Svensson, J. Appl. Phys.115, 012005 (2014)

[2] H. M. Ayedh, A. Hallén, B. G. Svensson, J. Appl. Phys.118, 175701 (2015).

[3] H. M. Ayedh, M. Puzzanghera, B. G. Svensson, R. Nipoti, Mater. Sci. Forum897, 279-282 (2017)

[4] M. K. Linnarson, U. Zimmermann, J. Wong-Leung, A. Shoener, M.S. Janson, C. Jagadish, B. G. Svensson, Appl. Surf. Sci.203-204, 427-432 (2003).

Silicon carbide is a material of interest for high-voltage and high-power switching device applications. Basal plane dislocations (BPDs) are a major concern for SiC bipolar devices as they source Shockley-type stacking faults in the presence of an electron-hole plasma and reduce minority carrier lifetimes [1, 2]. Many researchers have investigated methods to reduce the BPD density by experimenting with pre-growth treatments [3-5], substrate orientation [6], growth parameters [6, 7] and growth interrupts [8]. This work investigates extended defects, morphology and lifetime in 4H-SiC epilayers grown on substrates offcut 2° toward the [11-20].

Epilayers were synthesized on 2° offcut substrates in a horizontal hot-wall reactor using the standard chemistry of silane (2% in H₂) and propane. Epilayers were grown at various growth rates, C/Si ratios, and growth temperatures. The pressure was maintained at 100 mbar for all growths. Some samples were grown with a 5 µm highly doped n⁺ buffer layer using ultra high purity nitrogen prior to the low-doped epilayers. Ultraviolet photoluminescence (UVPL) imaging was used to identify BPDs in the low doped epilayers. Time resolved photoluminescence measurements were performed to determine the minority carrier lifetime of the layers and analysis of Raman spectroscopic maps revealed the location of polytype inclusions. Electron trap concentrations were determined using deep level transient spectroscopy (DLTS). Surface roughness was measured by atomic force microscopy and the morphology was also characterized using Nomarski microscopy and white light interferometry.

When a 15 µm epilayer was grown without a buffer layer, step bunching was observed and the surface roughness was 6.0 nm RMS. For comparison, a standard 4° offcut sample typically has 3.0 nm RMS for a 20 µm epilayer. Using UVPL, it was found that after 4 µm of epi, 90% of the BPDs had converted in the low doped layer as compared to 70% in a 4° offcut sample, indicating the conversion is faster in the lower offcut material. The conversion results were from an older substrate and vendor A. For newer substrates, vendor B, the density of BPDs at the epilayer/substrate interface was ≤ 0.2 cm^-2. 3C-SiC inclusions were present in the epilayers as verified using Raman spectroscopy for both unintentionally doped (UID) and N+ epilayers. These inclusions were eliminated by increasing the growth temperature and lowering the C/Si ratio for N+ epilayers, but by increasing C/Si ratios for UID films. Changing these growth parameters resulted in specular film morphology and resulted in minority carrier lifetimes of approximately 1 µs.

[1] J.P. Bergman, et al. Mater. Sci. Forum Vol. 353-356, 299 (2001).

[2] R.E. Stahlbush, et al., J. Electron. Mater. 31, 370 (2002).

[3] Z. Zhang, et al., Appl. Phys. Lett. 89, 081910 (2006).

[4] J.J. Sumakeris, et al., Mater. Sci. Forum 527-529, 529 (2006).

[5] H. Tsuchida, et al., Mater. Sci. Forum 483-485, 97 (2005).

[6] W. Chen and M.A. Capano J. Appl. Phys. 98, 114907 (2005).

[7] T. Ohno, et al., J. Cryst. Growth 271, 1 (2004).

[8] R. E. Stahlbush, et al., Jr., Appl. Phys. WeLett. 94, 041916 (2009).

In recent years cubic silicon carbide (3C-SiC) has been regaining its importance among other SiC polytypes in development of various semiconductor device applications. Besides for active devices it can be used as a substrate for growth of high quality nitrides or epitaxial graphene layers. The quality of the latter greatly benefits from the absence of energy driven step bunching. The high electron mobility (~1000 cm²V^-1s^-1) and lower bandgap (~2.3eV) of 3C-SiC, compared to hexagonal SiC polytypes, enabled researchers to demonstrate the best channel mobility values (~300 cm²V^-1s^-1) among the SiC-based MOSFETs devices. The advantages of 3C-SiC for development of medium power devices have been recognized by the European Commission which is funding a collaborative research project "CHALLENGE" (2017-2021) aiming at pushing 3C-SiC growth and device fabrication technologies closer to the market. There are also uprising innovative applications like intermediate band solar cells and photo electrochemical devices for water splitting which significantly benefit from the intrinsic 3C-SiC properties.

Due to the lack of bulk 3C-SiC crystals, hetero-epitaxial growth on Si or hexagonal SiC substrates is the way used today to obtain 3C-SiC material with a size suitable for device fabrication. However, such 3C-SiC does not demonstrate the full potential of its intrinsic semiconductor properties due to a high density of defects, e.g. stacking faults, which are formed at the 3C-SiC/substrate interface. This problem is more pronounced in 3C-SiC grown on Si due to the large mismatch in lattice parameters and thermal expansion coefficients. Concomitantly, the majority of functioning devices, varying from MOSFETs to MEMS, have been demonstrated using such material. Therefore, it can be expected that mastering the growth and doping of 3С-SiC on hexagonal SiC substrates, especially providing high resistivity 3C-SiC material, would allow to demonstrate better performance of medium power devices.

Although lattice and thermal matching between cubic and hexagonal SiC is not an issue, the 3C material quality on on-axis substrates is limited by the symmetry mismatch between SiC (0001) and 3C-SiC (111) , which induces rotational twinning and formation of double positioning boundaries (DPBs). Important fundamental problems on initial nucleation and defect formation have been already resolved and a solid background of knowledge has been delivered to developing of another 3C-SiC growth approach and that is to explore off-oriented hexagonal SiC substrates. 

In this talk we give a background of on-axis grown 3C-SiC and present results on growth of 3C-SiC crystals of superior structural quality using sublimation epitaxy. Bulk-like material with a thickness of about 1 mm and surface area of 10x10 mm² can be reproducibly grown at temperatures below 2000^oC in vacuum (10^-5 mbar). The majority of growth studies were performed using 4H-SiC (0001) surfaces with the off-orientation of 4 degrees. In general, much higher density of steps on off-oriented surfaces, compared to on-axis, is a limitation in initiating 2D nucleation of 3C-SiC islands. However, under certain conditions a large facet/terrace can be formed at the edge of the substrate where an initial nucleation of 3C-SiC domains can be established. Upon growth progression, these domains enlarge laterally to cover the entire substrate surface with 3C-SiC. Such 3C-SiC substrates exhibit very high crystalline quality which was confirmed by HRXRD and LTPL analysis. The full width at half maximum (FWHM) value of ω rocking curves varied from 25 to 50 arc seconds. Typical defects in this type of growth are elongated domain boundaries which will be discussed. Unintentionally doped 3C-SiC layers with residual nitrogen concentration in a range of 10¹⁶ cm^-3 exhibit resistivity of about 10-50 Ωcm. Such 3C-SiC substrates have been used for epitaxial growth of 3C-SiC and can be employed as seeds in sublimation bulk growth. We explored growth of intentionally B, Al, N and V doped 3C-SiC layers. The dopants were introduced by co-doping from the source material. We have demonstrated highly compensated 3C-SiC with resistivity close to 10⁵ Ωcm range. I-V and C-V measurements of Schottky diodes fabricated on such material were used for the resistivity evaluation. SIMS and PL measurements have confirmed the presence of Vanadium. DLTS measurements are in progress for further identification of the deep levels. The growth issues related to dopants transfer as well as compensation mechanisms in high resistivity 3C-layers are discussed with special focus on V doped 3C-SiC material.

The Al-Ti based alloys give ohmic contacts on p-type 4H-SiC with reasonably low specific contact resistance (≤ 10^-4­ Ωcm²). Unfortunately during alloying the deposited metals go through a liquid phase [1] and contact areas lose their form. Moreover, during cooling the Al in excess segregates in Al droplets on the top of the contact surface. All that produces ohmic contacts that have not an homogeneous interface with the semiconductor and limits the minimum distance between adjacent contact areas. In previous studies it has been shown that a thin layer of metal with high melting temperature like Ni can be used as a cap on the top of the deposited Al-Ti layer for reducing or avoiding the enlargement of the melted Al-Ti film during alloying, depending on the combination of the Ni, Al and Ti thin film thicknesses [2,3]. In the same studies it was shown that it exists an optimum Ni : Al : Ti thicknesses ratios to preserve the contact form and with optically homogenous and shiny contact surfaces with specific contact resistance values in the low 10^-4 Ωcm² decade at room temperature for p-type resistivity in the range 0.1-1 Ωcm [3]. This study will focus on the electrical performence of these optimal contacts above room temperature.

4° off-axis <0001> n-type 4H-SiC homo-epitaxial specimens with a 200 nm p-type layer at the top surface have been used for this study. The p-type resistivity of these layers varied in the range 10^-2 – 10¹Ωcm. Ni(50nm)/Al(40nm)/Ti(20nm) were evaporated on the surface of these samples and circular TLM devices (TLM-C) were obtained by the lift-off technology. The intra pad-distances of these devices was in the range 4 – 49 μm, and the internal-pad-radius in the range 51 – 508 μm. After lift-off the specimens were alloyed at 1000°C for 2 min in vacuum. The preservation of the pads form factor and of a mirror like contact surfaces after alloying [3] were verified by optical inspection.

The ohmic behavior of the alloyed contact was tested by current-voltage (I-V) measurements in the temperature range 300-560 K. The specific ohmic resistance r_c and transfer length L_Twere obtained from the I-V resistance values of TLM devices versus intra-pads distance for constant internal-pad radius [4]. As a cross check, the so obtained values were verified to be good for fitting the TLM resistance data obtained from the I-V measurements of devices versus variable internal-pad radius and constant intra-pads distance [4].

The main result of this study is that, for temperatures in the range 300-560 K, the specific contact resistance of the studied contacts is in the range 2 – 4 × 10 ^-4 Ωcm² over three decades of p-type material resistivity, i.e. 10^-2 – 10¹ Ωcm, that corresponds to a range of 10³- 6×10⁴ Ω_sq sheet resistance values, taking into account the thickness of the p-type layer. Reasons for such a perfomance will be discussed.

[1] Susumu Tsukimoto, Kazuhiro Ito, Zhongchang Wang, Mitsuhiro Saito,Yuichi Ikuhara, Masanori Murakami, Materials Transactions 50(5), 1071-1075 (2009).

[2] P. Fedeli, M. Puzzanghera, F. Moscatelli, R. A. Minamisawa, G. Alfieri, U. Grossner, R. Nipoti, Mater. Sci. Forum 897, 391-394 (2017).

[3] R. Nipoti, M. Puzzanghera, M.C. Canino, P. Fedeli, G. Sozzi, submitted to ICSCRM2017, Washington, DC, Sept. 17-22, 2017

[4] D. K. Schroder, Semiconductor Material and Device Characterization, 3rd Edition, 2006, Wiley-IEEE Press.

For 4H-SiC MOSFETs, the control of MOS interface properties have been one of the most challenging issues to meet the requirements of low on-resistivity and high-reliability. The dominant factors which deteriorate the channel characteristics have not yet been clarified well. In this study the effects of the oxidant species, i.e. O₂ or H₂O on 4H-SiC MOS interface properties were investigated from the viewpoints of SiO₂ microscopic structures, to discuss the possible physical origins of the significantly different MOS electrical properties between O₂- and H₂O-oxidized interfaces.

4°-off 4H-SiC (0001) Si-face wafers covered with 5μm-thick epitaxitial layers were thermally-oxidized at different temperatures in dry-O₂ or in wet ambient prepared by flowing O₂, N₂, and their mixed gas through deionized water kept at different temperatures to control the humidity. After determining oxide thicknesses accurately by x-ray reflectivity or Si2p XPS, infrared absorption spectroscopy with attenuated total reflection mode (ATR-FTIR) of grown oxide film was investigated. The films were etched-back repeatedly in a diluted HF solution to investigate the thickness dependence of the spectrum.

The structural difference of the oxides especially in the region within a few nanometers from the interface (near-interface region) was investigated by ATR-FITR. Since the peak frequency of Si-O-Si asymmetric vibration mode sensitively reflects the strain in SiO₂ (structural strains or non-stoichiometry of the film) [1], the formation of strained structure in near interface region is indicated by a significant shift of the peak frequency when the film thickness was reduced below ~2 nm by chemical etching [2]. For the cases of dry oxidation, we also found that such strain in near-interface region was not affected at all by simply changing the oxidation temperatures [2]. Thus we can conclude that employing H₂O as the oxidant is crucial for the relaxation of near-interface SiO₂ microscopic structure. It was also found that the peak width was also smaller for H₂O-oxidation than O₂-oxidation, which indicates a formation of near-interface oxide with more uniformity in microscopic structure. It is a reasonable assumption that the relaxation of locally-strained structures would be beneficial to reduce the density of carrier-trapping sites in oxide. The superior channel performances with wet-oxidation, reported frequently for 4H-SiC (000-1) C-face [3] will be also attributable to the effects of H₂O to modify the strained structure of near-interface SiO₂.

Next we fabricated lateral n-MOSFETs on p-type 4H-SiC (0001) with dry oxidation at 1300^ºC followed by post-oxidation annealing in H₂O/O₂ mixed ambient at as low temperature as 800^ºC. Even though the low temperature annealing in wet ambient results in additional oxide growth with a small thickness around only 1 nm or less, we successfully observed a significant enhancement of the channel mobility. This result is suggesting the modification of near-interface structure is achievable by an additional oxidation of only a few monolayers of SiC surface, which is expected to reduce the near-interface trap density.

Acknowledgements: This work is partially supported by CSTI, Cross-ministerial Strategic Innovation Promotion Program, "Next-generation power electronics" (funding agency: NEDO), and by JSPS KAKENHI.

References:

[1] H. Hirai and K. Kita, Appl. Phys. Lett. 103, 132106 (2013).

[2] H. Hirai and K. Kita, Appl. Phys. Lett. 110, 152104 (2017).

[3] M. Okamoto et al., Appl. Phys. Exp. 5, 041302 (2012).

Gallium Nitride (GaN) and its alloys with Indium and Aluminum, part of third semiconductors generation, are revolutionizing both the optoelectronic and electronic device industries. Despite a previous lack of native substrates, a number of devices exceeding the performance of those fabricated from well-developed semiconductors were realized. However, the fabrication of higher performance devices with higher yields requires higher crystalline quality substrates with fully controlled electronic transport properties. Bulk ammonothermal GaN substrates, recently developed and commercialized, are characterized by low dislocation density, a single crystal nature, and high flatness; but they lack full control of the electrical properties. It is expected that films deposited by vapor transport techniques, typically with low impurities background, would allow the growth of materials with high crystalline quality and improved electrical properties. More recently, it was demonstrated that thick GaN films deposited by Hydride Vapor Phase Epitaxy (HVPE, a fast deposition process) on ammonothermal GaN substrates reproduce the high crystalline quality of those substrates, and have free carrier concentrations that are several orders of magnitude lower that of the substrates [1]. We have verified that such HVPE GaN wafers can be used for further homoepitaxial growth. This is extremely important, because it demonstrates the usefulness of this new type of substrate to fabricate highly efficient optoelectronic and electronic devices.

An ~800 mm thick HVPE film deposited on an (0001) epi-ready Ammono substrate (~0.3 degree toward "m") was removed from the reactor and its surface was chemical-mechanically polished (CMP). This template was put back in the HVPE reactor and an additional ~800 mm was deposited. The final crystal consisted of two sequentially grown HVPE-GaN layers on the Ammono substrate. The top HVPE layer was sliced off and three samples were diced from different regions of this wafer. The surfaces of these samples were mechanically polished and CMP finished. A combination of techniques was employed to investigate the structural, optical, and electrical properties of the crystals.

High resolution XRD was measured on two samples using a Rigaku Smartlab diffractometer with a four bounce Ge (220) monochromator. Lattice parameters were measured using symmetric and asymmetric scans: sample A: c=5.1856Å and a=3.1824Å; sample B were, c=5.1856Å and a=3.1839Å. These values are very close to the bulk lattice constants. The rocking curves for these samples were measured and had full widths at half maximum of ~16 arcsecs, indicating superior crystalline quality.

High lateral and depth resolution micro-Raman scattering (RS) measurements were carried out on the front and back surfaces of two samples. The E₂² phonon frequency was mapped on both faces of two samples; the distribution of Raman shifts was 567.45±0.05 cm^-1, indicating stress free GaN. The A₁(LO) phonon frequencies and the linewidths measured on the Ga-polar face were larger than those measured on the N-polar face; this is consistent with a larger incorporation of donor impurities as the growth proceeds. Low temperature, high spectral resolution photoluminescence (PL) measurements carried out on the Ga- and N-polar faces of these samples were also consistent with more doping as the growth proceeds [2]. SIMS depth profile measurements also confirm this observation. Hall measurements provided information about the free-carrier concentration and carrier mobility.

[1] T. Sochacki, et al., J.J. Appl. Phys., 53 (2014)05FA04.

[2] J.A. Freitas, Jr., et al., Cryst. Growth & Design, 15 (2015) 4837.

In recent years, free-standing gallium nitride (FS-GaN) wafers were researched due to high demand for power device, high brightness LED (HB-LED) and laser diode (LD). The GaN wafers grown by hydride vapor phase epitaxy (HVPE) have been used for the substrate of power device, HB-LED and LD because they demonstrated lower dislocation density (DD) than that of GaN wafers grown by metal-organic chemical vapor deposition (MOCVD). However, they still have residual stress and wafer bow, which lower the device productivity in mass production. To overcome these issues, the control of crystallographic quality and wafer bow are the key technologies. The crystallographic quality of the GaN wafer is mostly determined at the growth process. The bow of the wafer is determined by the difference in thermal expansion coefficient (TEC) between sapphire substrate and GaN, and it can be controlled at the wafering process. In this study, therefore, we investigated how the bow of the FS-GaN wafer is changed during wafering process. In particular, the effect of the abrasive size on the damaged layer thickness during lapping process was investigated and residual stress was calculated theoretically.

Two inch GaN wafers were fabricated on (0001) sapphire substrates by HVPE and separated by the laser lift-off (LLO) process. The bow of as-grown GaN wafer after LLO process was ranged from -300 to -100 um, which was determined by the residual thermal stress. The GaN wafer bow is changed during the wafering process, especially the lapping process. From the Stoney's formula, it is notable that the thickness of substrate (t_S) and sub-surface damaged layer (t_SSD) can change the wafer bow.

Fig. 1 shows the wafer bow (black triangle), residual stress (blue square) of experimented GaN wafer and wafer bow calculated by the Stoney's formula (red triangle). It was confirmed that the wafer bow was reduced as the thickness of GaN wafer reduced. In particular, the bow was inverted from concave to convex at the thickness of around 180 um. As the lapping process progressed, t_S is reduced and t_SSD is generated, which led to the change of bow to convex.

Fig. 2 shows the sub-surface damaged layer of the GaN wafer after lapping with 2-um diamond abrasives. It exhibits that the crystalline GaN layer was damaged by the diamond abrasives and changed to polycrystalline phase at the top surface. In addition, it indicates that the microcracks propagated into the wafer under the polycrystalline layer. Total thickness of polycrystalline layer and microcracks, t_SSD, was around 1.09 um. Thus, the t_SSD should be removed for achieving the damage-free GaN wafer.

In our presentation, we report how we achieved zero-bow FS-GaN wafer shown in Fig. 3, and how to control residual stress and optimize wafering process.

* This work was financially supported by the Brain Korea 21 Plus Program in 2017.

Figure 1

Localized p-doping is a keystone in the development of many GaN based devices that need selectively doped pocket area such as MOSFETs or PIN diodes. Electrical activation of implanted Mg has been obtained lately with GaN grown on sapphire substrate using an AlN based protective layer combined with multi cycle of rapid thermal annealing at very high temperature (>1300 °C) proving the feasibility and interest of the method [1]. The use of Si (111) substrate allows a better integration of the process on microelectronic production line. However the growth of GaN on Si (111) is less mature and necessitates a buffer usually composed of a complex staking based on AlN intermediate layers [2]. The difference in lattice parameters and thermal extension coefficient in the stacking may make the samples more unstable during the high thermal budget required for doping activation. In the last few years, several groups focused their research on the prevention of GaN surface degradation at high temperature [3] and we have shown that a combination of in situ epi deposited AlN and SiN thin layers is very efficient to avoid this phenomena [4]. Here, we propose to study the impact of high thermal annealing on the evolution of the damage in Mg-implanted GaN (on Si). Indeed, comprehensive studies of the GaN healing mechanism in this kind of structures are not yet reported. We use samples of GaN layer grown by MOCVD on Si (111) using an AlN based buffer layer and protected by an AlN/SiN_x cap layer. These samples are implanted with Mg fluences ranging from 10¹³ to 10¹⁵ at/cm² corresponding to maximum effective concentration between 5.10¹⁷ and 5.10¹⁹ at/cm³ in the implanted layer. 400 °C -1100 °C anneals are proceeded in controlled N₂ atmosphere. X-Ray Diffraction (XRD) and Photoluminescence (PL) measurements point out that ion implantation induced damage are healed thanks to different mechanisms: both lattice strain relaxation and point defect annihilation can occur during annealing with different kinetics. Indeed as we can see on Fig.1a, on samples implanted with low to medium fluence (up to 10¹⁴ at/cm²), relatively low temperature anneals (< 450 °C) are enough to obtain a near complete correction of the lattice deformation. However, surprisingly, the PL spectra of 400 °C annealed samples shown on Fig1.b indicates that a lot of non-radiative defects are still present and shutting down the PL intensity. The spectra of the sample annealed at 1100°C exhibits bands characteristic of Mg in Ga site (Mg(Ga)) which proves the necessity of a higher thermal treatment to reduce non radiative defects concentration and promote Mg incorporation in the GaN lattice. As shown on Fig 2.a, an increase of the fluence (10¹⁵ at/cm²) leads to an increase of the induced strain but also of the temperature necessary to fully relax it (1100°C). However, the PL spectra (Fig 2.b) indicates that even after such a high thermal treatment, the PL intensity of the bands associated with Mg(Ga) is weaker than for medium fluence despite the higher Mg concentration in the matrix [4]. We assume that this behavior may be due to residual damage. This is supported by Transmission Electron Microscopy images of the layer (not shown here) that evidence remaining defective pockets after a 1 h 1100 °C in N₂ annealing. These results give insight on the healing mechanism occurring during the activation anneal of Mg implanted in GaN. They also highlight that damage management is a critical parameter for GaN (on Si) p-doping via Mg implantation. To reach this objective, we will show that it is necessary to implement further specific processes to limit the implantation induced damage and to improve the damage recovery efficiency.

1. Tadjer, M.J., et al., Selective p-type Doping of GaN:Si by Mg Ion Implantation and Multicycle Rapid Thermal Annealing. ECS Journal of Solid State Science and Technology, 2015. 5(2): p. P124-P127.

2. Charles, M., et al., The effect of AlN nucleation temperature on inverted pyramid defects in GaN layers grown on 200 mm silicon wafers. Journal of Crystal Growth, 2017. 464: p. 164-167.

3. El-Zammar, G., et al., Surface state of GaN after rapid-thermal-annealing using AlN cap-layer. Applied Surface Science, 2015. 355: p. 1044-1050.

4. Lardeau-Falcy, A., et al., Capping stability of Mg-implanted GaN layers grown on silicon. physica status solidi (a), 2016.

Figure 1

For obtaining low defect density GaN substrates with controllable electronic properties for high performance electronic and optoelectronic devices, quasi-bulk growth by hydride vapour phase epitaxy (HVPE) on ammonothermal grown GaN substrates appears to be a feasible approach [1]. Synchrotron X-ray topography (white beam and monochromatic beam) has been employed to characterize dislocation configurations in such GaN substrates that were grown by HVPE on ammonothermal GaN substrate, and then slicing the substrate. Threading dislocations and basal plane dislocations (BPDs) are observed in these GaN substrates. Compared with GaN grown on sapphire and silicon carbide substrates [2], HVPE GaN on ammonothermal GaN [3] is obviously of higher crystalline quality with lower defect densities. Threading screw dislocation (TSD) density was measured to be about 880 cm^-2 while threading edge dislocation (TED) density was about an order higher (~ 5824 cm^-2). The distribution of BPDs which are induced by deformation, was found to be highly non-uniform with most regions of the wafer nearly BPD-free as well as high densities concentrated near one edge. Also, besides the surface features, like the surface scratches, arrays of threading dislocations can be seen from the transmission and grazing incidence topographs, which likely originate from scratches on the surface of the ammonothermal substrate. Correlation of the defect distributions with the HVPE growth process and their implication for devices will be discussed.

References

[1] J. A. Freitas, Jr., J. C. Culbertson, N. A. Mahadik, T. Sochacki, M. Bockowski, and M. Iwinska, Cryst. Growth Des., 15, 4837 (2015).

[2] Tian. Y, et al. Direct growth of freestanding GaN on C-face SiC by HVPE. Sci. Rep. 5, 10748; doi: 10.1038/srep10748 (2015).

[3] S. Sintonen. Synchrotron radiation x-ray topography of crystallographic defects in GaN [D]. Finland: School of Electrical Engineering, 2014. 15-24

The processing optimization necessary to achieve the GaN-based trench MOS device is reported. Devices of this type have been designed, fabricated and characterized.

The operation of the device is based on the formation of a vertical inversion layer between the gate oxide and the p-type region. In the on-condition, this requirement is satisfied through the application of a positive voltage at the gate with respect to the source. Electrons are then accumulated at the vertical interfaces (only one shown) between the gate oxide and the p-type region. In this case, electrons flow from the source through the inversion layer on the side of the gate to the drift region onto the drain.

The on-state losses are mainly determined by the resistance of the channel and the drift region. The former is controlled by the electron channel mobility while the latter by the doping level of the drift region. In the off-state (or blocking mode) the channel is removed and the p-n junction between the n- drift region and the p-type layer is reverse biased. The blocking voltage of the device is determined by the critical electric field of the drift region and its doping concentration. Furthermore, the doping level of the p-type region has to be selected based both on on-state and off-state requirements. In fact, the p-type doping value has an upper bound that is imposed by the fact that a suitable threshold voltage, between 3V and 5V, needs to be obtained. On the other hand, in off-state, at the nominal blocking voltage the p-type region must not be completely depleted in order to avoid punch-through. This imposed a lower bound on the p-type doping of the channel layer. In the same way, the n-type doping level of the drift region is bounded by the need of reasonable low on-state losses, that requires moderately high doping, and blocking voltage that impose a maximum doping level given a thickness of the drift region.

To ensure a reliable operation of the device, it is critical to control the electric field value at the interface at the bottom of the gate trench at the interface with the drift region. In fact the shape of the gate trench has to be engineered to avoid high field region that may led to a local breakdown of the gate oxide. This can be avoided by a rounded trench profile and/or gate oxide shielding by additional p-type regions.

Consideration of the above device with a blocking voltage of 5KV leads to the determination of the thickness and doping needed for both the p-type and n-type drift regions. The thickness and doping of the drift region have to be selected to maintain the maximum electric field below the critical field, which for GaN is ~3MV/cm. Allowing a maximum electric field of the order of 2MV/cm leads to the need of a drift region thickness of 50 m with a maximum doping of 2.5 x 10¹⁵ cm^-3. Moreover, first design considerations show that to avoid punch through, the p-type region has to have a doping level of 5 x 10¹⁷ cm^-3 and a thickness of 0.75 m. Devices designed with such a p-region are expected to have a threshold voltage of 4.8V.

The GaN-MOS transistor properties of the inversion layers are of paramount importance for the proposed devices. Quantitative models of the carrier transport and breakdown properties of III-Nitrides-MOS inversion layer will be developed to address them. They will include a realistic description of the semiconductor/insulator interface.

Alternative approaches such as the creation of vertical 2D electron channels will also be explored. The carrier transport and breakdown processes in high-voltage lateral and vertical devices will be an important aspect that we intend to address.

We report on two major areas: dielectric characterization, and mask design for the next research phase. Detailed electrical characterization of GaN metal-oxide-semiconductor (MOS) capacitors with atomic layer deposited (ALD) ZrO₂ high-k dielectrics from conventional tetrakis(dimethyl)amido-zirconium (TDMAZ) or novel zirconium tert-butoxide (ZTB) precursors has been ongoing. Characterization of ZTB-ZrO₂ has been of particular interest after demonstration of record positive threshold voltage for an AlGaN/GaN high electron mobility transistor, indicative of negative charge in the oxide.

The expected performance of GaN and SiC based power devices far exceeds that of Si power transistors, but the gap between the expected and achieved performance is much larger for these wide band gap materials. In these paper, we discuss new approaches for shrinking this performance gap for GaN power devices. They include using the quantum well channel designs that lead to the electron wave function penetration into wide band gap cladding layers with the commensurate increase in the breakdown voltage while keeping the advantage of a high mobility in the device channel. The gate edge engineering (beyond just using field plates) that optimizes the voltage distribution in the drain-to-gate spacing could be combined with a low conducting passivation for smoothing or even eliminating the sharp maximum of the electric field in the vicinity of the gate and field plate edges. Additional contacts in the drain-to-gate spacing for the field control and variable doping implants should allow for further optimization. The perforated channel designs could alleviate both the parasitic series resistance problem and the heat dissipation problem. Extending the gate perforations into the drain-to-gate region allows for a considerable reduction of the switching RC constant with a commensurate decrease in power dissipation. The ultimate design should use the lateral-vertical structures. The AlInN/AlN/GaN technology is uniquely poised for the breakthrough in high temperature performance. We predict that the combination of these approaches will dramatically shrink the performance gap firmly establishing GaN as a superb material for power applications.

GaN-based high-electron-mobility transistors (HEMTs) have established a ten-fold increase in power density over incumbent GaAs technology over a wide range of RF operating frequencies. The improvement in power density comes as a result of both increased breakdown voltage in the wide-bandgap nitrides and increased channel current available via polarization engineering. Next generation high-power RF HEMTs will require further increases in channel sheet charge density (n_s) to improve output power while requiring thinner barrier layers for higher frequency operation in the millimeter-wave regime. Sc_xAl_1-xN is a novel materials system consisting of an alloy between group-IIIa (transition metal) nitrides and group-IIIb nitrides, with a stable wurtzite crystal structure for x < 0.55 and a lattice-match to GaN with x ∼ 0.2. Thin films with x up to 0.43 have been reported having a factor of five enhancement of the piezoelectric response relative to AlN [1], and similar predicted enhancement in spontaneous polarization [2]. The calculated polarization discontinuity between a Sc_0.2Al_0.8N barrier layer and GaN channel gives a predicted n_s as high as 5 × 10¹³ cm^-2, a factor of five higher than a conventional Al_0.25Ga_0.75N channel device. In this talk we will show initial development of ScAlN for high-power HEMTs, focusing on molecular beam epitaxy (MBE) growth and materials characterization of ScAlN, plasma etching of ScAlN and its effectiveness as an etch stop layer (ESL), and dc characterization of ScAlN-barrier HEMTs.

Sc_xAl_1-xN thin films were grown on freestanding GaN and SiC substrates using an Omicron PRO-75 RF-plasma MBE system, equipped with an Al effusion cell and an e-beam evaporator to supply Sc. Several series of samples were grown to investigate the impact of growth temperature (360–890 °C) and III-V ratio (0.6–1.1) on Sc_xAl_1-xN crystal quality and composition. The measured ScN fraction was constant between 360–810 °C and increased at 890 °C due to Al re-evaporation from the growth surface. X-ray diffraction (XRD) rocking curve full width at half maximum values were below 300 arcsec for 80-nm-thick Sc_0.18Al_0.82N thin films for growth temperatures between 520–730 °C, indicating a wide growth window and high crystal quality. Surface rms roughness measured by atomic force microscopy was generally under 1 nm and as low as 0.7 nm at a growth temperature of 730 °C. XRD measurements indicated single crystalline phase epitaxial Sc_xAl_1-xN for N-rich samples (III/V ratio < 1) and the emergence of additional phases for samples grown metal-rich.

In addition to having high spontaneous and piezoelectric polarization, Sc_xAl_1-xN also has a relatively low etch rate in Cl₂-based dry etching commonly used for GaN and AlN. The etch selectivity is as high as 11.2 relative to AlN and 18.6 relative to GaN. The etched surface remains smooth with no increase in the rms roughness or evidence of pitting or micromasking. There are several etch methodologies that allow selective etching of Al-containing layers relative to GaN, but this is the first demonstration of a conventional dry etch chemistry with a working ESL relative to AlN, leading to a variety of applications in AlN-based electronic devices and deep-UV optoelectronics.

Using a 25-nm-thick Sc_0.14Al_0.86N barrier layer in a GaN-based HEMT structure, we demonstrate the first ScAlN-barrier HEMTs with n_s as high as 3.4 × 13 cm^-2 and mobility of 910 cm²\Vs, resulting in a sheet resistance of 213 Ω/□. Reducing the ScAlN barrier thickness to only 3 nm results in an n_s of 2.0 × 10¹³ cm^-2 with a mobility of 1060 cm²/Vs. Both devices included both AlN and GaN interlayers to improve the mobility. These results demonstrate the potential for ScAlN as a barrier material in a highly-scaled, high charge density HEMT for high power millimeter-wave amplifiers.

[1] M. Akiyama, K. Kano, and A. Teshigahara, "Influence of growth temperature and scandium concentration on piezoelectric response of scandium aluminum nitride alloy thin films," Appl. Phys. Lett., vol. 95, p. 162107, 2009.

[2] M. A. Caro, S. Zhang, T. Riekkinen, M. Ylilammi, M. A. Moram, O. Lopez-Acevedo, et al., "Piezoelectric coefficients and spontaneous polarization of ScAlN," J. Phys.: Condens. Matter, vol. 27, p. 245901, 2015.

Wide bandgap GaN photoconductive semiconductor switches (PCSSs) have gained recent attention due to high critical electric field strength and high electron saturation velocity to provide high power ultrafast devices. To reduce leakage currents, PCSSs have previously been demonstrated on semi-insulating GaN achieved by Fe compensation doping. However, Fe is known to have strong memory effects, which can redistribute Fe into subsequent films, as well as a narrow window of acceptable doping levels. PCSSs with fast response time are required for applications requiring high repetition rates. C-doped GaN is used to reduce leakage current and improve the photocurrent of lateral PCSSs. The C-doping is performed by simply tuning the growth parameters, such as temperature, pressure and III/V ratio and creates shallow accepter levels, compensating any unintentional n-type doping. In this work, we demonstrate high voltage GaN:C PCSSs with fast response times measured using a picosecond pulsed laser and high breakdown voltages, over 4000 V, measured in a vacuum probe station.

To increase the breakdown voltage (BV) and, in the same time, decrease the on-state voltage (OSV) of wide-band gap transistors it is essential to carefully design the doping profile of these transistors in order to decrease the resistivity of the material during the on-state current flow and decrease the impact ionization generation rate in regions with high electric field during off-state. In general, the two problems depend on each other and there is trade-off between the increasing the BV and decreasing the OSV [1]. In this article we will analyze this tradeoff by using the formalism of doping sensitivity functions of the BV and OSV. These functions show how sensitive the BV and OSV are to infinitesimal variations of the acceptor or donor impurities inside the semiconductor. For instance, the doping sensitivity function of the BV, g_BV(r), shows how much the BV increases by adding one donor impurity at location r inside the device. Similarly, the doping sensitivity function of the OSV, g_OSV(r), shows how much the OSV increases by adding one donor impurity at location r inside the device. As we have shown in [2, 3], the doping sensitivity functions are instrumental in the optimization of WBG power devices.

The doping sensitivity functions of the BV and OSV can be computed efficiently by using the adjoint method. Once these functions are computed they can be coupled with gradient-based optimization methods to estimate the optimum doping profiles for acceptors, N_a(r), and donors, N_d(r), in order to increase the BV and decreases the OSV. At the conference we will describe the numerical implementation of the adjoint method for the optimization of WBG power devices and present simulation results for a vertical and horizontal SiC MOSFETs. More importantly, we will show that in general, in wide-band-gap MOSFETs and IGBTs, the doping sensitivity functions of the BV and OSV, g_BV(r) and g_OSV(r), respectively, and are not linearly dependent. Therefore, from a mathematical point of view, the BV and OSV are quantities that can be controlled independently by changing the doing profiles inside the transistor. Different equivalent ways to define and compute the doping sensitivity functions of BV and OSV will also be presented. The different definitions of the doping sensitivity functions will be compared to each other and the computational complexity will be discussed in each case.

[1] J. Baliga, Fundamentals of Power Semiconductor Devices: Springer, 2008.

[2] P. Andrei, "Using Doping Sensitivity Functions to Optimize Power Transistors," IEEE Workshop on Microelectronics and Electron Devices (WMED), Boise, ID, 2015.

[3] C. Zhu and P. Andrei, "Adjoint Method for Increasing the Breakdown Voltage and Reducing the On-State Resistance in Wide Band", 231 ECS Meeting, New Orleans, 2017.

[4] P. Andrei and L. Oniciuc, "Suppressing Random Dopant-Induced Fluctuations of Threshold Voltages in Semiconductor Devices," Journal of Applied Physics, vol. 104, Art. No. 104508, 2008.

Due to excellent intrinsic properties of silicon carbide (SiC), SiC power metal oxide semiconductor field effect transistors (MOSFETs) potentially become a desirable candidate featuring high blocking voltage with ultra-low conduction resistance for high efficiency power applications [1]. In order to achieve expected avalanche breakdown in SiC device, junction termination techniques are paramount to alleviate the crowded high electric field at the periphery of active regions [2]. Previous works related with various SiC junction termination techniques mainly focus on junction termination extension (JTE) and related variations, like hybrid, bevel-assist, multiple-shallow-trench, and counter-doped JTE [3-5]. However, little reports on field limited rings (FLRs) technique for SiC power device are released. Actually, the FLR technique features less tight process control and desirable reliability, benefiting SiC-based industrial power applications.

In this paper, three section adjusted field limited rings (TS-FLRs) are proposed and fabricated for 2200V rating for motor extraction applied in high-speed trains and hybrid/electric vehicles. The proposal not only avoids tight control of etching depth and ion implantation dose required by aforementioned multiple JTE structures, but also shows a desired process tolerance without complicated designs and extra process step for the TS-FLRs.

The schematic cross-section view of the proposed TS-FLRs is fabricated on an 18μm thick drift layer of with doping concentration of 5E15 cm^-3 as shown in Fig. 1. The TS-FLRs are implanted with formation of P base region of active region in same process step, followed by an 1800 degree C high temperature activation. Then a thick passivation layer is deposited on the termination region to effectively avoid influences from following processes. The TS-FLRs is designed to three sections characterizing space of FLRs S₁ and width of FLRs W₁ in section I, S₂ and W₂ in section II, as well as S₃ and W₃in section III for substantially reducing design complex of FLRs.

Firstly, due to formation at same fabrication step, the total implantation dose is carefully considered for both BV and V_th. TS-FLRs have an evidently better stability based on different total doses than that of fixed space and same width ones (F-FLRs) as shown in Fig. 2. Moreover, the TS-FLRs evidently show stable breakdown performances dependent on various spaces while a weak tolerance of space definition of F-FLRs.

Furthermore, the influence of TS-FLRs with different widths of ring and with different max energies of implantation on breakdown voltage is evaluated, combining analysis of electric field distribution inside termination region by Sentaurus simulation.

After optimized design, TS-FLRs and F-FLRs are fabricated at same process level with SiC power MOSFETs as shown in Fig. 3. Fig. 4 shows that the breakdown voltage of the MOSFETs with TS-FLRs is as high as 2500V, a significant enhancement in comparison with F-FLRs.

Acknowledge: The authors thank China Railway Rolling Stock Corporation.

Reference:

• J. W. Palmour, L. Cheng, V. Pala, E. V. Brunt, D. J. Lichtenwalner, G. –Y Wang, J. Richmond, M. O'Loughlin, S.Ryu, S. T. Allen, A. A. Burk and C. Scozzie, "Silicon Carbide Power MOSFETs: Breakthrough Performance from 900V up to 15kV," 2014 26th Int. Symp. Power Semiconductor Devices ICs (ISPSD)., pp.79-82, Jun. 2014, doi: 10.1109/ISPSD.2014.6855980.

• T. Kimoto and J. A. Cooper, Fundamentals of Silicon Carbide Technology: growth, characterization, devices and application. Singapore: Wiley, Nov. 2014.

• W. Sung, B. J. Baliga and A. Q. Huang, "Area-Efficient Bevel-Edge Termination Techniques for SiC High-Voltage Devices," IEEE Trans. on Electron Devices., vol. 63, no. 4, 2016, pp. 1630 - 1636, doi: 10.1109/TED.2016.2532602.

• H. Elahipanah, A. Salemi, C.-M. Zetterling and M. Ostling, " 5.8-KV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension," IEEE Electron Device Letters., vol. 36, no. 2, pp. 168 - 170, Feb. 2015, doi: 10.1109/LED.2014.2386317.

• J. -Y. Jiang, H.-C. Hsu, K.-W. Chu, C.-F. Huang and F. Zhao, "Experimental Study of Counter-Doped Junction Termination Extension for 4H–SiC Power Devices," IEEE Electron Device Letters., vol. 36, no. 7, pp. 699 - 701, July. 2015, doi: 10.1109/LED.2015.2428617.

Figure 1

SiC- and GaN-based power semiconductor devices have in the past few years enabled great improvements in the efficiency and power density of switching power converters. A wide variety of SiC devices (e.g. MOSFETs, JFETs, BJTs, thyristors, and PiN/Schottky/JBS/MPS diodes) are now available from a number of manufacturers, and the same is true for GaN HEMTs. Thus, while vertical GaN devices are not yet mature, new research in the field is increasingly turning to the "ultra" wide-bandgap (UWBG) semiconductors, including diamond, gallium oxide, and aluminum gallium nitride (AlGaN), due to the expected scaling of the critical electric field as the bandgap to the 2.0-2.5 power. Notably, AlGaN is an alloy system, so that heterostructures are available, and it is also a polar material, which enables polarization doping. Both of these benefits significantly expand the range of device architectures that may be considered, compared to materials that do not have these properties; this is especially significant for UWBG materials, all of which have energetically deep impurity dopants that do not fully ionize at room temperature. This talk will report on both vertical PiN diodes and lateral HEMTs composed of Al-rich Al_xGa_1-xN (x ≥ 0.7, E_G ≥ 5.2 eV) designed as prototype power switching devices.

The talk will begin with an overview of the properties of AlGaN that motivate its application to power switching, as well as an analysis of conduction and switching loss mechanisms as a function of AlGaN bandgap for various device types (PiN diodes, Schottky diodes, etc.) These results will be compared to similar metrics for SiC, GaN, and UWBG materials other than AlGaN. The talk will then present results on several PiN diode structures. All of the structures to be presented have thick (5-8 mm) Al_0.7Ga_0.3N drift regions doped in the 1-3×10¹⁶ cm^-3 range, and were grown on thick (1.3 mm) sapphire substrates; due to the insulating nature of the substrate, the cathode contact is to a heavily-doped n-layer on the front side of the wafer in a so-called "quasi-vertical" configuration. The diodes differ in the design of the p-type anode. Homojunction diodes suffer from low free carrier density in the p-Al_0.7Ga_0.3N due to the low fraction of Mg than is ionized in material of such a wide bandgap (E_A > 400 meV). Thus, two alternate approaches to achieve appreciable hole density were examined: heterojunction diodes in with the anode is composed of Al_0.3Ga_0.7N, in which reasonable Mg activation can be achieved; and diodes utilizing anodes in which the composition is graded from Al_0.7Ga_0.3N down to GaN. In order to avoid premature edge and/or surface breakdown, all diodes studied utilized a junction termination extension formed by nitrogen implantation into the p-region.

The talk will conclude with a presentation of a second class of device, which is a power switching HEMT utilizing an Al_0.85Ga_0.15N/Al_0.70Ga_0.30N heterostructure. This heterostructure, which as a 25 nm thick barrier, is characterized by a pinch-off voltage of -4.5 V, a channel mobility of 250 cm²/Vs, and a channel sheet charge density of 6×10¹² cm^-2. The key challenge for Al-rich HEMTs has been the formation of Ohmic source and drain contacts; the current density in previous HEMTs reported by our group has been limited by the quasi-rectifying nature of these contacts. The HEMTs in the present work utilize planar source and drain contacts, as opposed to the etched-and-regrown contacts that we have reported previously; for those previous contacts, the regrown material was heavily-doped n-type GaN. The planar contacts in this study are composed of a Ti/Al/Ni/Au stack deposited directly on the Al_0.85Ga_0.15N barrier. While the current-voltage characteristics of these contacts are still quasi-rectifying, they have enabled a current density of 46 mA/mm, which is more than ten times greater than that achieved in our previous-generation AlGaN-channel HEMT, which had comparable channel sheet resistance. An effective breakdown field of ~170 V/um was achieved in a field-plated device with 4 um gate-to-drain spacing. This effective breakdown field exceeds that typically reported for GaN-channel HEMTs (~100 V/um), demonstrating the potential of AlGaN-channel HEMTs for high-performance power switching devices.

This work was supported by the Laboratory Directed Research and Development (LDRD) program at Sandia. Sandia National Laboratories is a multi-mission laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.

Increasing global demand for energy makes urgent the need for highly efficient electronics for energy conversion and transport. Power electronics are required for electrical switching within the electrical grid and for green modes of transportation such as the in-switched-mode power supplies now used for hybrid electric vehicles. Silicon devices have been traditionally used for power electronics. However, wide bandgap semiconductors are much more efficient and thus more useful for future energy applications, because they can withstand higher electric fields with less material and reduced energy loss. As an example, Toyota recently began trials of a new hybrid system using power electronics based on SiC and claims that power electronic devices based on SiC could increase fuel efficiency of hybrid vehicles by 10%. Almost all high-power electronic devices are fabricated in very thick films grown on low defect density semi-insulating substrates of the same composition and crystal structure. At present, 4H-SiC is the material of choice for both substrates and films for devices operating at and above 1200 volts. The upper limits of operation for power devices fabricated in GaN-based films are markedly lower. And the substrates of both materials are highly textured polycrystalline materials and still very expensive. A very promising alternative to SiC and GaN is gallium oxide, Ga₂O₃, which has an even larger bandgap than the former two materials. The availability of this material presents new possibilities for disruptive devices and technologies that could translate to even greater energy efficiencies at lower cost than predicted for SiC and GaN.

Ga₂O₃ is known to exist in five polymorphs, i.e., α-, β-, γ-, δ-, and ε-phases. The monoclinic β-phase is the most thermodynamically stable phase. Single crystal boules of this phase can be grown using inexpensive melt-growth methods. Polished 2-in diameter wafers diced from these boules and oriented homoepitaxial films have recently become commercially available. However, there is increasing interest in the other phases, particularly the metastable corundum-structured α- and hexagonal-structured ε-Ga₂O₃ phases. Both of these phases have been observed to grow epitaxially on oriented substrates. We have successfully grown epitaxial films of α-, β- and ε-phases on c-plane sapphire using different precursors flow rates and growth conditions. The α- and ε-phases have generally been reported in the literature to form at lower growth temperatures than the β-phase However, we observed a change in phase formation at the same growth temperature by changing our growth technique and Ga precursor from metalorganic chemical vapor deposition (MOCVD) and trimethlygallium to halide vapor phase epitaxy (HVPE) and gallium chloride. The HVPE method allowed a significantly higher growth rate than MOCVD and is, therefore, advantageous for growth of the very thick films needed in high-power devices. The α- and ε-phases are of particular interest because of their higher symmetry and simpler epitaxial relations to c-plane sapphire. Moreover, given their similar structures to other wide bandgap materials such as ZnO and AlN, it should be possible to produce functional heterostructures or tunable bandgaps through alloying. Frequently, a thin interfacial layer of the α-phase is observed to grow on the substrate, before it undergoes a phase transition to the ε-phase. By varying the total gas flow rate as well as the Ga:O flow ratio, we observed different relative thicknesses of the two competing phases. Data from x-ray diffraction, scanning electron microscopy and high-resolution transmission electron microscopy will be presented to illustrate the different epitaxial films. The results of secondary ion mass spectroscopy of the various phases will also be presented, as these data suggest that compositional differences may exist among the phases. Additionally, α- and ε-Ga₂O₃ are metastable phases; however, we have observed these phases to be stable up to at least 750^oC. Only after prolonged annealing at T> 800^oC did they begin to undergo a transformation to the β-phase. These reasonably high working temperatures justify further investigation of α- and ε-Ga₂O₃-based devices. The authors wish to acknowledge the Office of Naval Research under contract no. N00014-16-P2059.

Diamond transistors with surface 2D conduction channels are projected to be radiation hard with respect to neutrons. However, ionizing radiation hardness may be a problem due to the disruption of the 2D hole concentration. In this paper, the processing of three terminal devices with 2D surface conducting channels is presented as well as analysis of device transfer characteristics. This paper addresses the fabrication, radiation induced defects and device characteristics of microwave power field effect transistors (FET) built on 1) high quality diamond surfaces exploiting the 2 dimensional surface conductivity, and 2) the surface two dimensional "hydrogen terminated" conduction layer in diamond single crystals grown by CVD.

Diamond is an ultra-wide bandgap semiconductor material that exhibits a number of ideal properties for future power and RF electronics applications beyond the current generation of SiC- and GaN-based technology. These properties include a bandgap of 5.5 eV, a high breakdown field (>10 MV/cm), high theoretical room-temperature carrier mobilities (>3800 cm²/V*sec), extremely high thermal conductivity (>22 W/cm*K), and excellent mechanical and thermal stability in vacuum. However, diamond doping is difficult, as the activation energies for typical dopants (B, P) exceed 0.37 eV and lead to very low dopant activation levels.[3] This drawback of dopant activation efficiency has been, in part, mitigated by two-dimensional conductivity found in hydrogen-terminated diamond surfaces. Hydrogen-termination (usually accomplished via exposure to hydrogen plasma) has been found to create a C-H surface dipole layer that reduces the carrier ionization energy by nearly 1.5 eV. Adsorbed species, such as atmospheric H₂O, NO₂, or intentionally-introduced passivation species contact this dipole layer, and together generate a two-dimensional hole gas (2DHG) with 10¹³-10¹⁴ holes/cm² carrier density several nanometers below the diamond surface.

Hydrogen-terminated diamond has been used as the basis for metal-semiconductor field effect transistors (MESFETs) and metal-oxide-semiconductor field effect transistors (MOSFETs) hydrogen-terminated diamond. Both unpassivated and passivated surface conduction devices have been fabricated. In the case of unpassivated devices, exposure to air (and thus atmospheric H₂O) causes the devices to exhibit sheet charge densities in the 10¹³ holes/cm² range.[1] MESFETs typically rely on Au metal for Ohmic contacts and Al metal for Schottky contacts to the hydrogen-terminated diamond. These devices have been normally-on devices, with threshold voltages around between -1V to +1V, depending on device dimensions.[1-4] MOSFETs fabricated using atomic layer deposited (ALD) oxides such as Al₂O₃ have been fabricated with either normally-off or normally-on behavior, depending on thermal history. Annealing of these devices at 180°C caused the devices to switch from normally-on to normally-off, with threshold voltages again in the range of ±1V range; the change was likely due to the removal of adsorbed species in the unpassivated diamond surfaces between the source, gate, and drain regions in the device, causing a reduction in the 2DHG sheet carrier density.[4]

The diamond materials and surface preparation supplied by Euclid Techlabs using proprietary processes to produce defect free, ultra-smooth (S_a ~ 0.2 nm) diamond surfaces and buried boron 'delta doped' CVD layers. Euclid techlabs has demonstrated the delta doped transport channels in Diamond have mobilities in excess of 700 cm²/V sec. Device design and process science development was carried out within the facilities of the UMD NanoCenter and the NanoFab Lab. Radiation testing has been carried out at the radiation facilities of the University of Maryland.

Device electrical performance and characterization has been carried out. We perform baseband noise, as well transconductance/output resistance dispersion characterization of 2D Surface Channel Diamond FETs fabricated under different processes and having different geometry and designs in order to identify device defects and their reliability and their susceptibility to radiation effects. The impact of the various types of noise on device defect and radiation hardness will be reported. Materials characterization techniques including Raman spectroscopy (strain, sp2 vs sp3 bonding), FTIR, and SIMS. Common diamond point defects are characterized by photoluminescence and FTIR.

References:

[1] M. Kubovic, M. Kasu, Y. Yamauchi, K. Ueda, H. Kageshima, "Structural and electrical properties of H-terminated diamond field-effect transistor," Diamond and Related Materials 18 796-799 (2009).

[2] M. Kasu, K. Ueda, H. Kageshima, Y. Yamauchi, "Gate interfacial layer in hydrogen-terminated diamond field-effect transistors," Diamond and Related Materials 17 741-744 (2008).

[3] D.A.J. Moran, O.J.L. Fox, H. McLelland, S. Russell, P.W. May, "Scaling of Hydrogen-Terminated Diamond FETs to Sub-100nm Gate Dimensions," IEEE Electron Device Letters 32 [5] 599-601 (2011).

[4] S.A.O Russell, S. Sharabi, A. Tallaire, D.A.J. Moran, "Hydrogen-Terminated Diamond Field-Effect Transistors With Cutoff Frequency of 53 GHz," IEEE Electron Device Letters 33 [10] 1471-1473 (2012).

Ultrawide bandgap (UWBG) gallium oxide (Ga₂O₃) represents an emerging semiconductor material with excellent chemical and thermal stability up to 1400 ^oC. It has a band gap of 4.5-4.9 eV, much higher than that of the GaN (3.4 eV) and 4H-SiC (3.2 eV). It exhibits high transparency in the deep ultraviolet (DUV) and visible wavelength region due to its very large bandgap. The monoclinic b-phase Ga₂O₃ represents the thermodynamically stable crystal among the known five phases (α, β, γ, δ, ε). The breakdown field of β-Ga₂O₃ is estimated to be 8 MV/cm, which is about three times larger than that of 4H-SiC and GaN. These unique properties make β-Ga₂O₃ a promising candidate for high power electronic device and solar blind photodetector applications. More advantageously, single crystal β-Ga₂O₃ substrates can be synthesized by scalable and low cost melting based growth techniques such as edge-defined film-fed growth (EFG), floating zone (FZ) and czochralski methods. For β-Ga₂O₃ thin film synthesis, both molecular beam epitaxy (MBE) and metalorganic vapor phase epitaxy (MOVPE) have been demonstrated to produce high quality and controllable doping films but with slow growth rates (2-10 nm/min). Halide vapor phase epitaxy (HVPE) using chloride precursors was demonstrated to grow β-Ga₂O₃ films with fast growth rates (>5 μm/hr). Recently, we have developed a low pressure chemical vapor deposition (LPCVD) method to grow high quality β-Ga₂O₃ thin films on both native Ga₂O₃and c-sapphire substrates with controllable doping and fast growth rates up to 10 μm/hr.

In this talk, we present a study on the defects in β-Ga₂O₃ thin films grown via LPCVD. The β-Ga₂O₃ thin films were grown on native β-Ga₂O₃ substrates and sapphire substrates using high purity gallium and oxygen as the precursors, and argon (Ar) as the carrier gas. The growth temperature ranged between 850 ˚C and 950 ˚C. The β-Ga₂O₃ thin films were characterized by using field emission scanning electron microscopy (FESEM) and transmission electron microscopy (TEM). FESEM images were taken with Helios 650. High resolution transmission electron microscopy (HRTEM) images and selected-area electron diffraction (SAED) were taken using a FEI Tecnai F30 at 300 kV. Bright field, dark field, combined with two-beam condition TEM were used to characterize the defects in the as-grown films. From our studies, β-Ga₂O₃ thin films grown on (010), (001) and (-201) β-Ga₂O₃ substrates have shown different growth rates as well as different properties of interfacial defects. Improved LPCVD growths to suppress defects in β-Ga₂O₃thin films grown on different substrates will be discussed. Room temperature Hall measurements will be performed to understand the dependence of carrier transport on defects.

In summary, the fundamental defect studies are performed on β-Ga₂O₃ thin films grown via LPCVD on Ga₂O₃ and sapphire substrates. The results from this study are important knowledge for power device applications.

Lateral and vertical power switching devices being intensively developed in GaN and SiC materials are beginning to reach a state of maturity and to displace traditional Si devices in certain applications. The relative advantage of these wide bandgap materials, which stems from intrinsic materials properties, can be compared in terms of an applicable figure of merit (FOM), indicating theoretical limits [1]. The most commonly discussed FOM for power applications is the unipolar FOM [2], based on reduction of conduction losses in the on-state and high voltage blocking in the off-state of vertical devices, V_B²/R_on,sp = εμ_nE_c³/4, where V_B is the off-state avalanche breakdown voltage, R_on,sp is the specific on-state resistance, ε is the semiconductor permittivity, μ_n is the electron mobility, and E_c is the critical electric field. The unipolar FOM scales as the cube of E_c, which is itself a strong function of the bandgap [3], leading to the key advantage for wide bandgap materials. Possessing bandgaps wider than GaN (3.4 eV), AlGaN alloys are expected to provide improved performance. We have investigated quasi-vertical Schottky barrier diodes, consisting of nominal Al_0.8Ga_0.2N drift layers grown on high quality AlN single crystal substrates. HexaTech has developed proprietary seeded AlN crystal growth technology based on physical vapor transport (PVT), allowing iterative expansion of single crystal size, while maintaining low dislocation density (<10³ cm^-2), as determined by x-ray diffraction and defect-selective etching. AlN boules were oriented, sliced, lapped, and chemo-mechanically polished (CMP) to produce epi-ready c-plane substrates. Due to the highly insulating nature of the Al-face AlN substrates (resistivity >10¹³ Ωcm at room temperature), quasi-vertical Schottky diode structures were grown by metal-organic chemical vapor deposition (MOCVD). The device structure consisted of an AlN homoepitaxial layer, followed by a 0.6 µm thick pseudomorphic Si-doped Al_0.8Ga_0.2N contact layer ([Si] ~2x10¹⁹ cm^-3), a 1 µm thick low-doped Al_0.8Ga_0.2N drift layer, and a 0.3 µm Mg-doped AlN cap layer ([Mg] ~2x10¹⁸ cm^-3), serving as a junction termination extension (JTE). Despite the high activation energy of the Mg dopant in AlN, the Mg acceptors are expected to be ionized under high reverse bias, due to the strong band bending. Following epitaxial growth and dopant activation, circular device mesas were defined by dry etching down to the n-AlGaN contact layer, the JTE region atop the mesa was defined into a series of lateral steps and the Schottky contact area was etched down to the drift layer, Ohmic contacts were deposited and annealed, circular Schottky contacts were deposited, and a blanket polyimide passivation layer was deposited and patterned. Schottky diodes with diameters ranging from 0.3 to 1.0 mm were fabricated. Capacitance-voltage measurements were used to determine the free carrier concentration of the drift region, 2.0x10¹⁷ cm^-3. The forward and reverse current-voltage characteristics were measured as a function of temperature. The specific on-state resistance was 125 mΩcm² at room temperature and 190 mΩcm² at 150 °C, which is partly attributed to high contact resistance. Diodes exhibited a current rectification ratio of ~10⁶. The off-state breakdown voltage was up to 500 V. Breakdown tended to be destructive, likely limited by the polyimide passivation, suggesting improved blocking performance could be achieved with a better dielectric and more developed edge termination strategy. Field calculations based on the measured carrier concentration and breakdown voltage indicated a trapezoidal electric field in the drift region with a 7 MV/cm field at the Schottky junction. This talk will review growth and expansion of high quality AlN single crystals by PVT, and fabrication of epi-ready AlN substrates. Results for high Al composition Schottky diodes grown on these substrates will be presented. Challenges for this emerging technology, including doping limitations and compensation in AlGaN alloys, Ohmic contacts, and device termination will be discussed.

[1] T. P. Chow, I. Omura, M. Higashiwaki, H. Kawarada, and V. Pala, IEEE Trans. Electron Devices, 64, 856 (2017).

[2] K. Shenai, R. S. Scott, and B. J. Baliga, IEEE Trans. Electron Devices, 36, 1811 (1989).

[3] J. L. Hudgins, G. S. Simin, E. Santi, and M. A. Khan, IEEE Trans. Power Electron., 18, 907 (2003).

The market for power electronic devices is highly competitive among devices made of silicon (Si), silicon carbide (4H-SiC) and gallium nitride (GaN) – devices with best performance and reliability at lowest cost will win the race. The price of SiC devices depends on material costs and device production yield, the latter one is limited by technological and structural defects. The device performance is a matter of device design and process technology, and the device reliability is often limited by structural defects. Hence, a characterization method for structural defects in substrates, epiwafers and partially processed wafers is a keystone for development of competitive SiC power electronic devices. Photoluminescence imaging with excitation in the ultraviolet range (UVPL imaging) is an established and powerful technique for such process-accompanying measurements of SiC wafers and we will review its current status in our talk.

In this paper we will compare different UVPL imaging systems available on the market in terms of UV excitation parameters and their PL detectors and discuss their defect detection capabilities. We will present the visibility of structural defects in substrates and epiwafers with regard to their defect-specific PL wavelength as well as excitation wavelength and intensity. SiC epiwafers can be optically stressed by using high excitation intensity, i.e. the conversion of basal plane dislocations to stacking faults can be provoked in unprocessed material as shown in figure 1. This "optical stress test" can be used for material quality testing prior to device processing as well as for scientific questions such as the velocities of dislocations. Furthermore, we will present UVPL images of partially processed SiC wafers revealing technologically induced structural defects. In case of 6.5 kV PIN diodes, the UVPL measurements allow even for prediction of bipolar device degradation.

UVPL imaging provides fast, non-destructive defect characterization on full-wafer area and allows for targeted process optimization in epitaxial growth and device processing as well as for process control measurements. Defects can be tracked from substrate/epiwafer to different stages of device production. Hence, UVPL imaging is of great importance for cost reduction and reliability improvement of SiC power electronic devices.

Figure 1

Grazing-incidence X-ray topography and photoluminescence (PL) imaging are utilized to understand the nature and behavior of extended defects in 4H-SiC. Although these methods are useful for non-destructive defect analysis, they provide two-dimensional (2D) images with low depth resolution. Advanced three-dimensional (3D) imaging methods are thus expected to be used for characterizing extended defects. In particular, very high-voltage SiC bipolar devices with a thick epilayer require defect imaging as deep as 100-200 μm. We established a 3D imaging technique using an X-ray microbeam and a novel fine slit, which was successfully applied to characterizing threading screw dislocations (TSDs) [1, 2], threading edge dislocations (TEDs), and basal-plane dislocations (BPDs) [3, 4] in 4H-SiC. However, this method requires a large-scale synchrotron-radiation facility.

In this study, we show how second-harmonic generation (SHG) and two-photon-excited photoluminescence (2PPL) imaging techniques are powerful tools for 3D analysis of extended defects in 4H-SiC epilayers [5, 6]. The SHG and 2PPL methods can be performed by a multi-photon microscope in individual laboratories. The SHG method provides clear 3D images of 3C-inclusions because 3C-SiC is SHG-active, but not 4H-SiC host crystal in c-axis incidence (Fig. 1). The 2PPL method yields 3D images; not only of 3C-inclusions but also 8H stacking faults (Fig. 2), and single Shockley stacking faults in the epilayers.

The 2PPL method also achieved 3D imaging of TSDs, TEDs, and BPDs using band-edge emission [7]. Since band-edge emission quenches near defects, these dislocations can be visualized as dark contrasts on a bright background. We obtained 3D images of TSDs and TEDs extending ~200 μm from the surface (Fig. 3). Unlike 2D PL imaging with uniform illumination, the dark-contrast imaging is governed by the diffusion and transport of excess carriers injected from a scanning focal point. A simulation study was conducted to reveal the mechanism of the dark-contrast imaging.

Each of the dislocations provided 2D dark-contrast images stacked depthwise, from which the tilt angles of dislocations were determined. Figure 4 shows the plots of φ versus θ for 89 TSDs in the 4º off epilayer, where θ denotes the angle of the dislocation line from the c-axis, and φ the counter-clockwise angle of (0 0 0 1) projected dislocation lines from the step-flow [1 1 -2 0] direction. Their dislocation lines incline in the step-flow direction. It is also shown that the regions of left- and right-handed (LH and RH) dislocations clearly differ. The plots in Fig. 4 include those of 1c and c+a dislocations. We found that 1c dislocations had very similar tilt angles, whereas those of c+a dislocations were largely spread out. The tilt angles were also investigated for 105 TSDs in the 8º off epilayer, which exhibits larger θ angles　and a smaller φ range than the 4º off-cut case. We examined the tilt angles of more than 300 TEDs and found that the TEDs not only inclined in the step-flow direction, but also the direction of the extra half planes [7].

The results of the tilt-angle analyses cannot be explained by the energy minimization model in bulk materials. We consider that the directions of TEDs and TSDs depend upon the interactions between dislocations and advancing steps on a growing surface.

[1] R. Tanuma, T. Kubo, F. Togoh, T. Tawara, A. Saito, K. Fukuda, K. Hayashi, and Y. Tsusaka, Phys. Status Solidi A 204, 2706 (2007).

[2] R. Tanuma, T. Tamori, Y. Yonezawa, H. Yamaguchi, H. Matsuhata, K. Fukuda, and K. Arai, Material Sci. Forum 615-617, 251 (2009).

[3] R. Tanuma, D. Mori, I. Kamata, and H. Tsuchida, Appl. Phys. Express 5, 061301 (2012).

[4] R. Tanuma, D. Mori, I. Kamata, and H. Tsuchida, J. Appl. Phys. 114, 023511 (2013).

[5] R. Tanuma and H. Tsuchida, Appl. Phys. Express 7, 021304 (2014).

[6] R. Tanuma and H. Tsuchida, Mat. Sci. Forum 778-780, 338 (2014).

[7] R. Tanuma, M. Nagano, I. Kamata, and H. Tsuchida, Appl. Phys. Express 7, 121303 (2014).

Figure 1

Silicon Carbide continues to become more mainstream and enjoy adoption in various high voltage applications. With the growth of volume and variety of devices shipping to customers, it is important to understand the yield and reliability implications of all the defects that are present in the substrates and epitaxial layers. In our previous works [1,2] we published ways of detecting and screening reliability causing crystal defects. There are however a variety of visible defects present both in the bare substrates and after epitaxial growth. In this work we present the detection and classification of these defects into killer and non-killer defects as measured by electrical tests after device fabrication. This methodology enables the accurate prediction of yield before starting the wafers for device fabrication. We then extend this method to predict yield on various product dies sizes and validate those results experimentally.

We have worked to detect all the visible defects present in our epitaxial layers. However due to the large variety of defects present and their varying effect on device performance, just detection is not enough. The defects have to be finely classified into various defect types to gauge their electrical impact. We have classified the defects into various types of triangular defects, fall-down particles, carrots, scratches, pits, step bunching, V-type defects [2,3], large and small topographic defects and defects related to manual handling. Through an iterative process involving electrical characterization of fabricated Schottky barrier diodes (SBD) we have determined which of these classes are killer defects. It is found that mainly fall-down particles, a subset of triangular defects, carrots and large topographic defects are the main causes of electrical failure at wafer sort. Other defects like fainter obtuse triangular defects [4], V-type defects, scratches, step-bunching and pits do not cause outright fails. Second degree effects are observed for many of these non-killer defect types. Other purely crystal defects having no visible defect signatures like basal plane dislocations, stacking faults, grain boundaries were also detected and classified. However these were also determined not to have any influence on SBD device yield at wafer sort.

Once the killer defects are determined after epitaxial growth, we created a yield model based on the actual die grid of our actual physical device layout. The yield prediction of this model was tested experimentally and validated for different wafers across multiple lots. A very close agreement of ±2% was observed across all the wafers. This model enables us to predict wafer yield right after epitaxy and before starting the wafers in the fabrication line very accurately. As product lines involve multiple current ratings with different die sizes, a further enhancement of this model was done to predict the yield on a wide variety of die sizes corresponding to device current ratings ranging from 2 Amps to 20 Amps. The predicted yield was validated experimentally and was found to be accurate within ±0.5%. The accuracy of both these models enables very efficient binning of epitaxial wafers to the correct device die size to ensure optimum yield at electrical wafer sort.

It is also important to gauge the impact of the non-killer defects on the electrical properties of various devices. Our analysis shows that some of these defects cause slightly increased leakage currents both in the forward conduction and reverse blocking conditions without causing the devices to fail. More extensive measurements and reliability testing is needed to understand some of the longer term impacts of the presence of these classes of defects in the SiC material.

Both the above yield models along with the validation against experimental data will be presented. A detailed description of the various classified defect types will be presented. Second order effects of the non-killer defect types on electrical tests will also be discussed.

[1] H. Das et al. ECS Transactions, 69 (11) 29-32 (2015)

[2] H. Das et al. ECS Transactions, 75 (12) 233-237 (2016)

[3] H. Wang et al. Materials Science Forum, Vols. 778-780, 332 (2014)

[4] G. Chung et al. Materials Science Forum Vols. 679-680, 123 (2011)

Unique and excellent properties of 4H-SiC have rendered a series of successful applications in various energy-related fields such as Electric Vehicle (EV) and Smart Grid. While efforts have been made over decades towards the improvement of crystal quality, the densities of crystalline defects existing in the as-grown crystals are still significant. One of the major issues is the residual stress left by the inhomogeneous distribution of crystal defects, which will lead to lattice bending and lattice strain once the bulk as-grown crystals are sliced into wafers. Therefore, the level of lattice strain and bending equivalently characterizes the level of overall homogeneity of the sliced wafer.

X-ray topography, particularly synchrotron monochromatic X-ray topography (SMBXT), enables a highly strain-sensitive technique for imaging the near surface regions of single crystals. When a strained crystal is illuminated by synchrotron monochromatic radiation, the crystal does not diffract entirely. In fact, only a limited region fulfills the Bragg's Law and diffracts. In order for other regions to diffract, the wafer has to be rocked through the perfect Bragg's condition with tiny increments. The variation in diffraction condition can thus be mapped as a function of position, which is caused by local lattice bending and strain. By recording the same map with the opposite diffraction vector, i.e. rotating the wafer about the original diffraction vector by 180 degree, the strain component can be separated with the bending component so that two individual maps of lattice strain and lattice bending, respectively, can be obtained.

In this paper, we use this method to estimate the local lattice strain and lattice bending as a function of position in a 75mm 4H-SiC commercial substrate wafer. Results are compared with X-ray topographic images recorded simultaneously from the same wafer.

Figure 1

Novel ion implantation processing has been introduced to enable p-type doping for high performance vertical GaN p-n power devices. Multicycle Rapid Thermal Annealing (MRTA) leads to state-of the-art p-type doping (> 8% dopant ionization); high n-type doping can also be achieved. The implantation process is also compatible with a tapered implanted junction terminal extension approach to achieve effective edge termination necessary to provide breakdown voltages over 90% of the theoretical maximum value at minimal cost and processing complexity.

MRTA, with ambient control (N₂ ambient at 200 psi), pulsed annealing up to ~1400 °C, and an appropriate dielectric encapsulant, is utilized to further improve activation efficiency and, ultimately, p-n junction performance through selective ion implantation and processing optimization. Here, the focus is on MRTA activation of Mg⁺ implantation, with comparison to the potential effectiveness of other p-type dopants, to assess the impact of the crystalline nature of the substrate and to optimize the encapsulant mask, in order to promote the highest dopant activation. This fundamental study of the role of defects in material produced by GaN epitaxial deposition is expected to lead to a pathway to high activation efficiency through a mechanistic understanding of the relationship between processing methods and performance. The critical link between defects and implant activation will be discussed through the use of novel structural materials characterization techniques as well as standard electrical and optical techniques. Electron microscopy defect analysis, determining the role of implanted and annealed defects, and providing localized strain measurements helps assess defect evolution as a function of implant and annealing parameters. X-ray based reciprocal space mapping as a function of the implant and subsequent annealing will be shown to correlate strain and defect formation with dopant activation in order to parameterize the MRTA process non-destructively. This information leads to the production of p-n junction devices that are scalable, provide high surge currents, and high ideality factors. Understanding point defect concentrations, dislocation types and concentrations, and residual stress will lead to effective p-type dopant activation and high device performance.

 Development of semiconductor devices and control of the manufacturing process require cost effective metrology with rapid feedback to pilot or manufacturing lines. In this respect, silicon IC's have been benefiting from inventions (by IBM, Fishkill, NY and by SDI, Tampa, FL) that created unique corona-Kelvin non-contact electrical metrology [1]. Corresponding commercial tools designed for Si wafers [2] reduced the need for fabrication of electrical test devices and electric contacts, reducing the manufacturing cost and shortening the data feedback time from weeks to less than one hour. Developments, reported in this work are directed toward new possibilities for corona-Kelvin application for wide-bandgap semiconductors, including SiC, GaN, and GaN/AlGaN heterostructures.

In charge-assisted corona-Kelvin metrology the low kinetic energy (thermalized) corona ions are placed on the surface. They produce an electrical field in dielectric and/or in semiconductor surface space charge region. The change of the surface voltage, DV, induced by charge dose DQ, is measured in a non-contact manner with a vibrating Kelvin probe. Non-contact differential capacitance is obtained as C=DQ/DV. Knowing the net surface voltage, V and the net charge density Q = SDQ the set of (C,V,Q) characteristics is determined. This unique corona-Kelvin data set enables determination of dielectric, interface, and semiconductor parameters [3].

Applications in silicon IC concentrated on characterization of wafers with dielectrics. Extension of the metrology to wide-bandgap semiconductors includes very important measurement of wafers with bare surfaces. Critical is charge-assisted profiling of dopant concentration and use of corona-kelvin CV as a non-contact alternative to mercury probe CV, MCV [4]. Large charging range and superior precision of corona charging for such measurement achieved only recently with the constant surface potential method [4].

In wide-bandgap semiconductors, the bare epi-surfaces in depletion were found to have excellent corona charge retention. In addition, the long- time constant of deep bulk traps and interface traps practically eliminates trap contribution to deep depletion capacitance. This increases the precision of dopant measurement and dopant-depth profiling.

Repeatability of measurements is very important for metrology acceptance in semiconductor manufacturing. In the charge-assisted measurement repeatability requires neutralization of the deposited charge. According to recent developments complete removal of corona deposited charge can be achieved using a photo-assisted process, namely, illumination with UV light with photon energy larger than the semiconductor energy gap. Photogenerated excess carriers neutralize corona ions and neutralized ions detach from the surface. This process enables to return to initial pre-charging condition as verified by the value of surface voltage.

The results of repeated dopant density measurement on epitaxial SiC and GaN demonstrated 1s in 10 repeats of 0.06% for doping in 10¹⁴ cm^-3 range and about 0.1% for dopant from 10¹⁸cm^-3 to 10¹⁹cm^-3. In the range from 10¹⁴cm^-3 to 2 x 10¹⁹cm^-3 very good correlation was obtained for SiC and GaN between corona-Kelvin noncontact CV and standard mercury probe MCV results. These results demonstrate present performance levels and confirms that corona-Kelvin represents an industry ready alternative to Hg-CV [5].

Recent results obtained on heteroepitaxial GaN/AlGaN/GaN with two dimensional electron gas, 2DEG, demonstrate the unique advantage of capacitance-charge characteristic C-Q available in corona-Kelvin method. This characteristic enables direct determination of the fully depleted 2DEG condition, and corresponding value of "charge to deplete" the 2DEG, and the pinch-off voltage value based on Q-V data. For GaN/AlGaN/GaN heterostructures these measurements confirmed the 2DEG location at the bottom AlGaN/GaN interface. The electron density depth profile of 2DEG determined from noncontact CV agreed very well with MCV results. The techniques gave the same pinch-off voltage values and the same total capacitance corresponding to AlGaN and GaN layers above the 2DEG.

Wafer level interfacial instability testing is the newest corona-Kelvin application for oxidized SiC and for GaN/AlGaN HEMT with dielectric capping. The fundamental advantage of charge-assisted technique is twofold: 1. larger dose corona charging provides a bias-stress inducing instability and 2. low dose corona charge-Kelvin measurement gives (C,V,Q) characteristics used for evaluation of instability magnitude. In HEMT heterostructures the instability is manifested by the shift in pinch-off point, that in accelerated photo-assisted testing is enhanced using illumination. In oxidized SiC the instability is manifested by CV shift corresponding to threshold voltage shift caused by charging of near-interfacial oxide traps.

The practical advantage of wafer level instability testing is rapid data feedback and elimination of test device fabrication cost, similar to corona-Kelvin advantages established in silicon IC development and manufacturing. An additional well proven advantage of the corona-Kelvin technique is whole wafer mapping capability for all measured parameters.

Figure 1

4H-SiC is one of the promising wide bandgap material that attracts considerable attention in power electronics industry. Several applications have benefited from the improved performances of devices made of 4H-SiC in terms of its higher breakdown fields, efficiency and reliability as well as excellent physical properties. However, the widespread commercialization of this material is still being hindered by the various defects introduced during the crystal growth which is found to degrade the device performance and lifetime. Stacking faults, for example, have been considered to be one of the most detrimental structural defects. It has been predicted theoretically that high nitrogen doping concentration level (above 2 x 10¹⁹cm-3) inside 4H-SiC crystal will increase propensity for formation of stacking faults. These can create quantum wells which can lower the free energy of the whole crystal once the barrier for partial dislocation motion is overcome by thermal energy (achieved by annealing above 1000^o C) [1-2]. Moreover, from a perspective of high power electronic applications, other severe issues, such as inhomogeneous resistivity and a large {0001} surface roughness of substrate are characteristic of heavily nitrogen doped SiC crystal [3]. It is known that, the nitrogen incorporation kinetic is anisotropic in different crystallographic directions during PVT growth of SiC. Therefore, better understanding the nitrogen doping distribution inside the material is important. In our experiments, we conducted X-ray topographic contour mapping [4] using synchrotron monochromatic X-ray beam by rocking the heavily doped wafer surface successively with a fixed angular step size around the near-surface diffraction vectors 0008 and -0008 respectively. From these measurements, a strain map can be derived by deconvoluting the lattice parameter variations from the lattice tilt. The nitrogen doping concentration can be calculated from the isotropic lattice strain due to the incorporation of dopants according to the equation from H. Jacobson [5].

[1] Y. Yang, J. Guo, Ouloide Goue, B. Raghothamachar, M. Dudley, G. Chung, E. Sanchez, J. Quast, I. Manning, and D. Hansen, J. Crystal Growth, 452, 32 (2016).

[2] T.A. Kuhr, J. Liu, H. J. Chung et al., Journal of Applied Physics,92, 5863 (2002).

[3] N. Ohtani, M. Katsuno, M. Nakabayashi, T. Fujimoto et al., J. Crystal Growth, 311, 1475 (2009).

[4] S. R. Stock, Haydn Chen and H. K. Birnbaum, Philosophical Magzine A, 53(1), 73(1986).

[5] H. Jacobson, J. Birch, C. Hallin, A. Henry, R. Yakimova, T. Tuomi, E. Janzén, and U. Lindefelt, Applied Physics Letters 82 (21), 3689 (2003).

Figure 1