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CMOS optical sensors devices are becoming increasingly important and popular for many different applications. Some of these devices are fabricated starting from SOI (Silicon On Insulator) wafers and using semiconductor manufacturing techniques. A common feature of the CMOS sensors is the isolating trench that protects the device from electrical noise. We report on the multistep etch process development to fabricate trenches deeper than usual, in order to isolate the sensor also from stray light interference. We focus the attention on unexpected features that originated during the Buried Oxide (BOX) etch.

A HfO₂/Al₂O₃ bilayer structure for a two-terminal ReRAM device with an intention of having multiple resistance states as a function of compliance current (CC) after forming was evaluated. A reduced power consumption was observed when the Al₂O₃ buffer layer was placed between the top electrode and the HfO₂ layer as compared to when it is embedded between the HfO₂ layer and the bottom electrode. Gradual resistance change capability was observed with varying CC. The switching power requirement increases even if the Al₂O₃ buffer layer thickness was decreased when the buffer layer was near the bottom electrode. It was demonstrated that by modifying the deposition process of the top metal layer the switching energy requirement can be altered.

We investigated the influence of O₂ concentration in ultra pure water (UPW) on the Si(110) surface roughness during the immersion of Si into UPW. The suppressing of O₂ concentration in UPW is very effective to suppress the increase of microroughness of Si(110) surface. The O₂ concentration in UPW can be controlled by the ambient O₂ concentration. Si(110) surface cannot be roughened when the O₂ concentration is suppressed to less than 100 ppm in ambient (4 ppb in UPW) and the immersion time is less than 1 hour. It can be expected that the Si(110) surface flatness is maintained, and this surface is mainly used for the channel of FinFET. Furthermore, we demonstrated that the O₂ concentration in a prototype 200-mm single-wafer cleaning chamber can be decreased to less than 100 ppm within 1 minute by an N₂ purge of 200 l/min.

An interferometric optical isolator with a Si guiding layer employing a nonreciprocal phase shift was proposed. The optical isolator can be operated in a unidirectional external magnetic field owing to the optical interferometer with distinct layer structures. A nonreciprocal phase shifter and a multimode interference coupler were designed at a wavelength of 1.55 μm. Branching characteristics of the multimode interference coupler were measured.

The switching dynamics of ferroelectric Y-doped HfO₂ films are evaluated and the thickness or the remnant polarization dependence is shown. Based on data fitting to Kolmogorov-Avrami-Ishibashi (KAI) model, the films have shown a small n-value, a parameter representing the dimension of the domain switching, of 1. This value is in contrast to the commonly observed values of over 2 for Hf_0.5Zr_0.5O₂ films.

Nitride-based materials including Al_xSc_1-xN (ASN) films have also been proven to show a ferroelectricity with a box-like characteristic recently. In this paper, ASN thin films were deposited by RF sputtering with different metal electrode materials, Al, W, TiN and Ni. Leakage current measurements hardly showed difference among the electrode materials. A Schottky barrier height (SBH) at metal/ASN interface was as small as 0.86 eV, irrespective to the electrode material, suggesting a strong Fermi level pinning (FLP). Capacitance-voltage (CV) measurements revealed ferroelectric-like hysteresis behavior for all the electrode materials.

The electromigration failure phenomena of the plasma etched copper line with a copper oxide capping layer has been studied. The copper oxide prepared by the oxygen plasma oxidation method covers the entire copper stack. The failure of this kind of structure was determined from the resistance change with the stress time. The line temperature was calculated accordingly assuming the adiabatic condition, i.e., the dissipation of Joule heat to the glass substrate and environment was negligible. The surface color of the line changes with the stress time. The composition and color of the copper oxide passivation layer were characterized and correlated to the Joule heating. The color change can be an effective reference to predict the line failure location and time. In summary, the copper oxide passivation layer can be easily formed into the self-aligned structure and the line failure process can be detected from the color change.

The IEEE International Roadmap for Devices and Systems (IRDS) for More Moore devices summarises the Logic Device state of play very effectively; the FinFET is the key device architecture that could enable logic device scaling until 2025. Increasing fin height while reducing number of fins at unit footprint area is an effective solution to improve performance. It is forecasted that the parasitics will remain as a dominant term in the performance of critical paths. For reduced supply voltage, a transition to gate-all-around (GAA) structures such as lateral nanowires or nanosheets will be necessary to improve electrostatics. Lateral GAA structure would eventually evolve in to the vertical GAA structure to gain back the performance loss due to increasing parasitics at tighter pitches. In this paper we will consider doping techniques based on ion implant, solid-source in-diffusion, liquid-source in-diffusion, and gas-source in-diffusion for these device technologies.

Accurate characterization of dopant activation at the near-surface region is essential to understanding and developing doping schemes to achieve low contact resistance for Ge NMOS. Differential Hall Effect Metrology (DHEM) was employed to study dopant activation with sub-nm resolution on n-type Ge layers epitaxially grown on Si substrates. Two different capping layers, Al₂O₃ and SiO₂, were deposited on Ge and the samples were implanted with Sb and P, then subsequently annealed. Carrier concentration depth profiles as measured by DHEM showed one order of magnitude higher dopant activation at the surface for the SiO₂ capped samples. SIMS measurements indicated Al in-diffusion for the Al₂O₃ capped films, suggesting a highly defective Ge surface. This indicates that annealing is insufficient to repair damage caused by ion implantation, necessitating alternative approaches to achieve high dopant activation in n-type Ge.

We demonstrate a MIM capacitor structure using ZrO₂ for the dielectric layer. This exhibits a 25% capacitance increase with minimal leakage current increase compared to Hf based dielectrics, extending the usefulness of MIM on-chip decoupling capacitors. The MIM structure, suitable for BEOL processing is TiN/ZrO₂/TiN combined with an anneal which is shown to improve the capacitance vs. leakage performance compared to doped and undoped HfO₂ based control structures. GI-XRD measurements demonstrate that the capacitance increase corresponds with a phase transformation from amorphous to cubic phase, which is shown to have a dielectric constant (k) up to 35. Reliability models based on hard-breakdown (HBD) show that this structure exceeds the end-of-life targets.

The impact of Plasma Immersion Ion Implantation (PIII) processes with various species (hydrogen, helium and nitrogen) on the stress of a tensile PECVD nitride film was evaluated. Ellipsometry measurements indicated no consumption of the nitride but a change in the optical index, signaling a material modification. The initial stress of the nitride was modified by PIII from tensile to mechanically neutral and even compressive. Hydrogen and nitrogen appeared to be more efficient to modify the stress than helium.