Table of contents

In this paper, substantial recent progress on graphene synthesis on standard substrates and the high-performance electronic properties arising from the synthesized monolayer will be highlighted. Nearly defect-free monolayer graphene can now be synthesized by CVD at wafer-scales with material quality comparable to ex-foliated natural flakes. Fabricated transistor devices from CVD graphene on oxidized silicon now readily afford mobilities over 10,000 cm²/V-s with 10x on/off current ratio while maintaining the intrinsic electron-hole symmetry. Linear and non-linear circuits such as amplifiers and low-loss doublers have also been achieved.

One of the main challenges in the fabrication of device quality graphene is the achievement of large area monolayer graphene that is processing compatible. Here, the impact of the substrate properties on the thickness uniformity and electronic characteristics for epitaxial graphene on SiC produced by high temperature sublimation has been evidenced and discussed. Several powerful techniques have been used to collect data, among them large scale ellipsometry mapping has been demonstrated for the first time. The study is covering all three SiC polytype, e.g. 4H-, 6H- and 3C-SiC in order to reveal eventual peculiarities that have to be controlled during graphene growth. The advantage of the cubic polytype is unambiguously demonstrated.

Chemical vapor deposition on copper is the most widely used method to synthesize graphene at large scale. However, the clear understanding of the fundamental mechanisms that govern this synthesis is lacking. Using a vertical-flow, cold-wall reactor with short gas residence time we observe the early growths to study the kinetics of chemical vapor deposition of graphene on copper foils and demonstrate uniform synthesis at wafer scale. Our results indicate that the growth is limited by the catalytic dissociative dehydrogenation on the surface and copper sublimation hinders the graphene growth. We report an activation energy of 3.1 eV for ethylene-based graphene synthesis.

We present incremental advances in carbon nanotube synthesis and in graphene applications. These advances include novel lateral growth of carbon nanotubes with fair alignment, demonstrations of limited control of carbon nanotube chirality distribution, a study of the reliability and robustness of graphene, and a characterization of atomic layer deposition onto carbon nanotubes.

We theoretically and experimentally studied the thermal transport properties in various graphene-based systems. Firstly, we review our previous works of molecular dynamics simulations to study the thermal transport in graphene nanoribbons (GNRs). We also studied negative differential thermal conductance (NDTC) at large temperature biases in GNRs. We extended our study of NDTC in the diffusive limit into general one-dimensional thermal transport and found that NDTC is possible if thermal junctions are introduced. These findings are useful for future applications of controlling heat at nanoscale. Secondly, we describe our experimental work of synthesized graphene-based composites with fillers of reduced graphene oxide and polymers. We used 3ω method to measure the thermal conductivity and found that the thermal conductivity can be tuned dramatically by the graphene filler concentration. Graphene-based composites are potentially promising as thermal interface materials, which have become increasingly important in modern heat management in many industrial applications.

The structural and electronic properties of silicene and germanene on metallic and non-metallic substrates are investigated theoretically, using first-principles simulations. We first study the interaction of silicene with Ag(111) surfaces, focusing on the (4x4) silicene/Ag structure. Due to symmetry breaking in the silicene layer (nonequivalent number of top and bottom Si atoms), silicene is predicted to be semiconducting, with a computed energy gap of about 0.3 eV. However, the charge transfer occurring at the silicene/Ag(111) interface leads to an overall metallic system. We next investigate the interaction of silicene and germanene with hexagonal non-metallic substrates, namely ZnS and ZnSe. On reconstructed (semiconducting) (0001)ZnS or ZnSe surfaces, silicene and germanene are found to be semiconducting. Remarkably, the nature (indirect or direct) and magnitude of their energy band gap can be controlled by an out-of-plane electric field.

Graphene-insulator-graphene tunnel junctions have been fabricated and characterized. The cleaning processes for chemical vapor deposited graphene and integration of barrier engineered atomic layer deposited tunnel dielectrics is presented. Initial results of device characterization demonstrate subthreshold slopes less than 100 mV/dec.

We discuss recent experimental observations of metal/graphene contacts in terms of intrinsic interfaces obtained with resist-free process by comparing with those made by the conventional lithographic fabrication steps.

We will present recent progress in graphene material, graphene FETs, heterostructures, graphene NEMS, and potentially disruptive RF applications of graphene FETs such as linear efficient mixers and high dynamic range radiometers. Development of emerging graphene and graphene heterostructure would potentially improve RF systems with or without integration with standard Si/III-V RFICs.

This work presents a detailed study of the graphene RF mixer in the ambipolar configuration, using quasi-free-standing epitaxial graphene on SiC. Record high conversion gain is achieved through use of optimized growth and synthesis techniques, metal contact formation, and dielectric materials integration. Hydrogen intercalation is utilized to isolate the graphene from the underlying SiC substrate and improve transport properties. Low contact resistances at the metal-graphene interface are realized using an oxygen plasma pre-treatment, while dielectric seeding is achieved using a direct deposited layer of HfO₂ before ALD film growth. Output characteristics of the graphene transistor are analyzed and the effects on mixer performance are explained. A graphene RF transistor is designed with gate length 750 nm, width 20 μm, and equivalent oxide thickness ~2.5 nm in order to achieve record high conversion gain of -14 and -16 dB at LO power 0 dBm at 4.2 and 10 GHz, respectively, 100x higher than previously reported ambipolar mixing.

The unique physicochemical properties of graphene enable the various electronic applications, even it is a zero band gap semiconductor. To overcome the low on/off ratio of graphene device originated from zero band gap property, several types of graphene have been studied such as nanoribbon and bi-layered graphene. Here, we reported the new structural graphene transistor, tunable Schottky diode, with high on/off ratio. Since it does not accompanied with any structural deformation of graphene, intrinsic properties were also preserved. Schottky barrier was simply formed by transferring the CVD grown graphenes on hydrogenated silicon surfaces. By adjusting graphene's work function, we got a threshold voltage shift with high on/off ratio, 10⁵.

We first describe self-organizing graphene ribbon formation by chemical vapor deposition. Graphene ribbons can be formed only on narrow twin crystal regions with a (001) or high-index surface sandwiched between Cu crystals having (111) surfaces. At a relatively low CH₄ pressure in Ar/H₂, graphene is preferentially nucleated and formed on twin crystals. The preferential nucleation is probably caused by a difference in surface-dependent adsorption energies of reactants. In the second part, we describe newly developed dual-gated graphene transistors. We found that a transistor with a graphene channel irradiated with He ions can have a transport gap up to 380 meV. We then made dual-gated transistors using such a channel and obtained an on-off ratio of 10³ at 200 K. The device has a channel region between the dual gates, and the polarity of the transistor can be electrostatically reversed by flipping the bias polarity of one of the dual gates.

In this work we report a technique to improve the Ion/Ioff ratio in bilayer graphene FET by asymetrical doping of layers. Doping is achived by n-doping the bottom layer by depositing bilayer graphene flakes on NH₂-SAM modified SiO₂ substrate and hole doping the top layer via coating the device with a film of F₄TCNQ-containing polystyrene. Asymmetric surface doping of bilayer graphene can induce an electric field between both layers which results in opening of an electronic bandgap due to symmetry breaking. DFT modelling shows an effective electric field of ~1.5 V/nm between the layers and field effect measurements show an increase of Ion/Ioff ratio in bilayer FET up to 135 due to opening of the bandgap also, a Schottky barrier of ~60 meV at the interface of the semiconducting bilayer graphene and the electric contact is observed.

In this paper we report on the application of in-situ CCVD grown bilayer graphene transistors (BiLGFETs) suitable as memory devices. By means of catalytic chemical vapor deposition (CCVD) the BiLGFETs are realized directly on oxidized silicon substrate without transfer. These BiLGFETs possess unipolar p-type device characteristics with a high on/off-current ratio between 1x10⁵ and 1x10⁷ at room temperature. The hysteresis of BiLGFETs depends on the cycling range of the applied backgate voltage V_BG while the sub-threshold slope is uniform for varied temperatures and varied cycling ranges of the backgate voltage. Based on the observed properties of BiLGFETs it is possible to use BiLGFETS as memory devices.

Carbon NanoTube (CNT) channel promises near ballistic transport and is examined extensively for potential application in next-generation Nano-scale transistor. Cylindrical gate-all-around CNT field effect transistor (CNTFET) with semiconducting CNT S/D contacts and Schottky barrier CNTFET (SBCNTFET) are modeled numerically based on self-consistent solution of Poisson-Schrödinger equation with open boundary conditions within Non-Equilibrium Green's Function formalism considering coaxial symmetry. The effect of dielectric constant (κ) and physical thickness of gate dielectric on transport characteristics of CNTFET and SBCNTFET are examined in this work. Gate capacitance, carrier injection velocity, current and therefore speed increases significantly with the inclusion of high κ dielectric and decrease in thickness. SBCNTFET also shows better performance with thin high κ dielectric layer. High trans-conductance and much lower Sub-threshold swing is visible with the inclusion of high κ gate stack.

High quality bulk GaSb and InGaSb quantum wells grown on GaAs substrates were MBE grown using a AlGaSb(As) metamorphic buffer layers to reduce dislocation density down to 107cm-2. Strained In0.36Ga0.64Sb quantum wells with a biaxial compressive strain of 1.8% showed the highest mobility of 1020 cm2/Vs and a low sheet resistance of 3.9 kΩ/sq. at hole sheet at hole density of 1.9x1012 cm-2. Buried channel design with an AlGaSb top barrier improved hole mobility by only 30% compared to surface QW channels. Improving the interface trap density down to 1012 cm-2eV-1 was realized using an amorphous Si layer (in-situ gate oxide) or an InAs layer (ex-situ gate) as a gate passivation. p++-GaSb epitaxial contact layers were developed and showed the leakage current of ~0.1 mA/cm2 not affected by growth defects. Critical elements of "gate-last" InGaSb MOSFET fabrication process were developed utilizing an InAs etch stop layer to avoid high temperature processing of the gate stack.

The capacitance-voltage (C-V) response of III-V MOS devices has been a subject of increased research and debate over the past decade. Attempts to correlate chemical states to the observed electrical response in addition to simulation and modeling have led to great advances in the understanding of these systems. Here, we present our observations on the electrical and physical characteristics of III-V based devices. The C-V response is fundamentally different than that of Si-based devices owing to the tunneling of charge carriers into distributed trap states. Our investigations suggest that these trap states are caused by a disordered chemical region associated with the III-V semiconductor (Disorder Induced Gap States, DIGS) and not due to defects in the high-k dielectric (border traps).

This work demonstrates a self-consistent 2-D numerical model for calculating the charge profile and gate capacitance and therefore obtaining C-V characteristics of a gate-all-around III-V nanowire transistor with a high mobility In_0.53Ga_0.47As channel and atomic layer deposited Al₂O₃/20nm WN gate stacks which has recently been demonstrated experimentally. Finite element method is used to solve Poisson's equation and Schrödinger's equation in a coupled manner taking wave function penetration, energy level splitting and other quantum effects into account while calculating the charge profile and gate capacitance for different gate bias. The functional dependence of C-V characteristics on different physical/process parameters i.e. alloy composition, oxide thickness, fin-width, doping density are explored as well.

In this paper, we present the effects of Ozone post deposition treatment on Al₂O₃/GaSb MOS capacitors. It is found that after deposition of Al₂O₃ dielectrics by atomic layer deposition (ALD), in-situ Ozone post deposition treatment for five minutes can improve the interfacial and electrical properties of the Al₂O₃/GaSb MOS capacitors, reducing the interface state density (Dit) and gate leakage current. Dit near the mid-gap is reduced by ~10% after in-situ Ozone post deposition treatment. Explanations for the improved characteristics by in-situ Ozone post deposition treatment are proposed. It is believed that the effects of in-situ Ozone post deposition treatment is due to the reduction of oxygen vacancies and defects at the interface and in the dielectrics.

Self-assembled Ge quantum dots were formed by in-situ thermal annealing of a thin amorphous Ge layer deposited by molecular beam epitaxy either on a thin porous TiO₂ layer grown on SiO₂ on Si(001) or directly on the SiO₂ layer itself. For samples with dot diameters ranging from 10 to 35 nm, the dot photoluminescence (PL) appeared primarily as a wide near-infrared band peaked near 800 meV. The peak energy of the PL band reflects the average dot size and its shape depends on the dot size distribution. Using tight binding and effective mass theoretical models, we have analyzed the PL spectrum in terms of the dot size distribution. The observed size distribution determined from transmission electron and atomic force microscopy allowed the determination of the nonlinear increase in the PL efficiency with decreasing dot diameter. Although the absolute intensities of the PL from the samples vary, the calculated efficiency curves are all well fitted by straight lines on a log-log plot, with essentially the same slope for all samples, thereby demonstrating that under the weak confinement regime investigated here there is a universal power-law increase in PL efficiency with decreasing dot size. Knowing this generic PL efficiency, we show that it is possible to evaluate the size distribution of Ge dots from their PL energy dependence.

A strained SiGe layer will be used in next-generation transistors to improve device performance along with device scaling. However, the stress relaxation of SiGe layer may be inevitable in nanodevices, because the SiGe layer is processed into nanostructure. In this study, we evaluated the stress relaxation profiles in mesa-shaped strained SiGe layers on Si substrate by electron back scattering pattern (EBSP), super-resolution Raman spectroscopy (SRRS) measurements, and finite element method (FEM) simulation. As a result, the stress relaxation profiles with high spatial resolution were obtained by each measurement. The range of σxx stress relaxation is mostly 100 nm from edge. The drastically σxx stress relaxation was over than approximately 25 percent in that range. Thus, the stress relaxation is inevitable in nanostructure with less than 200 nm scale. Moreover, there is a good correlation between the results of EBSP, SRRS measurements, and FEM simulation. The spatial resolution of EBSP and SRRS measurements were estimated less than 100 nm. Thus, super-resolution algorithm improved the spatial resolution of Raman spectroscopy from approximately 400 nm to sub-100 nm. It is prospective to evaluate the precise stress relaxation profile the sub-100 nm order structures by EBSP and SRRS measurements, respectively. Moreover, the complement of FEM simulation is important to verify the results of EBSP and SRRS. We believe that EBSP, SRRS measurements, and FEM simulation will be indispensable to for evaluating stress in future MOSFETs with high spatial resolution, which will surely surpass the present ones in complexity.

In crystalline, dislocation-free, Si/Ge nanowire (NW) axial heterojunctions grown using the vapor-liquid-solid (VLS) technique, transmission electron microscopy (TEM) photoluminescence (PL) and Raman spectroscopy reveal a SiGe alloy transition layer with preferential chemical composition and strain. In addition to the lattice mismatch, strain due to the difference in Si and Ge thermal expansion is observed. We find, in agreement with theoretical predictions, that the strain can be partially relived by lateral nanowire expansion in the vicinity of the Si/Ge heterojunction. In addition to the observed nanowire lateral expansion, the lattice mismatched induced strain could be relaxed by other mechanisms including intermixing, formation of structural defects and partial amorphization. The conclusions are supported by analytical TEM measurements.

This work studies the effectiveness of stressors for Si- and Ge-channel gate-last FinFETs in nested layouts with dimensions of the 14, 10 and 7 nm-nodes. P-type FinFETs with Si-channels can be efficiently boosted by SiGe source/drain (S/D) stressors, and provide higher mobility than relaxed Ge-channel pFinFETs. The highest pFET mobility is found for strained Ge-channels: in this case a SiGe Strain-Relaxed Buffer (SRB) with Ge < 90% leads to a channel mobility that is significantly higher than what is achievable with strained Si. For nFETs, a SiGe-SRB is the most efficient booster for Si-channels. Theoretically, the electron mobility of Ge fin sidewalls is very high, making Ge-channel nFinFETs a promising alternative, even without strain. SRBs are the most efficient stressors and are scalable beyond the 14 nm-node. Etching the fins in the S/D regions releases strain generated by the SRB, therefore raised S/D stressors are preferred over recessed for maximal mobility when combined with SRBs. Except for SRBs and S/D stressors, the other stressors studied in this work (contact etch-stop layers, stressed gates and contacts) are found to be inefficient in nested 14 nm-node layouts.

In this paper our recent research on Ge nanoparticles embedded in ZrO₂ will be reviewed. Ge nanoparticles have been deposited by rf-cosputtering of Ge_1.6ZrO₂/ZrO₂ superlattices and subse-quent annealing. TEM measurements confirmed the phase separation of the two compounds and the forming of ex-tended nanocrystalline Ge layers at 650°. These layers show a luminescence signal at 2.5 eV, which is contributed to defect luminescence.

An approach of creating CMOS channel with GeSn is one of the post-scaling techniques and is widely considered to be promising to improve LSI performance. In this paper, we selected the metal-organic (MO) precursors to deposit GeSn and investigated their characteristics. We confirmed that it is possible to deposit GeSn on a substrate using the MOCVD technique.

Deep levels associated with extended and point defects in MOS capacitors fabricated on unintentionally doped GeSn epitaxial layers on Ge-on-Si substrates have been studied by Deep Level Transient Spectroscopy (DLTS). A 9nm layer of Al₂O₃ is deposited as high-k gate dielectric by Molecular Beam Epitaxy. The trap kinetics and origin of defect states is discussed. Also, it is shown that the dislocation cores in relaxed p-Ge are associated with band-like donor-like states in the lower half of forbidden band gap, and act as carrier trapping and recombination centers. In addition, slow and fast oxide interface traps are observed.

Bandgap engineering in semimetal nanowires can be utilized to form a field effect transistor (FET) near atomic dimensions and eliminates the need for doping in the transistor's source, channel, or drain. For sufficiently small wire diameters the metallic behaviour of the semimetal is lost and a bandgap is induced. Using a full quantum mechanical description of the semi metal nanowires, we are able to demonstrate that the design of adopant-free, mono material confinement modulated gap transistors (CMGT) which unlike conventional FETs does not require dopant atoms to define different device regions. This overcomes a primary obstacle to fabricating sub-5 nm transistors, enabling aggressive scaling to near atomic limits.

In this work, we report preliminary results from a 32×32 pixel prototype array that integrates a-Si:H TFT pixels with optically sensitive lateral a-Se MSM detectors. The array was in-house fabricated and characterized. Recent advances in improving the wavelength sensitivity, dark current, photocurrent and quantum efficiency of the a-Se optically sensitive lateral device are also presented together with system-level characterization and the first image captured by the array.

Hafnium dioxide (HfO₂) and aluminum oxide (Al₂O₃) films have been deposited using atomic layer deposition (ALD) method and have been evaluated and used as metal-insulator-metal (MIM) capacitor dielectric in GaAs hetero-junction bipolar transistor (HBT) technology. The results show that the capacitor with 62 nm of ALD HfO₂ resulted in a capacitance density of 2.73 fF/mm², while that with 59 nm of ALD Al₂O₃ resulted in a capacitance density of 1.55 fF/mm². This capacitance density increased, when the temperature was increased from 25 to 150^oC. There was no significant change in capacitance density of these ALD films, when the applied voltage was varied from -5 to +5 V and when the frequency was increased from 1 kHz to 1 MHz. The breakdown voltage of the ALD hafnium dioxide and aluminum oxide films was measured to be at 34 V and 41 V, respectively. As the temperature was increased from 25 to 150^oC, the breakdown voltage of both films decreased, while the leakage current increased. These results show that both ALD HfO₂ and Al₂O₃ are compatible with, and suitable as MIM capacitor dielectric in GaAs HBT technology and can be adjusted to meet the specific application and requirements of the GaAs devices and designs.

In this study, using the finite element method analyzes stress and strain of device structure on different patterns epitaxial lift-off process. Design copper substrate bears stress 28.3 MPa and to simulate the change of the sacrificial layer in the epitaxial lift-off process, which setting the sacrificial layer etching amount for 10%, 30%, 50%, 70%, 90%. Besides, the stress and strain distribution of device structure analyzes on various sacrificial layer etching amount. Copper substrate is subject to tensile stress and its corner exist the maximum of stress and strain. Moreover, the stress distribution of epilayer concentrates in the upper and lower interface of sacrificial layer. The stress is larger sacrificial layer etching to 10% than etching to 90%. The structures 3 stress is relatively lower, which the stress reduces approximately half on etching amount 50%. Therefore, the GaAs epilayer not only reduce subjected to stress but also decrease the occurrence of defects.

A new class of semi-conducting boron carbide polymers has been formed from cross-linking of ortho-carborane (o-B₁₀C₂H₁₂) or o-B₁₀C₂H₁₂ in the presence of aromatic compounds (Y =1,4-diaminobenzene, pyridine, and benzene) to form B₁₀C₂H_X and B₁₀C₂H_X:Y, respectively. Core and valence band photoemission and molecular orbital calculations indicate that cross-linking of o-B₁₀C₂H₁₂ results in site-specific bonding between boron sites opposite carbon sites on the carborane icosahedra. This site specificity is retained when cross-linking o-B₁₀C₂H₁₂ in the presence of aromatic linking units; the linking units insert themselves between carborane icosahedra. This insertion results in bonding between boron sites opposite carbon sites in the carborane icosahedra to carbon sites on the aromatic moieties. B₁₀C₂H_X:Y films exhibit shifts in the valence band maximum from -4.3 eV (i.e. 4.3 eV below the Fermi level) for B₁₀C₂H_x, to -2.6 eV, -2.2 eV and -1.7 eV for Y = benzene, pyridine, or 1,4-diaminobenzene, respectively. States near the top of valence band correspond to states localized on the linking unit. Films formed by plasma-enhanced chemical vapor deposition of o-B₁₀C₂H₁₂ are p-doped, and such films show excellent rectifying characteristics when deposited on n-type Si--extremely promising for neutron detection and other device applications.

In this paper, the author points out that the Poole-Frenkel (P-F) and Schottky emission mechanisms actually can happen simultaneously and a unified Schottky-Poole-Frenkel model can be used to explain a lot of existing experimental data. However, sometimes, the basic unified Schottky-Poole-Frenkel model fails and an extended unified Schottky-Poole-Frenkel model is required to explain experimental data. In this paper, an example of using the basic unified Schottky-Poole-Frenkel model to explain the I-V characteristics of high-k capacitor structures used in analog integrated circuit technology will be presented. Then an example of high-k capacitor structures used in analog integrated circuit technology which require the extended unified Schottky-Poole-Frenkel model will also be provided.

We have researched low temperature silicon oxide (SiO₂) with improved electrical properties and excellent film step-coverage. In-situ O₂ plasma densification (DENSIFICATION) effect on SiO₂ that has been deposited by PE-ALD at temperature (<400°C) was investigated. The wet etch rate was controllable as a function of DENSIFICAION time due to repairing of the SiO₂ network defects by the oxygen radicals. Angle Resolved X-ray Photoelectron Spectroscopy (AR-XPS) analysis was carried out to observe the core-level binding energies shifts (chemical shifts) in the different SiO₂ films. The characteristics of wet etch rate of high quality low temperature SiO₂ demonstrated lower than high temperature LP-CVD SiO₂ values. Compared to LP-CVD SiO₂, PE-ALD SiO₂ with DENSIFICATION showed excellent I-V characteristics with lower leakage current and similar to the thermal SiO₂ carrier transport plot.

Redistribution of interface trap capacitance (Cit) and deep depletion (D.D.) behavior was observed in non-planar substrate MOS capacitors with ultra thin oxides grown by anodic oxidation (ANO). We find the D.D. electrical characteristics between the non-planar and planar samples are different. The minority carrier crowding induced low frequency effect and corner E-field crowding induced D.D. was observed in non-planar substrate MOS capacitors. Moreover, the deep depletion behavior of non-planar sample after constant voltage stress (CVS) was also explored. The non-planar devices exhibit significant two peaks distribution in Cit after CVS due to multiple surfaces effect. It was found that the multiple surfaces effect induces additional interface trap of acceptor-like. However, the interface trap characteristic of planar sample is mainly donor-like.

Electrical and physical properties of ErSi_x on n-type Si(100) (111) and (551) surfaces are reported. The ErSi_x density affects the work function of ErSi_x. A controlling the composition ratio of Er and Si is a key parameter for a reducing contact resistance for high performance MISFETs. These silicidation reactions are very important to develop the high current drivability devices using any surface orientation.

The effect of absorbed moisture on the electrical and reliability characteristics of the low-k dielectrics was investigated in this study. The experimental results indicate that the porous low-k dielectrics would absorb more moisture as compared to the dense low-k dielectrics. This absorbed moisture degrades the electrical and reliability performance of the low-k dielectrics. A higher temperature anneals at 400^oC is needed to decompose physically-adsorbed water, which is benefit to restore reliability performance. On the other hand, the chemically-adsorbed moisture seems to be difficult to be removed by a 400^oC annealing, causing a degraded TDDB performance.

In this paper, the author points out that Poole-Frenkel (P-F) saturation can be experimentally observed in ultrathin tantalum oxide capacitors. Factors why P-F saturation has been difficult to observe experimentally will be discussed. P-F saturation has not been successfully observed in thick tantalum oxide capacitors. Using an annealing process at a temperature just below the crystallization temperature seems to be helpful. In addition, TiN gate seems to be much better compared to Al gate. N₂O is superior to O₂ as the annealing ambient.