Table of contents

It is believed that to continue the scaling of silicon CMOS innovative device structures and new materials have to be created in order to continue the historic progress in information processing and transmission. Recently germanium has emerged as a viable candidate to augment Si for CMOS and optoelectronic applications. In this work we will first review recent results on growth of thin and thick films of Ge on Si, technology for appropriate cleaning of Ge, surface passivation using high-κ dielectrics, and metal induced crystallization of amorphous Ge and dopant activation. Next we will review application of Ge for high performance MOSFETs. Innovative Si/Ge MOS heterostructures will be described with high on current and low off currents. Finally we will describe optical detectors and modulators for on-chip and off-chip interconnect. Successful integration of Ge on Si should allow continued scaling of silicon CMOS to below 22 nm node.

Fifty years of Si and SiGe epitaxy in the semiconductor industry and twenty-five since the conception of the present generation of industrial epi reactors suffice to justify a review of the evolution and the status of the technology. Although there has been very little change in the reactor design, the epi process progressed significantly. The strengths and weaknesses of the current technology are discussed with an emphasis on possible improvements.

In this contribution, we are focusing on low temperature Si and SiGe epitaxy for the fabrication of thin-films transistors devices. In particular, we will consider two different approaches: the first one is the use of FDSOI substrates in combination with a poly-selective Si epitaxy. The second one is the use of conventional wafers for the fabrication of SON devices where SiGe can be employed as a sacrificial layer to form very-thin buried ONO below the transistor channel. Some electrical results on FDSOI, folded Bulk+, and localized SOI with TiN/HK gate stack are presented showing a perfect control of the SCE and DIBL with a very low Ioff which is mandatory for advanced CMOS low power applications

We explore several technology options for forming lattice-mismatched source/drain (S/D) stressors for enhancing the performance of complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Recent research on silicon-carbon [Si:C or Si(1-y)C(y)] S/D stressors for n-FETs will be reviewed. Device integration work involving epitaxial Si:C S/D with high carbon concentration and in situ doping, as well as alternative technologies for forming Si:C S/D, e.g. using implantation and anneal, will be discussed. For p-FETs, tin-incorporated S/D stressors will be explored. Integration of new stressors in advanced device architectures is expected to enable the realization of ultimate CMOS performance.

We have thoroughly investigated Double Gate (DG) n-MOSFETs with III-V materials (GaAs (111), InP (111), InAs (111) and InSb (111)) and compared to Si (100) and Ge (111). The simulations performed under ballistic transport take into account non-parabolic full band structure, quantum confinement effects, BTBT leakage and SCE effects. Our results show that with oxide thickness of 0.7 nm, despite of small density of states (DOS) of these materials, III-V and Ge outperform Si in terms of drive current and gate delay. However, the high mobility, small bandgap materials like InAs, InSb and Ge, suffer from excessive BTBT current and poor SCE, which limits their scalability. Effect of parasitic gate capacitance in DGFET on device performance is given as well.

Suspended strained-Si nano-wires (NWs) were fabricated from a highly biaxially strained-Si substrate (with an initial stress of 2.16 GPa). Using e-beam lithography, ~25nm thick NWs with the widths in the range of 20 to 80 nm were fabricated and the stress was investigated by UV micro-Raman spectroscopy. Suspended NWs are strained to an average uniaxial tensile stress level of ~2.1 GPa which is almost independent of NW width, in the range studied in this work. Ultra-dense (25 NWs per micron) sub-20 nm suspended strained-Si NWs were fabricated using resolution-enhanced lithography to improve the Raman signal-to-noise ratio. A tensile in-plane stress level of 1.7GPa was measured for 18 nm-wide NWs at 40 nm pitch. Gate-all-around n-MOSFETs were fabricated based on these strained-Si NWs. Electrical measurements on these MOSFETs demonstrate near ideal subthreshold behavior, very high on-to-off ratio and current drive and transconductance enhancement of ~2X over unstrained NWs.

The stress sensitivity of SSOI substrate offers a unique material platform for strain manipulation. Base on patterning and device processing, new opportunities to engineer the metastable stress for planar and other novel device structures are possible. In this presentation, the strain stability of SSOI devices are discussed and how mixing of uniaxial and biaxial strain can be achieved to improve devices for CMOS operation.

Thin SGOI substrates with Ge content from 42 to 93% have been produced by the Ge condensation technique and full structural characterization has been carried out. In a second step, the electrical properties of these substrates have been analyzed by the pseudo-MOSFETs technique which allowed the determination of the carrier low field mobilities as well as the density of fixed charges in the buried oxide (BOX) and the density of interface traps at the BOX-SiGe film interface. Optimization of intermediate anneals in argon during the condensation process has made the production of high crystalline quality and high mobility substrates possible (up to 400 cm2/Vs for a 93% SGOI). Opposite trends were observed for holes and electrons: while the hole mobility is increasing with increasing Ge content, the electron mobility decreases. Moreover, the density of interface traps and the density of oxide charges were found to increase with increasing Ge content.

The on-current (Idsat) enhancement in process-simulated <110> nMOSFETs by a tensile strained cap layer is investigated by mechanical stress and Monte Carlo (MC) device simulation. Our MC model is based on an improved semi-empirical analytical two-band model for electrons. This model is found to compare favorably to pseudopotential MC results with some underestimation of the on-current improvement. The MC simulations yield Idsat gains of around 20 % and 10 % for a 60 nm thick cap layer with 2 GPa and 1 GPa intrinsic stress, respectively, with decreasing tendency upon scaling. These current gains are significantly higher than the gains predicted by drift-diffusion simulation with the linear piezoresistance model.

Strain technology under metal/high-k damascene-gate stacks is discussed. It is estimated from stress simulation that compressive stresses for pMOSFETs with compressive stress-liners of SiN film and eSiGe are enhanced by damascene-gate process. Moreover, it is confirmed by UV-Raman spectroscopy in plane view that the compressive stress is considerably enhanced just after dummy-gate removal step, especially for smaller gate length. On the other hand for nMOSFETs, tensile stresses even by top-cut tensile stress-liners of SiN film are slightly enhanced by damascene-gate process. Therefore, high drivability of high-performance CMOS devices with gate length of 40 nm are achieved by not only thinner Tinv of 1.4 nm but also higher transconductance.

The effects of SiN stress film, argon implantation and annealing on the stress of planar and patterned samples were examined. Stress levels changed with SiN films of line-and-space patterned samples can be well characterized by de-convoluting the UV-micro-Raman spectra. Argon implantation caused stress because argon atoms remained in silicon after long-time annealing. Larger stress change in the patterned sample than the planar sample by argon implantation was observed.

We have investigated the etch rates and the angle subtended for Ge as a function of varied Inductively Coupled Plasma (ICP) power, CCl2F2 flow, and Cl2 flow. The etch rate of Ge increases from 374 to 520 Aå/min as ICP power increases from 400 to 700 W, whereas the etching rate of Ge decreases from 524 to 400 Aå/min as CCl2F2 flow increases from 40 to 80 sccm, respectively. Also, the etching rate of Ge decreases from 467 to 400 Aå/min as Cl2 flow increases from 0 to 20 sccm. As ICP power increases the angle subtended also increases. From the SEM photographs it appears that Ar/CCl2F2 /Cl2 ICP etching causes the presence of carbon-based material in the form of large particles.

The manuscript presents the results of a combined experimental and modeling study on the Liquid Phase Diffusion (LPD) growth of single crystal SixGe1-x on Germanium with and with the application of magnetic fields. Although the LPD process is mainly diffusion driven through out the growth period, strong natural thermosolutal convection occurs in the first five hours of growth, and the growth interface is concave to the melt. Applied rotating and static magnetic fields were considered to examine the growth and silicon dissolution processes in the LPD system. Results show that the application of a combined applied magnetic is beneficial.

The plasma etching of Si3N4 spacers selective to germanium with less than one nanometer recess in a CH3F/CF4/O2 mixture has been studied. The X-Ray Photoelectron Spectroscopy, Angle Resolved X-ray Photoelectron Spectroscopy, Transmission Electron Microscopy, Ellipsometry and Mass Metrology analyses suggest that the oxidation of the germanium top layers is the key parameter to achieve a high selectivity during the Si3N4 spacer patterning.

This study presents a way to design chips to obtain uniform selective epitaxial growth of SiGe layers in pMOSFET structures. The pattern dependency behavior of the growth has been controlled over different sizes of transistors. It is shown that the exposed Si coverage of the chip is the main parameter in order to maintain control of the layer profile. This has been explained by gas depletion theory of the growth species in the stationary boundary layer over the wafer. The control of SiGe layer profile has been obtained over a wide range of device sizes by optimized process parameters in combination with a wafer pattern design consisting of dummy features causing uniform gas depletion over the chips of the wafer.

DiMethylAminoGermaniumTriChloride (DiMAGeCl) is evaluated as a C-dopant source for selective SiGe and Ge epitaxy using Chemical Vapor Deposition. We determine the C-level as a function of temperature and pressure and we examine the applicability of DiMAGeCl for the growth of high quality Ge on Si.

The negative bias instability on p-channel and n-channel polycrystalline silicon thin-film transistor is investigated. Negative threshold voltage shift is observed in p-channel TFTs and is attributed to the positively charged donor type interface traps. On the other hand, polarity change of threshold voltage shift is observed in n-channel TFTs, suggesting two competing mechanisms. Negatively charged acceptor type interface traps are the dominant factor for the positive threshold voltage shift. As the gate stress voltage increases, accumulated holes are trapped in the insulator via Fowler-Nordheim tunneling and are responsible for the negative threshold voltage shift. The stress-induced hump effect is attributed to higher electric filed at the edge transistors as compared to channel transistor along the channel width direction.

This report describes the ivestigation of the electronic properties for the single and multiple quantum well devices with the Ge composition of 20 % and 40 % fabricated on SOI. The single quantum well device with the 40 % Ge-composition showd that the highest hole mobility below the effctive electric field bellow -0.7 MV/cm. The mobilities of the multiple quantum well devices were inferior to those of the devices with the Ge composition of 20 %. This was due to that the increase of Ge composition caused three-dimensional growth in forming well layer, which resulted in the reduction of the well layers and interfaces quality.

In this work, a simple model, with a higher interface trap density in the upper half of Ge bandgap than that in the lower half, is proposed to explain the abnormal behaviors in Capacitance-Voltage characteristics of both p- and n-MOS capacitors on Ge substrate using different surface passivation. Variable rise/fall-time charging pumping measurement is used to study the energy distribution of interface trap density in HfO2 gated Ge MOSFETs. Our results reveal that Dit is higher in the upper half of the Ge bandgap than that in the lower half of the bandgap. These results are also consistent with the observation that n-channel mobility is more severely degraded compared to p-channel for Ge MOSFET.

Mechanical strain can be used to improve electronic transport properties in advanced short gate length Si-based Metal Oxide Semiconductor Field Effect Transistors. The controlled introduction of strain in the channel area of transistors (thanks to recessed SiGe sources and drains, contact etch stop layers or to previous processing at the wafer scale) can indeed increase the carrier mobility by a factor of up to two. We have used here ultra-violet and visible Raman Spectroscopy to study the processes that can influence strain during the elaboration of strained Si On Insulator (sSOI) substrates. The results obtained during analyses of tensily-strained Si layers grown on polished Si1-xGex virtual substrates (VS) show that the strain can be preserved for 20% of Ge. However, we observed a relaxation of the strain for 40% Ge, after layer transfer onto oxidized silicon. A definite strain relaxation at the edges of lines patterned in sSOI wafers was also demonstrated. A good agreement between experimental results and simulation has been achieved

Effects of oxidation induced Ge condensation on local strains in Si microstructures induced by the SiGe stressor were investigated. The strain ratio in the Si microstructures increased by the Ge condensation, due to piled-up Ge atoms at SiO2/SiGe interfaces. However, the strains were relaxed by defect generation, if the concentration of piled-up Ge exceeded a critical value (~40%). Thus, a possibility to enhance local strains by oxidation induced Ge condensation was demonstrated.

The SGOI structures using Ge condensation method have been fabricated by rapid thermal chemical vapor deposition using H+ and He+ ion-implantations, and deep level defects investigated using the deep level transient spectroscopy (DLTS). According to DLTS measurement, a deep level defect induced during Ge condensation process was found at 0.28 eV above the valence band with capture cross sections of 2.67x1017 cm-2, and two extended deep levels at 0.54 eV and 0.42 eV above the valence band with capture cross sections of 3.17x1014 cm-2, 0.96x1015 cm-2, respectively. Of ion-implanted samples, the densities of the newly generated defect as well as the existing defects were decreased effectively. And, Coulomb barrier height of the extended defect was drastically reduced. Thus, we suggest that the Ge condensation method using the H+ ion implantation could reduce deep level defects generated from the Ge condensation and control electrical properties of condensed SiGe layers.

We report preliminary results on the Raman characterization of strained-Si films pseudomorphically grown on (001), (110) and (111) SiGe virtual substrates. Because the relation between strain or stress and the Raman frequencies are complex, we first derive the strain-shift coefficients for the different substrate orientations considered in this work. Then, visible and near-UV Raman spectroscopies were used to extract the in-plane lattice parameter of the virtual substrate and the strain in the thin silicon epitaxial layers grown on top. Finally, we investigated the in-plane strain distribution in strained Si/SiGe buffer layers grown on (110) and (111) silicon substrates by Raman imaging. In-plane strain fluctuations are observed both in the epilayer and the virtual substrate for all substrate orientations.

We present a method for fabricating hybrid-orientation surfaces composed of regions of single-crystal Si(001) and Si(110), with the potential for transfer to foreign surfaces, providing a material suitable for high-performance CMOS devices on a variety of host substrates.

Formation of SiGe quasi-single crystal grains on insulator by the indentation-induced solid-phase crystallization has been investigated. The incubation time for nucleation was significantly reduced by the indentation. As a result, large (~2um) crystal grains were realized at controlled positions for samples with all Ge fractions. This method is expected to be useful for realization of the 3D-ULSIs and system-in-displays.

The trapped charge distributions in Al/TiO2/GeOxNy/p-Ge and Al/ TiO2/SiOxNy/strained-Si0.91Ge0.09 structures subjected dynamic stress of different amplitude and frequency in order to analyze the transient response and the degradation of the oxide as a function of different stress condition. The current transients and voltage transient observed in dynamic voltage (-4V to -9V) and current stresses (-2.5mA/cm2 to -12.5mA/cm2) have been interpreted in terms of the charging/discharging of interface and bulk traps. The evolution of the current during unipolar voltage stresses shows the degradation being much faster at low frequencies than at high frequencies.

This paper presents the accurate measurement by Transmission Electron Microscopy of the Solid Phase Epitaxial Regrowth of an amorphous Germanium layer. Moreover, these experiments give the proof that End of Range defects form in Germanium during the regrowth of the layer.

We investigate the temperature dependence of p-i-n photodetectors realized in germanium on silicon. The dark current increases by a factor 1.6÷1.9 every 10oC and is typically dominated by generation in the space charge region, with diffusion contributing in the best samples. The NIR responsivity decreases with temperature in devices with a large defect-density, but is more stable in high quality photodiodes. These findings provide a relevant insight on the design Ge-on-Si NIR detectors to be operated above room temperature

Aspect Ratio Trapping is a promising technique for heterointegration of Ge onto Si substrates. By growing Ge in patterned SiO₂ trenches, lattice-mismatch dislocations arising from the epitaxial interface can be effectively trapped. However, planarization of these samples is required to enable device fabrication. This paper describes the development and optimization of a chemical mechanical polishing process for these structures. Polishing using diluted Nalco 2360 slurry was investigated, with the addition of NaOCl, NH₄OH, or H₂O₂, for Ge removal rate increase. A slurry mix consisting of Nalco 2360, H₂O₂, and DI water was shown to have low dishing and low surface metals contamination, and planarized the Ge Aspect Ratio Trapping samples very effectively.

Nickel germanides formed on crystalline n-Ge (110) substrate are investigated. By the XRD analysis, Ni5Ge3, NiGe, and Ni2Ge phases are formed sequentially with the increasing annealing temperatures from 300oC to 600oC on n-Ge (110) substrate. NiGe, however, is the only phase observed on (100) substrate at corresponded annealing temperatures. On the other hand, there shows a strong tensile stress in the underlying Ge (110) substrate. The tensile strain may be due to the lattice mismatch between nickel germanides and Ge substrate.

We have demonstrated that the Si nucleation density can be controlled over ~1011cm-2 by changing the conditions of GeH4-exposure treatments just before Si2H6-LPCVD such as the GeH4 pressure, exposure time and the substrate temperature. This technique is quite effective to achieve a uniform size distribution of Si-QDs with an areal density of the order of 1013cm-2.

We have studied energetics and atomic and electronic structures of Ge mono-vacancies under biaxial and uniaxial strain. We have found that compressive strain drastically reduce the formation energy of Ge mono-vacancy, and strain induced Ge vacancy formation is expected. Further, our calculations show that energy levels of Ge mono-vacancies sensitively depend on the types of applied strain. In particular, direction of uniaxial strain greatly affects the position of Ge mono-vacancy levels. Our calculation indicates that acceptor levels are easily generated under [110] uniaxial compressive strain. Whereas, acceptor level generation is difficult under [100] uniaxial compressive strain.

Selective epitaxial growth of B-doped SiGe (SiGe:B) films is one of the key techniques for the embedded SiGe (e-SiGe) structure for high-performance pMOSFETs. Both the high Ge composition and the high B-doping concentration are desirable for increasing the stress in the channel region and decreasing the series resistance in the source/drain region. However, increasing Ge composition and B concentration may lead to defects in the epitaxial SiGe:B layer and thus to the roughening of the surface of the films. In this work, influence of B doping on the surface roughness and the roughening process in SiGe:B epitaxial films are examined.

Low temperature epitaxial growth of the full Heusler alloy Fe₂MnSi layers on Ge(111) substrates has been investigated. Good crystallinity of Fe₂MnSi layers and a very sharp interface of Fe₂MnSi/Ge structure were realized at 200^oC.

The electrical characteristics of epitaxially grown Fe3Si/Si structures were investigated. From the I-V and C-V measurements, excellent Schottky barrier characteristics (n=1.0, φn=0.62eV) were demonstrated. Moreover, the electrical characteristics did not deteriorate after post-annealing (400oC, 1h), which guaranteed the thermal stability of Fe3Si/Si structures up to 400oC.

In this paper, we demonstrate Schottky barrier height adjustment of Nickel-Germanosilicide (NiSiGe) contact on Si0.7Ge0.3 by controlling the As+ implants at the NiSiGe/Si0.7Ge0.3 interface. Various dosage of As+ was implanted into both n- and p- type Si0.7Ge0.3 to demonstrate the control of effective barrier height. Electrical characterization shows ohmic contact can be achieved for NiSiGe on n-Si0.7Ge0.3. We use 2-D XRD to confirm presence of NiSiGe phase and TOF-SIMS to confirm the segregation of As+ doping at the contact-semiconductor interface.

Epitaxial Ge(111) layers were grown by Molecular Beam Epitaxy (MBE) on cubic PrO2(111) / Si(111) systems. The achieved Ge-on-Insulator heterostructures were widely characterized by a combination of in-situ and ex-situ techniques. It was shown that an interaction between the PrO2(111) layer and the growing semiconductor deposit occurs in the initial Ge evaporation stages, which results in a complete reduction of the buffer oxide to a cubic Pr2O3(111) film. On such a thermodynamically stable support Ge grows epitaxially in the Volmer-Weber mode, forming single crystalline, (111)-oriented islands. By suitably tuning the deposition parameters, these islands coalesce in a closed, atomically smooth, single crystalline Ge(111) layer with the same type-A orientation as the Si(111) substrate.

In this paper, defects and strain in SiGe heterostructures with 8, 13, 25, or 40 nm strained-Si (sSi) on top of 300 or 600 nm Si0.77Ge0.23 buffer have been examined. We found that threading dislocations (TDs) in the super-critical thickness sSi samples are more evenly distributed, while they are severely trapped inside TD pileups in the sub-critical thickness sSi samples. Raman spectroscopy revealed that the relaxation degree of the 300 nm SiGe layer decreases from 80% to 67% with the sSi layer increase from 8 nm to 40 nm. This suggests a continuous relaxation of the highly compressively strained, thin SiGe buffer during or even after sSi growth, and its gradual suppression by presence of a tensile strained sSi layer. Based on these observation, we suggest that an in-situ thermal annealing prior to the sSi growth will help to enhance the strain relaxation of thin SiGe buffers.

A new approach to SiGe island ordering on mechanically responsive silicon nanomembranes (SiNMs) is examined using mechanics modeling. Double-sided deposition on freestanding substrates results in ordered islands on both surfaces. This ordering occurs because the extreme thinness of the SiNM allows islands on one surface to create significant strain fields, which guide the nucleation of subsequent islands, on the opposite surface. The locations of nucleation sites predicted by the modeling agree with experimental observations of SiGe islands grown on silicon nanomembranes. The modeling shows that the island location and the strength of ordering can be controlled by manipulating the thickness of the membrane.

Spectroscopic Ellipsometry (SE) is a non contact, non destructive approach based on the change of polarisation of light after reflection on a sample. SE allows the precise determination of the refractive indices and thicknesses of the films. With UV-Vis-IR spectroscopic ellipsometer, not only epilayer thickness and Ge concentration can be obtained with the UV-Vis channel, but also p-type dopant concentration with the IR channel. In this presentation, an alloy model will be introduced first to obtain Ge concentration. The principle to determine dopant concentration and electric properties of the film will be given secondly. With the advanced SOPRA ellipsometer tool, four types of samples were characterized, which are (a) single SiGe layer (Box), (b) SiGe layer with Si cap, (c) SiGe layer with graded Ge concentration and (d) Boron doped SiGe layer

This paper discusses the fundamental challenges and reports the recent progress in enabling embedded Si:C (eSi:C) nMOS source/drain stressor technology. A thick oxide (SiON, Toxgl ~ 26Aå) long channel (Lgate in the range of 80nm-110nm, gate-pitch =336nm) nMOS device was used as the main test structure to evaluate the impact of eSi:C stressor to the device electrical characteristics, such as channel mobility and drive current. It was demonstrated that modifying the conventional Si CMOS fabrication process to accommodate the intrinsically meta-stable eSi:C material property is crucial in keeping carbon in its substitutional site thus to preserve strain in the eSi:C stressor throughout the device fabrication process. Significant channel mobility and drive current enhancement was demonstrated in the thick-oxide long-channel nMOS devices using in situ phosphorus-doped (ISPD) epitaxial eSi:C source/drain material.

In addition to device scaling, strain engineering using SiC stressors in the S/D regions is important for nFET performance enhancement. In this paper, we review the characterization of fully-strained epitaxial SiC and in-situ doped SiC:P films for various ion implant conditions and anneals that are typically used in traditional CMOS flows. Full characterization has helped identify process integration schemes which give significant drive current enhancements.

When wafers with embedded SiGe (e-SiGe) are laser annealed, serious wafer warpage can result. This warpage will lead to registration error when patterning is attempted to create contacts, and can make subsequent processing of the wafers impossible. If relatively low levels of carbon are introduced into the SiGe prior to laser anneal, wafer warpage is reduced. Carbon can be introduced through implantation or by co-deposition during the epitaxial growth of the SiGe. This paper illustrates the impact that laser anneal has on e-SiGe wafers, and explores the impact of carbon on these effects. Mechanisms by which carbon influences warpage are discussed, and the manufacturing impact of this introduction is reviewed. Finally, species other than carbon are examined for their ability to modify wafer warpage in laser annealed e-SiGe wafers.

Deals with (i) the growth and thermal stability of large number or periods SiGe/Si superlattices on bulk Si and (ii) the impact of B and P doping and of C alloying of SiGe on the growth kinetics of SiGe/Si superlattices.

Poly-crystalline Silicon-Germanium is a promising structural material for post-processing Micro Electro-Mechanical Systems (MEMS) above CMOS due to its excellent mechanical and electrical properties when deposited at CMOS compatible temperatures. In this work an optimized process to deposit high quality crystalline poly-SiGe layers with low stress, low strain gradient and good within-wafer uniformity at a manufacturable throughput is developed. The process used to deposit the layers is based on a combination of CVD and PECVD SiGe depositions. Firstly, the CVD SiGe process has been extensively characterized to the extent that the influence of thickness, Ge concentration and B concentration on film stress and strain gradient is now well understood. Then the interaction between the PECVD SiGe and the underlying CVD layer has been investigated. This combined knowledge enables specific tailoring of the CVD-PECVD SiGe stack to give the desired strain gradient for a certain layer thickness.

An appropriate merging of mobility enhancement technologies with multi-gate device structures has been strongly required for future high performance and low power CMOS. In this paper, we review our recent results concerning multi-gate CMOS with uniaxially strained SOI channels for nFETs and SGOI channels for pFETs. It is shown that those channels are quite effective to increase mobility. It is also suggested that the optimum multi-gate CMOS structures with enhanced mobilities of both electrons and holes can be realized on a conventional (001) substrate in the same <110> current flow direction for n and pFETs.

This paper presents a spectroscopic study of interfacial bonding and substrate gate/dielectric reactions for crystalline Ge-high-K gate dielectric hetero-structures. A novel processing sequence has been developed for (i) depositing HfO2 and Hf Si oxynitrides (HfSiON) onto N-passivated Ge(111) and (100) substrates, designed to prevent subcutaneous oxidation of the Ge substrate during dielectric deposition, and then (ii) eliminating N from Ge-N interfacial bonds during 650-800oC rapid thermal annealing in Ar. This approach has been motivated by spectroscopic studies that have shown that the band-gaps of GeO2 and Ge3N4 are reduced with respect to their Si counterparts and cannot be used as interfacial layers (ILs) either: (i) on n-type Ge substrates, or (ii) in n-MOSFETs in which a p-type Ge substrate is inverted. Changes in interface bonding as a function of post-deposition annealing for G/HfO2 Ge/HfSiON, and Ge/HfSiON/HfO2 stacks have been studied by X-ray absorption and photoelectron spectroscopy revealing (i) conduction and valence band edge defects, as well as (ii) significant process induced changes in these defect densities.

In this work, we have performed a thorough study of the mobility in 'Si / s-Ge / Si' QW heterostructure pMOSFETs. Through experiments and detailed simulations, the effects of the s-Ge quantum well (QW) thickness and quantum confinement effects on the hole mobility of both, single-gate (SG) and double-gate (DG) QW pMOSFETs have been explored.

Apart from the widely used bandgap engineering in the base of Hetero-junction Bipolar Transistors (HBTs) and strain engineering in CMOS SiGe has many other possible application in Si technology. This paper will discuss several examples, both within and outside (Bi)CMOS technology. For instance, SiGe bandgap engineering can be used in power diodes. Other possibilities make use of the fact that SiGe can be etched selectively towards Si. This allows, for example, creation of cavities in the silicon substrate. These can be used for, e.g., reduction of parasitic capacitance, device isolation, or electric field shaping.

In this paper, we review integration of selective epitaxy in advanced logic and memory devices. Embedded SiGe epitaxy has been adapted for logic pMOSFET fabrication from the 90 nm technology node and device performance continues to scale with higher [Ge] in the epitaxial SiGe layer. For nMOSFET performance boost, use of embedded silicon carbon (Si:C) epitaxial layer has been considered. Recent improvements in crystal quality of selective in-situ phosphorus doped Si:C epitaxy enables significant transistor drive current increase. For integration of Si:C epitaxy, effect of various thermal annealing processes on substitutional carbon incorporation and NiSi formation on Si:C epitaxy are described. Also, heavy phosphorus doping in Si and Si:C layers is discussed in terms of film resistivity and strain contribution. Selective epitaxy is being used to form elevated source/drain in DRAM memory devices where it provides immunity against short channel effects and results in improved retention time.

We have studied the low temperature (~ 650oC), high HCl partial pressure (180 Torr) selective etch of SiGe versus Si inside a RP-CVD reactor. The surface roughness strongly increases while vertically etching fullsheet Si1-xGex layers. We have also laterally etched (Si / SiGe) multilayers patterned along the <110> directions. The best selectivities and the highest SiGe etch rates have been obtained for the highest Ge content studied, i.e. 40%. <111> facets have been revealed at the end of tunnels. A strong increase (x 18) of the <110> lateral HCl etch rates has been evidenced when increasing the Si0.6Ge0.4 layer thickness from 5 up to 20 nm. Very good SiGe versus Si selectivities have been obtained with slightly higher etch rates than on bulk Si when HCl etching (Si / SiGe) multilayers grown on Si0.8Ge0.2 virtual substrates. Finally, a strong HCl etch in-plane anisotropy has always been evidenced. <100> oriented pattern corners are indeed far more etched than <110> oriented edges.

Three very different approaches to laterally etch SiGe layers selectively versus Si have been evaluated in terms of etch rate, selectivity and isotropy. The first one calls upon a CF4 plasma at low pressure and room temperature. The second one consists in the use of gaseous HCl at relatively high temperature and pressure in an epitaxy reactor. The third one is based on the use of appropriate chemistries in a wet bench. Germanium concentration impact on processes has been studied in the 20 - 40% range. To allow a strict comparison between so different processes, common test structures have been fabricated and etching targets have been jointly defined. Each technique entails its strengths and drawbacks, which will have to be carefully weighted when selecting one instead of another for a given sacrificial material configuration.

Si has dominated semiconductor industry for decades. However, new materials are appearing in this field such as Ge, GaAs and InxGa1-xAs. In semiconductor processing several wet chemical steps are used including cleaning, etching and stripping. Knowledge of etch rates in these solutions is of great importance. In this paper, an etch rate study was performed for Ge, GaAs and InxGa1-xAs in several wet chemical cleaning solutions. The chemistries studied include acids (HCl, HF, HNO3, H2SO4, H3PO4, H2O2) and bases (NH4OH) and peroxide based mixtures. It has been found that etch rates are much higher than for Si due to the formation of soluble oxides. Therefore, "fine-tuning" of the chemistries is a prerequiste when introducing these materials in microelectronic industry.

Selective epitaxial growth of Si and SiGe films has been applied to the fabrication of many high-performance MOSFETs, because new device structures can be realized by selective epitaxial growth. Selective growth of Si(Ge) at the source/drain region is the most well-known example. Precise control of the selective epitaxial process enables the best performance with the desired structure. Control of the selectivity is also important for a robust manufacturing process. Selective epitaxial growth is essential for next-generation MOSFETs, such as FinFETs. Innovation of selective epitaxial growth will spur the continuous progress of MOSFETs.

Embedded SiGe (eSiGe) has become a widely used method to enhance device performance. The key step in this process is the selective epitaxial growth of a SiGe film in the source/drain region of the transistor. In the present study, we describe how the epitaxial growth may be controlled on multiple levels. On a microscopic level, the morphology is a function of the process conditions and the structure in which the epitaxial film is grown. On a macroscopic level, the loading effect can be characterized by a simple empirical model based on gas phase reactant depletion. Finally, on a global level, the within-wafer thickness variation can be controlled by temperature-based uniformity tuning, and the run-to-run growth rate drift can be controlled by an advanced process control (APC) feedback loop.

Deals with the low temperature and high temperature boron and phosphorous doping of Si for raised sources and drains and MEMS purposes. Hydrogenated (NSEG) and chlorinated (SEG) chemistries have been probed.

Atomic layer doping of phosphorus (P) and arsenic (As) into Si was performed using the vapor phase doping (VPD) technique. For increasing deposition time and precursor gas flow rate, the P and As doses tend to saturate at about 0.8 and 1.0 monolayer of Si, respectively. Therefore, these processes are self-limited in both cases. When a Si cap layer is grown on the P-covered Si(001), high P concentration of 3.7 × 1020 cm-3 at the heterointerface in the Si-cap/P/Si-substrate layer stacks is achieved. Due to As desorption and segregation toward the Si surface during the temperature ramp up and during the Si-cap growth, the As concentration at the heterointerface in the Si-cap/As/Si-substrate layer stacks was lower compared to the P case. These results allowed us to evaluate the feasibility of the VPD process to fabricate precisely controlled doping profiles.

Selective polycrystalline growth is obtained by incorporation of high level of B concentration at the interface between the Si substrate and the deposited Si layer using atomic layer doping (ALD). The high doping concentration of B at the interface is covering the crystal information of the Si lattice resulting in polycrystalline growth. B diffusion into deposited Si layer is pronounced by the transition from epitaxial Si growth to polycrystalline growth. Effective activation energy of the selective polycrystalline Si growth on Si is not different from that on SiO2. The transition from epitaxial growth to polycrystalline growth is observed for B doses in the range of 2-4×1015 cm-2 as well for selective Si as for selective Si0.8Ge0.2 growth.

This paper reports on the Solid Phase Epitaxial Regrowth (SPER) of phosphorus implanted pre-amorphized p-type germanium at 350 oC using Rapid Thermal Annealing and focuses more specifically on the P concentration dependence of the regrowth velocity. This is studied by a combination of Rutherford Backscattering in the channeling mode (RBS-C) and Secondary Ion Mass Spectrometry (SIMS). As will be shown, different regimes can be distinguished whereby for chemical concentrations up to 4-5x1020 cm-3 an enhanced recrystallization occurs compared with undoped amorphized Ge. Above this metastable solid solubility limit, the regrowth is retarded, due to the redistribution and snow plow of the excess P across the amorphous/crystalline interface. It will also be demonstrated that during SPER at 350 oC, limited P-diffusion occurs even at the highest implantation dose studied.

It was found that for strained Si channel layers of supercritical thickness on relaxed SiGe virtual substrates, the 1/f noise on average is maintained at the same level as in unstrained devices. Short gate length nMOSFETs were analyzed statistically and the noise level variation, across a large number of samples, was similar in strained and unstrained devices. The obtained noise level variation was partly related to gate length fluctuations across the wafer, which was evident from a small VT fluctuation.

A commercial supercritical thickness strained Si-on-insulator (SC-sSOI) wafer was characterized by large-area synchrotron x-ray topography at the glancing incident condition. Several kinds of contrast showing crystalline imperfections were observed all over the wafers, such as macule and crosshatch patterns. Similar crosshatch patterns were also observed in the x-ray topographs of a conventional strained Si-on-insulator (sSOI) wafer and a strained Si wafer that has the strained Si layer epitaxially grown on the relaxed SiGe layer on the insulator (SGOI) structure. This indicates that the crosshatch pattern of the SC-sSOI wafer originates from the lattice distortion in the original SiGe substrate of the strained Si layer.

Nano-beam diffraction (NBD) has been successfully used in measuring channel strain in device of embedded SiGe (eSiGe). Strain measurements have been correlated to different processing conditions and microstructures of eSiGe and device performance. For intrinsic eSiGe without growth defect with 15-17%Ge, the average channel strain measured by NBD is ~ -0.55%, consistent with our previous measurement by convergent electron beam diffraction (CBED) and TCAD simulation. For graded eSiGe with average ~22%Ge, the average channel strain measured by NBD is ~ -0.90%, which is lower than the TCAD simulation. Differences between experimental results and simulation are also discussed.

Intrinsic mechanical stresses in device structures with strained SiGe and Ni silicide have been studied. Stresses in blanket films were derived from wafer curvatures after different stages of device processing. The measurement suggested that the temperature coefficient of NiSi linear expansion equals 1.16⋅10-5 K-1. Experiments showed that silicide films on epitaxial layers of SiGe compensated SiGe stresses in a much greater degree compared to what would follow from the thermal contraction model. Electron microscopy revealed that NiSi(Ge) films formed on SiGe had rough surfaces reducing overall stresses in Si/SiGe/NiSi structures. Computer simulations of MOSFETs with embedded SiGe Source/Drain regions indicated that partial consumption of SiGe layers at silicidation, tensile stress developed in NiSi films due to the thermal contraction and silicide-SiGe interface roughness might reduce compressive stresses in MOSFET channels by 15 - 40%.

We are studying three types of these detectors for use at 1310 nm; normal incident illuminated p-i-n detectors (NI-PD), waveguide p-i-n detectors (WG-PD), and avalanche photodetectors (APDs). NI-PDs have achieved -14.5 dBm sensitivity at 10 Gb/s and 850 nm, which is comparable to similarly packaged GaAs devices. Unlike GaAs detectors, however, the Ge detectors can also operate at 1310nm, with a ~0.5dB sensitivity improvement expected. WG-PDs have achieved bandwidths of approximately 30 GHz at 1550 nm with internal quantum efficiencies of 90%, and similar, or better, performance is also expected at 1310 nm. Normal incident APDs operating at 1310 nm have achieved a gain-bandwidth product of 153 GHz which exceeds that of a commercial InP-based APDs, These devices also have a primary responsivity of 0.54 A/W with a 3-dB bandwidth of 9GHz at a gain of 17.

We present high performance, Ge-based photodetectors and electro-absorption (EA) modulators for electronic-photonic integrated circuits on Si platform. As a pseudo-direct band gap material, Ge offers excellent optoelectronic properties with CMOS compatibility. We demonstrate waveguide-integrated Ge photodetectors with a high responsivity of >1.0 A/W in a broad spectrum range of 1470-1570 nm and >7 GHz bandwidth at a low reverse bias of -0.1 V. We have also achieved a waveguide-integrated, ultra-low energy GeSi EA modulator with a small footprint of 30 µm2, a 10 dB extinction ratio at 1540 nm, an ultra-low energy consumption of 50 fJ/bit, and an operation spectrum that covers half of the C-band. These devices have been fabricated with standard CMOS technology and can be conveniently integrated with CMOS circuits for electronic-photonic integration.

In the first part of this paper, we have quantified the surface roughness, the degree of strain relaxation and the defect density in thick Ge layers grown using a low temperature / high temperature approach on nominal and 6oC off (towards one of the <110> directions) Si(001) substrates. In the second part, we have succinctly described the Si passivation process we use on Ge prior to gate stack formation in order to obtain high performance p-type metal oxide semiconductor field effect transistors.

We demonstrate low dark currents Ge pin photodiodes on Si substrate fabricated by UHV-CVD without post-growth annealing and possibility of fabricating any composition SiGe diode between Si0.5Ge0.5 and Ge with as a high responsivity as theoretical calculation even at 0V. SiGe diodes showed diode characteristics like reference Si diodes but had much higher dark currents because of the surface leakage. The Ge diodes had low dark currents but some Ge diodes had high dark currents because of a structural difference. We discuss the difference of the current-voltage characteristics and responsivity between Ge and SiGe and between the Ge diodes with different structure. We also deal with a method to reduce a dark current without post-growth annealing using a Si cap. The photodiodes with low dark current without high temperature annealing is a key to photonics-electronics (P-E) convergence using standard Si processing.

This paper describes Luxtera's approach to the monolithic integration of Germanium photodetectors with CMOS electronics for high speed optical transceivers. Insertion of the Germanium module into a CMOS process and its impact on the design of the detectors is discussed. The deployment of the devices in 4x10 Gbps receivers is also described, wherein an optical sensitivity of - 19 dBm for a bit error rate of 1e-12 is demonstrated. The optimization of the transimpedance amplifier to take advantage of the reduced capacitance (<20fF) of the waveguide detectors is also discussed.

Among the semiconductor materials, silicon stands out for its technological, industrial, and scientific relevance. Its growth process has been widely studied, theoretically and experimentally, so that it's surface and gas phase kinetics are mostly known. In this work this knowledge was exploited to develop a 3D Kinetic Monte Carlo model that, combined consistently with a detailed fluid dynamic analysis of a CVD reactor and ab initio simulations of relevant surface processes, was used to investigate the surface and gas phase dynamics active during the film growth. The proposed mathematical model is thus able to link information coming from the atomic scale, such as the diffusion of hydrogen and silicon adatoms and dimers, with the surface microstructural evolution (density and shape of islands), and, finally, with the reactor operating parameters, such as pressure, temperature and gas phase composition.

Si:C films have been successfully grown by the gas-source molecular beam epitaxy. The thermal stability of Si:C was comprehensively studied, and the formation of SiC and the diffusion of carbon atoms from the substitutional sites were observed when the film was annealed higher than 800 C. It was shown that the SOI substrate was very promising substrate in order to realize the strained Si/strain-relaxed Si:C structure, which is applicable to the vertical MOSFETs. Finally, the relaxation mechanism of Si:C was studied. It was shown that the Si:C was hard to form the misfit dislocations at the interface and that the stress was released by the cusp formation. The phenomenon is suitable for the application of Si:C to the source/drain stressor.

Selective and nonselective growth of Si and SiGe was performed in a large batch vertical LPCVD furnace on 200mm substrates. Excellent atomic crystal quality, as demonstrated by RHEED, and low defect epitaxy were observed using a wet HF-last process to remove native oxide followed by a H2 bake. Although an oxygen free interface, measured by SIMS, was achieved with a H2 bake temperature of 800C, a temperature of 900C was required in order to remove interfacial features detectable by laser surface scan. Selective Si deposition rates of 10nm/min., using SiH2Cl2/H2 chemistry have been demonstrated at a temperature of 850C and a pressure of 500Pa.

SiGe quanrum rings (QRs) grown at 500oC and 600oC were observed on SiGe quantum dots (QDs) capped with Si. Average depth and diameter are 9 nm and 185 nm, respectively, for QRs at 500oC, while those are 0.9 nm and 84 nm for QRs at 600oC. Ge out-diffusion mechanism is proposed to be responsible for nanorings formation in 500oC, and Si surface diffusion toward strain-free edges is proposed to be responsible for nanorings formation in 600oC. Raman spectroscopy demonstrates that formation of QRs in 600oC is close correlated with a strain-driven process. QRs grown in 600oC are the metastable states and can be only observed in very limited conditions. Thick cap and high thermal budget can both destroy SiGe nanorings structures.

Density functional theory with local density approximation including on-site Coulomb interaction has been used to calculate the formation and migration energy of the neutral and charged vacancy and self-interstitial in germanium.

Ge and III-V semiconductors are potential high performance channel materials for future CMOS devices. In this work, we have studied Atomic Layer Deposition (ALD) of high-k dielectric layers on Ge and GaAs substrates. We focus at the effect of the oxidant (H2O, O3, O2, O2 plasma) during gate stack formation. GeO2, obtained by Ge oxidation in O2 or O3, is a promising passivation layer. The germanium oxide thickness can be scaled down below 1 nm, but such thin layers contain Ge in oxidation states lower than 4+. Still, electrical results indicate that small amounts of Ge in oxidation states lower than 4+ are not detrimental for device performance. Partial intermixing was observed for high-k dielectric and GeO2 or GaAsOx, suggesting possible correlations in the ALD growth mechanisms on Ge and GaAs substrates.

New structures and materials alternative to conventional bulk-Si(001) substrates are now under consideration for their application to CMOS channel layers on a Si platform. However, mismatch of lattice parameter between the alternative channel material and the Si substrate inevitably causes defect introduction which is one of crucial issues when implementing the formation of channels on Si. In this work, we perform interface and defect engineering for group IV semiconductor materials; Si with hybrid crystal orientation, Ge, and Sn. Engineered channel crystals formed with the wafer direct bonding and heteroepitaxy technologies are characterized in terms of crystalline quality and strain.

The interface traps in HfO₂/Ge is reduced by fluorine treatment, and photoreflectance spectroscopy (PRS) which has some merits such as nondestructive and contactless, is applied for characterization of fixed charges distribution to HfO₂/Ge gate stack as a new type of measurement method. C-V characteristics show that the sample treated with fluorine before deposition by photo-assisted MOCVD has small hysteresis, and interface states are improved. PRS signal of HfO₂/Ge gate stack can be detected, and these measurements show that fixed charges are mainly distributed at interface and reduced by fluorine treatment.

A post-gate CF4-plasma treatment process is proposed and demonstrated on Ge MOS devices and the effects of F incorporation have been extensively studied on both high-k/Ge gate stacks without any surface passivation and with Si surface passivation. Our results show that: (1) F is effectively introduced into the gate stack by CF4 treatment and segregates near high-k/Ge interface; (2) Electrical characteristics like Dit, gate leakage, C-V hysteresis and breakdown voltage are improved after F incorporation; (3) Post-gate CF4 treatment is also compatible with pre-gate surface passivation, and it can further enhance the device performance. By combining Si surface passivation and post-gate CF4 treatment, interface quality has been greatly improved for high-k/Ge gate stack and a high peak hole mobility of 376 cm2/V⋅s has been achieved for Ge pMOSFETs

Formation of Ge3N4 on Ge(001) substrates by nitrogen radicals and their thermal stability were investigated in this study. A Ge3N4/Ge structure with a root-mean-square surface roughness of 0.18 nm is successfully formed by layer-by-layer manner at a substrate temperature of 300oC. In contrast, island growth and thermal decomposition of Ge3N4 occur during the nitridation at 600oC, and consequently island structures and locally-flat areas are formed. Ge3N4 thickness is saturated at a certain nitridation time and, not only saturation times but also saturation thicknesses are different depending on plasma condition. By a 2-step nitridation in which the nitridation at 300oC and 600oC for 900 sec were sequentially subjected to Ge surfaces, a Ge3N4 thickness much larger than that at the single-step nitridation can be obtained without surface roughening.

It is be hard to believe that nanowires will succeed planar CMOS completely, given some of the fundamental incompatibilities with the expected System-on-Chip needs. Nanowires may eventually replace planar devices for specific applications like memories. However, devices like FinFETs and Tri-gates would stand better chances for CMOS platform integration due to their compatibility with planar devices processing.

Though top-down approach, which leverages on conventional lithography, patterning for wire formation, has been considered as the closest to the manufacturing format, many technology issues or even barriers are still widely remained. These technology concerns will be presented in our discussion, in respect to both the horizontal and vertical wire platforms. With the analysis of the commonality and differences facing both platforms, the potential of the ultimate integration will be addressed

Multi-gate and "Gate-all-around" (GAA) MOSFETs are attractive for deeply-scaled CMOS as their geometry improves electrostatic control, which promises enhanced scalability, and enables lower channel doping, reducing random dopant fluctuations which are a significant source of variation for scaled bulk planar CMOS. Performance boosters such as the use of strain and alternate channel materials to improve carrier transport are essential for future CMOS technologies. In this evening panel discussion we present prospects and challenges for top-down fabricated uniaxial strained nanowire MOSFETs.

We discuss several group IV semiconductor nanowire devices, which are compatible and may outperform conventional CMOS devices. These include gate-all-around nanowire devices, Ge/Si core-shell structures, and tunneling field effect transistors.

III/V MOS transistors are currently attracting considerable attention. The main driving force is that the advantageous transport properties in III/V materials are expected to increase the drive current in the MOS transistors. Major challenges for the III/V MOS technologies include the growth of high-quality III/V materials on Si substrates and the control of the MOS interface. Using the nanowire technology, we have recently demonstrated enhancement mode operation of 50 nm Lg InAs nanowire wrap-gate transistors in a vertical configuration. They demonstrate a transconductance of 0.5 S/mm, an inverse sub-threshold slope of about 80 mV/dec., and an Ion/Ioff ratio > 1000 for a drive voltage of Vd=0.5 V. These results show promise for the use of nanowires in CMOS applications.

To reap the full benefits of superior transport and optical properties of germanium, a low-resistance metal-germanides contact that is compatible with existing Si CMOS process technology would be highly desirable. In this abstract, we report the developments of nickel-germanide (NiGe) contact technology and its combination with Schottky barrier engineering techniques (e. g., dopants and valence-mending absorbate segregations) for contact resistance improvement. In addition, we explore the application of these techniques in NiGe Schottky barrier metal-Ge-metal (MSM) photodetector for low dark current and high speed photodetection applications, such as through Si:C (Metal direct contact on Ge) or Sincorporation (for NiGe). Sulfur is used as example in the valencenmending absorbate scheme in this work. In both cases, significant suppression of dark current (~103 to 104 ×) was observed, with the enhanced hole Schottky barrier heights to 0.49eV (S-incorporated) or 0.52eV (thin Si:C layer). In both surface-illuminated and waveguided schemes, 12-15GHz speed were obtained with 1V operating bias.

The problematics of contacts optimization on Germanium MOSFETs suffers from a gap between fundamental studies and the structures obtained after full processing. The contact properties of metals such as Ti on Ge were so far mostly investigated on weakly n-doped samples under pure Thermionic Emission (TE) regime. In this paper, we detail Schottky Barrier Height (SBH) extractions based on contact resistance (Rco) measurements on highly n- and p-doped Ge, where the predominant tunnel current component results in ohmic behavior. We applied this methodology to our fully-processed GeOI samples with Ti-based contacts, yielding effective barriers of 0.32eV for electrons and 0.15eV for holes. The method provides a good physical understanding of the technological factors impacting their electrical properties, therefore enabling to define paths towards ohmic contact optimization in the context of device integration on GeOI.

Passivation of Ge surface is the biggest challenge in the effort to develop Ge MOS technology. We present ZrO2 on Ge with GeO2 passivating interfacial layer prepared by atomic oxygen beam deposition. Electrical data show that ZrO2 has a high-k value around ~44, indicative of tetragonal phase crystallization. This is also supported by x-ray diffraction data. The dielectric permittivity of GeO2 interfacial layer was estimated about ~4.9, which is very close to the lowest boundary for stoichiometric GeO2 reported in literature.

Realistic amorphous samples of a-Al2O3 and a-ZrO2 were generated by a hybrid classical and density functional theory (DFT) "melt and quench" molecular dynamics approach. The generated samples demonstrated good correlation with reference experimental and simulated properties.

Atom intermixing at metal/semiconductor interfaces is studied using the first-principles theoretical calculations. In this paper, by demonstrating atom-diffusion potentials and electronic structures of Au/Si, Al/Si, Au/GaN, Au/HfO2, Ni_xSi_y/Si and Au_xSi_y/Si systems, we answer various elementary questions concerning to the intermixing; what is the motive force of intermixing, how the intermixing proceeds, what are relevant factors to prevent the intermixing, what origins distinguish silicide formation from random alloying, why the silicide stoichiometry is limited on Si substrate, and how and why the Schottky barrier changes with varying the silicide stoichiometry.

Neopentasilane (Si5H12) has been used as a precursor for the chemical vapor deposition epitaxy of silicon and Si1-yCy alloys at temperatures from 550 to 700 oC. This paper summarizes the experimental findings of high growth rates of high quality epitaxy and planar films and then proposes mechanisms to support these observations. Concerted mechanisms, which can lead to growth without the usual requirement of open sites on an otherwise hydrogen covered surface are described as they relate to high -order silanes.

We describe new routes to the growth of Ge and Sn-containing semiconductors on Si(100). For modest Sn concentrations GeSn alloys are expected to be direct-gap materials and this property can be exploited to develop band-to-band devices. The ternary GeSiSn system eliminates one of the major limitations of SiGe/Si by decoupling strain and bandgap. This may lead to new families of devices including quantum cascade lasers and high-efficiency solar cells based on hybrid group IV/III-V designs. The latest advances in low-temperature CVD of SiGe/Si, Ge/Si, GeSn/Si, GeSiSn/GeSn/Si and GeSiSn/Ge/Si materials are described and key developments leading to practical device fabrication are emphasized. This includes selective growth via novel epitaxy and practical doping protocols via designer molecular sources to achieve carrier concentrations n, p > 1019 cm-3 for which alloy scattering to the electron and hole mobilities is very small. As an example of a GeSn/GeSiSn prototype device the fabrication of a simple photoconductor at 1.55 μm is presented.

We demonstrate a promising approach for the monolithic integration of Ge-based nanoelectronics and nanophotonics with Silicon: the selective deposition of Ge on Si by Multiple Hydrogen Annealing for Heteroepitaxy (MHAH). Very high quality Ge layers can be selectively integrated on Si CMOS platform with this technique. We confirm the reduction of dislocation density in Ge layers using AFM surface morphology study. In addition, in situ doping of Ge layers is achieved and MOS capacitor structures are studied.

Ge selective epitaxial growth (SEG) in shallow trench isolated windows is of great interest in advanced devices due to the good lateral electrical isolation of shallow trenches and the possibility of integrating Ge on Si wafers. However, the high density of threading dislocations in strain-relaxed Ge layers and facet formation are two major concerns in Ge SEG. In this work, we have obtained facet-free growth of Ge in shallow trench isolated Si windows with a threading dislocation density (TDD) of 4.2×108 cm-2. A mass transport model is developed to simulate the Ge faceting and the factors influencing the Ge deposition selectivity are studied.

The goal of this work is to study and optimize the growth parameters for Ge-on-Si for photodiodes operating at 1.55 um. Approximately 1 um-thick, relaxed Ge is grown in exposed Si regions on oxide-patterned Si wafers. Germanium selectivity, faceting, morphology, and threading dislocation density are investigated as a function of growth and processing conditions. Ge faceting was reduced by increasing the growth temperature and germane partial pressure, and at the optimized growth condition of 750{degree sign}C and 10T, an RMS surface roughness of 1.3 nm was obtained for 10 x 10 um AFM scans. Threading dislocation density was reduced for structures smaller than 5 um, but the dislocation density depends on post-growth annealing conditions and Ge film thickness.

We discuss the physics and device structures of optical modulators using germanium quantum wells grown on silicon substrates. These exploit the recently discovered strong electroabsorption mechanism in such wells, and promise high performance optical modulators on silicon.

Different silicon optical microcavities with Ge self-assembled quantum dots are fabricated and characterized. Room-temperature microphotoluminescence measurements show that strong resonant light emission from Ge dots in the cavities dominate the spectra and the photoluminescence intensity is significantly enhanced by the optical resonance in the cavity. Control of the wavelengths of resonant peaks is demonstrated by tuning the lattice constant of photonic crystal structures. A quality factor around 3000 of the resonant peak is achieved by microring resonators with Ge self-assembled dots.

Si/SiGe bound-to-continuum quantum cascade emitters designed by self-consistent 6-band k.p modeling and grown by low energy plasma enhanced chemical vapour deposition are presented demonstrating electroluminescence between 1.5 and 3 THz. The electroluminescence is Stark shifted by an electric field and demonstrates polarized emission consistent with the design. Transmission electron microscopy and x-ray diffraction are also presented to characterize the thick heterolayer structure.

The optical property was studied for the Si0.8Ge0.2/Si strained multiple quantum-well (MQW) structure grown by using ultra high vacuum chemical vapor deposition (UHV-CVD). The structural properties of the Si0.8Ge0.2/Si strained MQW were investigated using high-resolution X-ray diffraction (HR-XRD). The photocurrent spectrum of a Si0.8Ge0.2/Si strained MQW was measured at the room-temperature and the liquid-nitrogen temperature. For Si0.8Ge0.2/Si strained MQW, the transition peaks related to the MQW region observed in the photocurrent spectrum were preliminarily assigned to electron-heavy hole (e-hh) and electron-light hole (e-lh) fundamental excitionic transitions.

Thin film Ge on Si is a potential active material candidate for electrically pumped monolithically integrated Si-based light emitters. Theoretical analysis has shown that a combination of strain and n-type doping can modify the band structure of Ge so that it exhibits direct bandgap properties. Direct band-to- band optical transition is observed from the room temperature photoluminescence at around 1550nm. An optical bleaching ef- fect occurring in lock-in pump-probe measurements indicates a precursor to optical net gain.

High Ge content SiGe alloys or pure Ge are essential components of future microelectronics (high performance p-channels) and optoelectronics/microelectronics (on-chip and chip to chip communication) integration scenarios. The successful integration with Si based circuits requires process compatibility. Here we report specifically on recent results with high n and p doping of Ge and contact formation with Al and silicide/germanide metals. Highly Sb and B doped epitaxial layers (/cm3) are grown at low temperatures (< 400oC) and complete electrical activation of dopants is proven by SIMS and TLM measurements. Metal contacts on p-Ge are easily fabricated as Ohmic ones, whereas n-Ge contacts are more critical. We explain this by the Fermi level pinning near the valence band, and the strong influence of thin interface layers on the strength of Fermi level pinning.

We have found a phenomenon that the metal is heated up to 1150° by exposure to the hydrogen microwave plasma. It is thought that the heating is caused by the relief of the binding energy when the hydrogen atoms recombine and make molecules on the metal surface. For device application, Ni was deposited on a source area of a FET, and the activation of the implanted atoms and poly-crystallization of the channel area were performed at the same time by using this method, and the fabricated TFT shows good I-V characteristics.

In this work, we present very low temperature boron activation technique in amorphous (α)-Ge using Ni-induced crystallization. Ni not only successfully crystallize α-Ge film, it also facilitates activation of the respective boron atoms in the α-Ge during the crystallization process at temperatures as low as 360ºC. The feasibility of the low temperature activation technique has successfully been demonstrated for a Ge gate electrode in a Si P-MOSFET using Schottky Ni silicide source/drain.

Photoluminescence of strained Si1-x-yGexCy alloy layer and Si1-x-yGexCy /Si1-xGex structures selectively grown by RT-CVD is investigated. Spectroscopic PL at low temperature (14K) and integrated PL at room temperature were performed. We report the effect of C atoms on SiGe photoluminescence spectra features, especially intensity ratio between the no-phonon (NP) and transverse-optical (TO) transitions. Using dedicated Si1-x-yGexCy /Si1-xGex structures, influence on SiGe PL spectra of C atoms supposed in non-substitutional positions is reported.

We present a novel approach to pattern aggressive aspect ratio Si/Si1-xGex superlattices on Silicon On Insulator (SOI) wafers. This approach is based on the anisotropic etching of Si/SiGe superlattices with final dimensions down to 30nm, and the isotropic etching of the SiGe selectively to silicon. This isotropic etching was developed in a remote plasma chamber, and in-situ in an Inductive Coupled Plasma (ICP) reactor.

Spin transport in semiconductors holds promise for beyond-CMOS logic processing because the orientation of spin (coupled to the electron's intrinsic magnetic moment) can encode a binary state. However, the experimental difficulties of achieving coherent spin-polarized electron transport in the most prevalent semiconductor, Silicon, were overcome for the first time only recently. I will present our solution to this long-standing problem, including observations of exceptionally long spin lifetimes and transit lengths, which confirms Silicon's status as the ideal semiconductor for spintronics.

The paper presents a novel preparation technique for Si- and Ge-based half-metallic full-Heusler alloy thin films, utilizing silicon-on-insulator (SOI) and germanium-on-insulator (GOI) substrates, respectively. Full-Heusler Co2FeSi (Co2FeGe) alloy thin films were successfully formed by thermally activated silicidation (germanidation) reaction between an ultra-thin SOI (GOI) layer and Co/Fe layers deposited on it. This technique can easily produce fully ordered L21 structure that is necessary for the half-metallicity of full-Heusler alloys. The proposed technique is compatible with metal source/drain formation process in advanced CMOS technology and would be applicable to the fabrication of the half-metallic source/drain of MOSFET type of spin transistors.

Ferromagnetic semiconductor Ge1-xFex thin films were grown on Si(001) substrates by low-temperature molecular beam epitaxy. The crystal structure of the Ge1-xFex films was of diamond type for 0 {less than or equal to} x {less than or equal to} 17.5%. Magnetic circular dichroism (MCD) characterizations revealed that the origin of the ferromagnetic ordering in the Ge1-xFex films comes only from the diamond lattice phase with the cooperation of s,p-d exchange interactions. The Ge1-xFex films clearly exhibited the anomalous Hall effect at lower temperatures, and their ferromagnetic behavior was consistent with the results of the MCD observations. As the Fe content increased, the resistivity of the film monotonically decreased and simultaneously the Curie temperature monotonically increased. All the experimental results indicate that the Ge1-xFex films grown on Si(001) have the properties of intrinsic ferromagnetic semiconductor.

For conventional MOSFETs band-to-band tunnelling has to be avoided because it causes unintentional leakage currents. On the other hand the Tunnel FET, which basically consists of a gated pin-diode, takes advantage of tunnelling. The influence of technological parameters on device performance as well as scaling rules will be discussed. Finally it will be shown that band gap engineering with SiGe and the incorporation of high-k dielectrics strongly improve current slope and maximum ON current. A future device performance comparable or even better than the conventional MOSFET is predicted.

We report for the first successful electrodeposition of highly pure SixGe1-x from the air- and water stable ionic liquid 1-butyl-1-methylpyrrolidinium bis(trifluoromethylsulfonyl)amide ([Py1,4]Tf2N) containing GeCl4 and SiCl4 as precursors. The electrodeposition is investigated by cyclic voltammetry and high resolution scanning electron microscopy. SixGe1-x can be deposited reproducibly and easily in this ionic liquid. Interestingly, the SixGe1-x deposit showed a strong colour change (from red to blue) at room temperature during electrodeposition. The observed colours are strong hints for band gaps between at least 1.5 and 3.2 eV, which are indicative of a quantum size effect. This proves the potential of ionic liquids in the electrodeposition of high quality SixGe1-x.

We present both experimental results and a compact model on nanoscale thermal transport in the vicinity of a hot spot in silicon. Effective-local-temperature measurements on the nanoscale are influenced by localized heating effect and a thermal interface resistance, as well as by the spreading resistance in silicon. Ballistic phonon transport is observed for nanoheaters where the interface thermal resistance contribution can be minimized. Thermoelectricity in silicon nanostructures is investigated as a possible route to convert thermal energy into electricity.

We describe the formation of a ferromagnetic Fe-rich germanide layer by a two-step process involving magnetron sputtering and anneal. A thin epitaxial iron (epi-Fe) film is deposited on Ge (001) substrate and then annealed at 275 oC in nitrogen inducing germanide formation. Surprisingly, we observe an enhancement in saturation magnetization in germanide films. Secondary ion mass spectroscopy and x-ray diffraction confirm the formation of a thin Fe-rich germanide layer whilst high resolution transmission suggest that it can be Fe3Ge.

In this paper we demonstrate the successful integration of in-situ doped embedded Si:C stressors epitaxially grown in the source and drain areas of nMOS devices using a novel Cyclic Deposition Etch (CDE) process. These layers have substitutional C content ranging between 1% and 2% with potential of achieving even higher substitutional carbon concentration. Another distinctive feature of this process is that it allows for high in-situ P doping for ease of integration within a CMOS platform. We demonstrate superior performance of strained nMOS devices with embedded Si:C showing up to 12.5% on-state current improvement over the unstrained reference process. We report on material characterization results of embedded Si:C stressors, in particular, strain retention properties as a function of subsequent post-epitaxy processing.

We summarize our work on creating substrate platforms, processes, and devices for the monolithic integration of silicon CMOS circuits with III-V optical and electronic devices. Visible LEDs and InP HBTs have been integrated on silicon materials platforms that lend themselves to process integration within silicon fabrication facilities. We also summarize research on tensile Ge, which could be a high mobility material for III-V MOS, and research on an in-situ MOCVD Al2O3/GaAs process for III-V MOS.

The influence of P diffusion on the thermal stability of epitaxial Si:C films has been studied. P diffusion is shown to greatly contribute to the strain loss in epitaxial Si:C films. It is proposed that the strain loss is mainly caused by the interaction of Si interstitial atoms injected by P diffusion with substitutional C atoms, driving them to non-substitutional lattice sites.

Passivation of Ge has been a critical issue for Ge MOS applications in future technology nodes. In this work, we introduce ozone-oxidation and low temperature plasma nitridation to engineer Ge/insulator interface. Density of interface states (Dit) across the bandgap and close to conduction band edge was extracted using conductance technique at low temperatures. Electrical qualities of Ge-GeO2 and Ge-GeON interfaces are investigated. Thermal stabilities and desorption pathways of those passivation techniques are investigated through Ge 3d spectra measurements. Low Dit advantage of ozone-oxidation technique is combined with thermal stability provided by plasma nitridation.

This paper reports on the Solid Phase Epitaxial Regrowth (SPER) of phosphorus implanted pre-amorphized p-type germanium at 350 oC using Rapid Thermal Annealing and focuses more specifically on the P concentration dependence of the regrowth velocity. This is studied by a combination of Rutherford Backscattering in the channeling mode (RBS-C) and Secondary Ion Mass Spectrometry (SIMS). As will be shown, different regimes can be distinguished whereby for chemical concentrations up to 4-5x1020 cm-3 an enhanced recrystallization occurs compared with undoped amorphized Ge. Above this metastable solid solubility limit, the regrowth is retarded, due to the redistribution and snow plow of the excess P across the amorphous/crystalline interface. It will also be demonstrated that during SPER at 350 oC, limited P-diffusion occurs even at the highest implantation dose studied.

The introduction of automotive radar sensors operating in the 76-81 GHz frequency range is a very promising application for SiGe:C HBT technologies. In this work, the performance of the critical mm-wave circuits has been benchmarked showing the suitability of SiGe:C HBT circuits as competitors to the III-V compound semiconductor circuits available in the first generation radar sensors. Additionally, because of the strong interest of the automotive industry on reliable sensor operation between -40oC and up to +85oC the temperature stability of the radar oscillator and the reliability of the SiGe:C HBTs will be discussed.

We describe a 0.35 micron SiGe BiCMOS technology that is optimized for power amplifier (PA) applications. The key feature of this technology is a novel low inductance ground to the package by method of through-silicon-via (TSV), offering a competitive solution for future multi-band / multi-mode PA integration. The tungsten filled, multi-finger, bar shaped TSV delivers over 75% reduction in inductance compared to a traditional wire bond, enabling higher frequency applications with roughly 20% die area reduction, and without compromising the technology reliability for use conditions in a low-cost plastic QFN package. In this paper we demonstrate the commercial feasibility of the TSV, its RF performance, and its usefulness in a demanding WiMAX PA application.

A comparison of electrical performances of state-of-the-art SiGe heterojunction bipolar transistors at low temperature is presented. The performances increase results from the diminution of transit times thanks to the rise of non-stationary transport, the relative increase of the transconductance with the reduction of self-heating effects, and the decrease of access resistances.

The regional transit time analysis technique is extended from 1-D to 3-D and used to investigate the AC performance of a SiGe HBT-on-SOI fabricated with a novel contact layout. As confirmed by TCAD simulations, the relocation of the base contacts out-of-plane with respect to the emitter and the collector results in a true 3-D current flow. Consequently, AC analysis and optimization cannot be performed with conventional 1-D regional transit time analysis.

A high-precision RT-CVD epitaxial growth technique has been successfully developed for fabricating ultra-low-power SiGe HBTs. Extremely high-concentration doping with abrupt profiles in the Si/SiGe layers was achieved without high-temperature activation annealing. Furthermore, good crystallinity of the grown layer was also achieved, which results in low resistivity. A major advantage of the technique is that SiGe HBTs fabricated using it have high cutoff frequencies at low current density (50 GHz at JC = 0.2 mA/μm2), which makes them highly suitable devices for use in future low-power high-speed communication systems.