Table of contents

The UV light densitometer was developed to measure concentration of gases having absorption in the ultraviolet region using UV absorption method. The developed densitometer was applied to monitor temporal variation of concentration of ALD precursor TEMAZ introduced into a chamber, where TEMAZ was introduced alternately with purge Ar gas to simulate ALD process. We could successfully capture temporal variation of gas concentration such as time delay in arrival of gas in the chamber due to presence of gas flow. Such phenomenon cannot be measured by the pressure gauge.

The directed self-assembly (DSA) of block copolymers (BCPs) can be used to produce nanoscale patterns without the cost and process complexity of state-of-the-art optical lithography. Thus, DSA may be useful in a wide variety of semiconductor applications such as fin field-effect transistors and biosensors. To create technologically useful patterns with aligned BCP domains, conventional DSA mechanisms often rely on topographically complex structures or high-resolution chemical patterns to direct the self-assembly, that are difficult to fabricate. In comparison, a newly discovered mechanism for DSA, termed boundary-directed epitaxy (BDE), utilizes chemical contrast at the boundaries between a substrate and relatively wide chemical stripe. Here, we demonstrate the use of BDE to template the fabrication of sub-10 nm features for the first time. BDE is used in conjunction with selective infiltration to create ultranarrow line-space arrays of alumina. These results demonstrate a proof-of-concept for BDE as a method for ultrahigh-resolution feature formation.

It will be shown that nanogaps can be fabricated by selective etching of fully strained SiGe layers embedded in single crystalline silicon. It will be shown that intrinsic stress is the dominating parameter for the anisotropy. High temperature etching with gaseous hydrochloric acid allows a large etch selectivity RSiGe/RSi depending on surface orientation, Ge concentration and temperature during etching. Multilayer nanogaps have been prepared and completely filled by several deposition techniques. Applications regarding diodes and MOSFETs will be given.

This paper reviews the low-temperature and low-pressure thermal polymerization of dielectric polyimides that are used for redistribution layers (RDLs). Specifically, this presentation illustrates the significant impact of the low-pressure cure process in reducing cure temperature (by 20° to 50°C) and cure times (by as much as 25%) while providing better imidization ratio, film stress, mechanical (elongation %, tensile strength, Young's modulus), thermal (Tg, Td5%, CTE), and electrical (Dk, Df) properties for different types of dielectric polyimides. Among the many low-temperature polyimides we have studied, we focus here on the Fujifilm LTC-9300 series (LTC-9310 and LTC-9320) and the Asahi BL-300 series. The excellent post-curing polymerization ratio (as measured by FT-IR) and film stress results are also described. Finally, a proposed mechanism for these dielectric polyimides' polymerization under reduced pressure is discussed.

This work focuses on the manufacturing of Al/AlO_x/Al Josephson junctions (JJs), which are essential components of many quantum circuits. Two processes were studied to understand the oxidation of the aluminum surface. Static oxidation was performed by removing native AlO_x in a cluster system with Ar-ion beam milling and controlling the final tunneling oxide by applying a specific O₂ pressure in the chamber. Controlled plasma oxidation was performed by removing native AlO_x with a H₂ plasma followed by a defined reoxidation with an oxygen plasma. The resulting oxides had thicknesses up to 10 nm and their electrical properties were analyzed on wafer level, providing insight into the structure and composition of the aluminum oxides and their applicability for Qubits. This work is crucial for reliable industrial manufacturing on full-scale 200 mm wafers with a very high uniformity level.

We are growing at CEA (i) high purity ²⁸Si layers and (ii) c-Ge/SiGe heterostructures for electron and hole spin quantum bits. We describe here strategies usable for the fabrication of ²⁸SOI substrates, with a focus on ²⁸SiH₄ consumption minimization, as such a gas is very expensive and hard to come by. We also focus on the properties of Si_0.26Ge_0.74 and Si_0.21Ge_0.79 Virtual Substrates (VS) grown at 850°C, 20 Torr and a forward Ge ramping-up on Si(001) substrates. After some chemical polishing (to remove the surface cross-hatch), those VS are used as templates for the 500°C, 100 Torr growth of SiGe/c-Ge/SiGe 2D Hole Gas Gas (2DHG) stacks. Those c-Ge layers are, in X-Ray Diffraction, fully compressively strained on the relaxed SiGe VS underneath and of high crystalline quality. Some slight undulations are evidenced at c-Ge / SiGe cap interfaces, hinting at elastic strain relaxation, however. Magnetotransport measurements in Hall-bar devices were performed at 4.2 K to assess the electrical properties of the 2DHG in those SiGe/c-Ge heterostructures. At low magnetic field, a hole mobility of 1.2 x 10⁵ cm² V^-1 s^-1 was obtained for a hole density of n_2DHG = 3.7x10¹¹ cm^-2 in a 16 nm thick c-Ge/55 nm thick Si_0.21Ge_0.79 cap sample.

In this work, after X-ray and electron irradiation, the outcomes of the evaluation dynamic characteristics of interstitial atoms Si_j, vacancy V, and O-complexes were evaluated to account for the annealing conditions to derive specific structural defects in the SiO₂/Si wafer. A non-destructive method, which allows the determination of the internal friction difference ΔQ^-1/Q^-1₀ of the elastic vibration structure defect density N_d and the depth of the broken layer h_b, is offered for the SiO₂/Si wafer. The method was developed, the installation was designed and manufactured for the excitation and registration of damped bending resonant oscillations in a SiO₂/Si disc-shaped wafer with a thickness h_SiO2 ≈ 100 nm, h_is = 300÷500×10³ nm, and diameter D = 60÷100×10^-3 m to measure the structurally sensitive internal friction Q^-1. Measurement of the internal friction background Q^-1₀ at harmonic frequencies f₀ and f₂ allowed us to experimentally determine the nodal lines of the oscillating disks.

The search for alternatives to Si in the VLSI technology is based on experimental and theoretical work. Here, we consider only the latter and, looking at a few two-dimensional materials of current interest, we use them as examples to emphasize the difficulties faced by theorists in assessing their potential: Silicene and germanene are examples of materials whose properties suffer from the strong scattering of electrons with flexural acoustic phonons; phosphorene highlights how small inaccuracies of ab initio methods prevent a reliable assessment of transport properties; finally, we consider transition metal dichalcogenides to show how surrounding dielectrics (the substrate and/or a top-gate insulator) depress significantly the carrier mobility and the performance of devices that use these materials as channels.

Transient behavior of metal-insulator-semiconductor tunnel diode (MISTD) with ultra-thin metal surrounded gate (UTMSG) is discussed in this work. The influence of an important parameter, S, which is the area proportion of surrounding gate to the total gate, on the transient read current and transient capacitance window is demonstrated. Transient current is found to be larger for larger S due to more significant edge late response. By taking advantage of the unusual capacitance-voltage characteristics, improved capacitance window could be achieved. The transient current window and capacitance window of UTMSG device with S = 0.66 have been found to be 17x and 14x larger compared with planar device.

In this work, the impact of outer oxide charges on the electrostatics of metal-insulator-semiconductor tunnel diodes (MISTD) is discussed. The existence of outer oxide charges will significantly affect the critical voltage V_c of MISTD in the strong inversion region. At the bias voltage of V < V_c, the MISTD works like a traditional metal-oxide-semiconductor (MOS) capacitor. However, at the bias voltage of V > V_c, the MISTD goes to deep depletion. V_c is an important boundary for the electrostatics behavior of MISTD. We propose a model, considering the existing outer oxide charges, to calculate V_c and compare the calculated results with V_c extracted from our devices. V_c of our devices is extracted by measuring high-frequency capacitance-voltage (HFCV) at 300 kHz. It is found that the model is able to fit well with the experimental results when the amount of outer oxide charges is in the magnitude of 2.5×10¹¹ cm^-2 for our devices. The model is fundamental but helpful for analyzing and designing a MISTD.

The power amplifier (PA) in an RF front-end module operating above 100 GHz required for 6G wireless networks is the most power-hungry device circuit component. In that respect, InP-based heterojunction bipolar transistors (HBT) clearly outperform other PA technologies, but being processed on small size wafers, they lack a cost-effective fabrication for mass production. This paper presents a comprehensive comparison of various integration approaches for InP-based HBTs. A key aspect in achieving high yield device fabrication is the use of large-diameter silicon wafers. This study discusses the advantages and disadvantages of different InP-based HBT integration concepts on Si, emphasizing important factors for upscaling InP technologies. Furthermore, this work introduces nano-ridge engineering (NRE), a novel monolithic III-V integration approach currently being explored at imec, which holds the potential for cost-effective and complementary metal oxide semiconductor (CMOS)-compatible production.

This work covers integration of advanced III-V semiconductors on silicon substrate for RF-sensor integration up to very high frequencies of 300 GHz and 670 GHz, respectively, including improved active device performance through intelligent engineering of the co-integrated buffer layers. Several Terahertz Monolithically-Integrated Circuits are presented, which demonstrate good gain performance, low-noise, and improve large-signal behavior through the application of the back-gate.

This paper reviews our experimental studies on the resistive switching behaviors of sputter-deposited Si oxide films. Theoretical simulations are also demonstrated to elucidate the physical mechanisms of resistive switching behaviors. These suggest the various potential applications for low-energy sensor network systems, neuromorphic computing systems and low-cost commercial electronic systems.

This work presents for the first time the use of dual aluminum contacts (DAC) to improve the performance of reconfigurable field effect transistors (RFET), integrating two aluminum contact in ^BESOI MOSFET (with and without annealing process). Using TCAD simulations, the charge density in the channel region below the aluminum source contact depends on the channel thickness and bias in the programming gate. This thickness making possible to create a hole's channel below the Schottky aluminum contact for silicon thickness below the aluminum contacts higher than 30nm, enabling conduction in the dual aluminum contact transistor. The DAC ^BESOI MOSFET had a current level increase of 3 times for ^BESOI pMOSFET and 9 times in ^BESOI nMOSFET compared to using NiSi contacts

In the current study, two-dimensional pyrite thin films were produced on various substrates using a plasma-assisted, radio frequency (RF)-powered sputtering process. The photosensitivity of pyrite thin films with varying thicknesses was investigated. The sputtering process was carried out at room temperature under argon gas flow. The pressure was maintained at 3 mTorrs, and the RF power was held at 70 watts. The thickness was adjusted by changing the sputtering time from 20 to 90 minutes. The purpose of this work was to investigate the suitability of these films for use in photovoltaic applications. The growth rate, film thickness, and behaviour of as-grown pyrite thin films were analyzed using various characterization techniques. These films displayed favourable absorption in the UV/Vis range.

We present an overview of the performances of FDSOI CMOS transistors down to deep cryogenic temperature, highlighting in particular the benefits brought by the back bias. FDSOI transistors are operational from room temperature down to temperature as low as 100mK. The main DC electrical characteristics, as well as variability properties and reliability are measured and analyzed. We also point out specific behaviors appearing at cryogenic temperature, and discuss their physical origin and modeling.

The manuscript performs a review of the differentiated new layout styles for the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) that can boost their electrical performance and ionizing radiation tolerance. Firstly, we present the elements of the first generation of layout styles, the effects intrinsic to their structures, and the first-order analytical models of their drain current. After, we study the first element of the second generation of layout styles, which presents a hybrid gate geometry, aiming mainly to further reduce its effective channel length in comparison to those reached by the first generation and consequently further boosting the electrical performance of the analog MOSFETs. The experimental results in room temperature and high temperature found to show that the first element of the second generation can be considered an alternative hardness-by-design to improve the electrical performance and ionizing radiation of the analog MOSFETs.

We compute the spin torque acting on elongated magnetic layers inrecently proposed ultra-scaled STT-MRAM devices. For thispurpose we evaluate the non-equilibrium spin accumulation bysolving the coupled spin and charge transport equations. This goesbeyond the Slonczewski torque approximation which describestorques localized at the interface of the tunnel barrier and themagnetic free layer as well as the Zhang-Li torque approximationmodeling the torque acting on a magnetic texture (a domain wall)in the layer's bulk. We show that the torque contributions frominterface and bulk are not independent from each other and ourgeneralized approach is necessary to accurately model the torquein the presence of a magnetic domain wall inside the magnetic freelayer. We implemented a numerical solution of the spin and chargetransport equations in a finite element-based framework.

In this work, we investigate solution processable MoS₂ based MOS (metal oxide semiconductor) capacitor device for data storage and in-memory light sensing. The MOS capacitor exhibits a good memory window of about 2.5 V with the operating voltage of +6/-6 V and good endurance of 1000 cycles without any degradation. The device shows a good memory window from 0.4 V to 5 V when the operating voltage was varied from 4/-4 to 8/-8. Importantly, the memory window of the device was increased from 2.5 V to more than 5 V when optical light with different wavelengths was induced onto the device. These promising features of the device make it suitable for data storage and in-memory light sensing.

Operational Transconductance Amplifier (OTA) designed with Omega-gate Nanowire SOI MOSFETs was evaluated. The transistor model was created using Verilog-A language and a Look-Up Table strategy, which is based on very precise measurements of the fabricated device. For the model, both the current and capacitance responses were considered. The proposed OTA showed a very good results with a voltage gain of 69.5 dB and a gain–bandwidth product (GBW) of 724 MHz. After that, a comparison among OTAs using different technologies was performed, showing that although the OTA designed with omega gate nanowire does not reach the same voltage gain of one designed with nanosheets, the proposed OTA shows a better GBW and smaller compensation capacitor for the same load capacitance. Considering the complexity of the nanosheet manufacture and the cost, the OTA designed with W-gate nanowire appears as a promising solution to replace FinFETs in the future.

In this work, an in-depth static and low frequency noise characterization of nanosheet FETs, consisting of two vertically stacked silicon channels per device, is performed. A comparison of the performances from n- versus p-channel FETs operated at 300 K and 78 K, in terms of static and low frequency noise parameters variability, is also discussed. The main electrical parameters are estimated from the I-V characteristics using access resistance robust methodologies. An additional criterion demonstrating that the extracted parameters are not influenced by the second mobility attenuation factor is proposed. The low frequency noise studies prove that the dominant flicker noise mechanism is linked to correlated carrier number and mobility fluctuations, with additional access resistances noise contribution in very strong inversion. The importance of the considered total flicker noise model on the estimation of the Coulomb scattering coefficient is highlighted.

In the era of emerging computing paradigms and artificial neural networks, hardware and functionality requirements are in the surge. In order to meet low power and latency criteria, new architectures for in-memory computing are being explored as alternatives to traditional von Neumann machines, which requires technological breakthrough at the semiconductor device level such as vertical gate-all-around junctionless nanowire field effect transistors (VNWFET), that can address many process challenges such as downscaling, short-channel effects, compactness and electrostatic control. Its integration in the mainstream design flow is not straightforward and requires design technology co-optimization (DTCO) at an early stage. This invited paper explores strategies for accurate characterization and parameter extraction of the VNWFETs to feed the compact models allowing DTCO-efficient strategies.

At present, silicon very large-scale integration has reached channel thicknesses of 7 nm. However, further scaling is becoming increasingly challenging as the gate electrostatics requires a significant reduction in channel thickness to about a fourth of the gate length. Consequently, the gate length of high-performance field-effect transistors is 16 nm at the state-of-the-art, and it is projected to stall at 12 nm for the 1.5 nm node and the following nodes, according to the International Roadmap for Devices and Systems. At these nodes, two-dimensional materials could potentially replace silicon as the channel material as they maintain sizable mobilities at atomic thicknesses, providing improved gate control in stacked channel nanosheet transistors. However,there are several challenges to overcome for FETs based on 2D mate-rials to serve as the front-end devices in VLSI circuits.

In this work, the transient current behavior of metal-insulator-semiconductor tunnel diode (MISTD) with oxide removal at the gate edge has been investigated. With an oxide-removed structure at the gate edge, the edge-removed (ER) MISTD not only exhibits reduced reverse bias current but also demonstrates enhanced transient current compared to conventional co-planar MISTD. These improved characteristics of ER MISTD can be attributed to the absence of oxide charges outside the gate edge and the insufficient supply of minority carriers. We also proposed a two-state transient current operation and tested the device's endurance. Finally, we examined the relationship between oxide thickness and the current window and found that the current window is maximum when EOT is around 3.1 nm. Based on these properties, edge-removed MISTD shows potential as a dynamic transient memory device.

High read throughput single-molecule sensing is a cornerstone of established third generation long-read DNA sequencing technologies and is crucial for emerging protein sequencing technologies. These omics technologies are of great interest for essential understanding and applications in the life sciences. Field Effect Transistor (FET)-based single-molecule sensors promise advances in omics, by further enhancing read throughput with massive parallelization. Here an overview is given of our recent progress on nanoscale bioFETs and nanopore FETs (NPFETs).

In this work, we presented a novel simulation tool called the Biomolecule-Oxide Simulator (BOxSim) and its application in simulating the behavior of BioFETs. The capabilities of BOxSim are shown by investigating the impact of various high-k dielectric materials on important Figures of Merits such as current in the channel of the device, surface potential, sensitivity, and intrinsic buffer capacitance. The capabilities of our BOxSim framework allow us to discover new features in the variation of differential capacitance with respect to the second gradient of drain current and surface potential. The profile of the surface potential is used to uniquely identify the signatures (fingerprints) of amphoteric molecules like acids or peptides. The proposed model prospects the possibility to develop an efficient method for protein sequencing. The reliability of the designed model is confirmed by calibrating the simulated results with experimental data for different physical conditions. The results presented in this paper demonstrate the potential of this framework for advancing the field of biosensors and bioelectronics for the biorecognition of different molecules.

This review presents the technological evolution of devices based on Ion Sensitive Field Effect Transistors (ISFETs), which try to go along with the Metal Oxide Semiconductor FET (MOSFET) technology. Furthermore, many examples of the applications as chemical or biological sensors with different structures (planar or 3D), conduction channels (Silicon or Graphene), and dielectric gate films (SiNx, TiOx, TaOx, and AlOx) will be discussed.

Our research group has proposed the measurement concept of multimodal sensing, in which sensors with broad detection characteristics are used to realize the sensing of multiple items, and has developed semiconductor CMOS-based sensors to realize this concept. In this talk, we introduce ion image sensors and odor sensors as examples of CMOS-based sensors suitable for multimodal sensing, and data analysis using machine learning, which is important for this measurement concept will be mentioned and introduce an example of machine learning-based sensing. The application of these sensors to smart agriculture and other fields will also be discussed, as well as the current status and issues for the practical application of sensor systems.

This paper presents, for the first time, the ^BESOI MOSFET working as Ion Sensitive Field Effect Transistor (ISFET): the ^BESOI ISFET. Experimental measurements were performed with standard pH solution replacing the gate electrode. The threshold voltage becomes lower when the pH decreases (changes from basic to acid) as expected. Furthermore, the back (substrate) bias influence was studied, showing an increase in the device sensitivity (mV/pH) as a function of the back voltage. The best sensitivity value was obtained for 30 V applied in the back bias, reaching 33 mV/pH. These results demonstrates that the ^BESOI ISFET has electrical behavior compatible with other ISFETs.

This work faces the use of graphene liquid-gate transistors as sensors. Before dealing with a functionalized surface and biological targets, achieving a reliable sensing platform within this novel material as an active channel, fabrication, lithography, and reliability have to be extensively evaluated. In this work, we have analyzed the inter-device variability and the reliability of the sensors together with the phenomena which can increase these issues under operative conditions. High quality material corroboration has been evaluated through structural characterization (optical, XPS and Raman). Then photolithography and processing for liquid-gate sensor have been performed. Finally, electrical evaluation of the devices has been carried out demonstrating reliability issues and considerable inter-device variability. We propose in this work the use of integrate-coupling effect (front and back-gate simultaneously) to alleviate the inter-device variability and reliability problems.

This work compares the Drain-Induced Barrier Lowering (DIBL) effect in SOI nanowire transistors. The fin width, length, and temperature influence are experimentally evaluated for junctionless (JL) and inversion mode (IM) nanowire transistors. The results show that DIBL degradation with length reduction is more pronounced in IM nanowires. Although the DIBL might be higher on JL nanowires, its temperature variation has been reduced compared to IM devices.

In this work, the Metal-Insulator-Semiconductor High Electron Mobility Transistor (MIS-HEMT) behavior in saturation region was analyzed and compared with a GaN MOSFET. The MIS-HEMT presents a current level about 30 times higher than GaN MOSFET, for the same bias conditions. The different saturation points (V_{DS sat}) of the MOS and HEMT conductions is responsible for the appearance of a kink in the drain current (I_DS) current as a function of drain voltage (V_DS) curve. The output conductance (g_D) of the MOSFET presented a strong dependence on V_GT, while the MIS-HEMT only a slightly dependence was observed. The MIS-HEMT kink effect (MH kink) was defined by the drain voltage where the bump occurs. The MH kink only occurs for a high enough gate bias to enable the MOS conduction, and MH kink value increases with the gate voltage overdrive (V_GT) and its variation tends to saturate for V_GT higher than 3,5V.