Table of contents

Dopant concentrations higher than 1x10¹⁹ cm^-3 are required to improve the performances of various GeSn based devices such as photodetectors, electrically pumped lasers and so on. In this study, the in-situ Boron and Phosphorous doping of SiGeSn was investigated, building upon recent studies on in-situ B or P doped GeSn. The surfaces of intrinsic and lowly doped pseudomorphic SiGeSn layers were rough. By contrast, a <110> cross hatch was recovered and surfaces as smooth as the Ge Strain-Relaxed Buffers underneath were obtained for the highest B₂H₆ or PH₃ mass-flows. The surface Root Mean Square roughness and Z_range values were then as low as 0.36 nm and 2.86 nm for SiGeSn:B, and 0.47 nm and 4.60 nm for SiGeSn:P. In addition, Si contents as high as 25% were obtained, notably in SiGeSn:B layers. Dopants were almost fully electrically active in those SiGeSn:B and SiGeSn:P layers, with carrier concentrations as high as 2.0x10²⁰ cm^-3 and 2.7x10²⁰ cm^-3, respectively. For SiGeSn:P, the shortcoming of in-situ doped GeSn:P was overcome, that is the formation of electrically inactive Sn_mP_nV clusters for high PH₃ mass-flows. Such electrically active carrier concentrations will be beneficial for (Si)GeSn based devices, but also for all Group-IV based devices with extremely low thermal budget constraints.

We demonstrate waveguide coupled germanium fin p-i-n photodiode being on a par with state-of-the-art III-V devices. The intrinsic, undoped germanium regions of the photodiodes are sandwiched in between two complementary in situ-doped silicon regions, circumventing ion-implantation into Ge. By scaling the width of the germanium, different combinations of bandwidths and responsivities can be obtained. Optoelectrical 3-dB bandwidths reaching up to 265 GHz at (1550 nm) 1 mA photocurrent and 2 V reverse bias are shown for a device with ~100 nm narrow germanium fin. Certainly, broader germanium region will yield higher responsivities but on the expense of 3-dB bandwidths. Increase of the germanium width from 100 nm to 450 nm results in a change in internal responsivity from 0.3 A/W to 1 A/W at -2 V bias. The impact of high photocurrent on performance of our new photodiodes will be presented in this paper.

A strain-enhanced Ge layer is epitaxially grown on a bonded Si-on-quartz (SOQ) wafer and is applied to a near-infrared pin photodetector (PD) at a normal incidence. X-ray diffraction measurement reveals a tensile in-plane lattice strain of 0.33 ± 0.01% in Ge on SOQ, which is generated by the mismatch of the thermal expansion coefficients between the Ge layer and quartz substrate of SOQ. The strain is approximately two times higher than 0.14 ± 0.01% in Ge on an ordinary Si wafer. Resulting from a direct bandgap narrowing under the tensile strain, the fabricated pin PD of Ge on SOQ exhibits a responsivity enhanced in the C+L band (1.530 – 1.625 µm).

In this work we present the progress in regard to the integration of a surface plasmon resonance refractive index sensor into a CMOS compatible 200 mm wafer silicon-based technology. Our approach pursues the combination of germanium photodetectors with metallic nanohole arrays. The paper is focused on the technology development to fabricate large area photodetectors based on a modern design concept. In a first iteration we achieved a leakage current density of 82 mA/cm² at reverse bias of 0.5 V and a maximum optical responsivity of 0.103 A/W measured with TE polarized light at λ = 1310 nm and a reversed bias of 1 V. For the realization of nanohole arrays we used thin Titanium nitride (TiN) layers deposited by a sputtering process. We were able to produce very homogenous TiN layers with a thickness deviation of around 10 % and RMS of 1.413 nm for 150 nm thick TiN layers.

Since mid-infrared (MIR) wavelengths have a great potential for optical communication, sensing, and quantum information, Si-based MIR photonic integrated circuits (PICs) have been developed by leveraging Si photonics technology for near-infrared wavelengths. However, the transparency wavelength window of Si is from 1.2 μm to 8 μm, limiting the available wavelengths in the MIR spectrum. Ge is emerging as a waveguide material to overcome this difficulty because Ge is transparent in the entire MIR spectrum. We have developed a Ge-on-insulator (GeOI) platform for MIR integrated photonics. The strong optical confinement in a GeOI waveguide enables an ultracompact MIR PIC. Using wafer bonding and Smart-cut, a GeOI wafer was successfully fabricated. As a result, we have demonstrated various Ge passive devices, thermo-optic phase shifters, modulators, and photodetectors on a GeOI platform.

Extremely-thin body (ETB) nano-sheet CMOS is expected as a device structure to realize future continuous scaling. Thus, channel materials to maintain high mobility in such an ETB channel are strongly needed. It is revealed through analyses based on a new physical model of thickness fluctuation scattering that ETB GOI channels, particularly (111) GOI channels, are promising for this purpose. High-quality ETB GOI channels are formed by the Ge condensation and smart-cut technology. The operations of Ge p- and n-MOSFETs with the body thickness down to 2 nm are experimentally demonstrated and the body thickness dependencies of the effective mobility are examined. The importance of strain and surface orientation engineering on mobility in an ETB region is addressed.

The discovery of Hafnia-based ferroelectric materials made ferroelectric field-effect transistor (FeFET) a promising nonvolatile memory device and enables aggressive scaling down. However, the ferroelectric layer possesses polarization variation (PV) induced by its crystallinity, whereby FeFET suffers from performance variation. Hence, it is critical to assess its influence quantitatively to utilize the FeFET for storage or compute-in-memory applications. In this review, recent trends and progress of the performance variation on the FeFETs are surveyed. We present the impact of PV on three-dimensional (3D) FeFETs. In addition, to show its capability for compute-in-memory application, the inference accuracy is discussed under the structures. Next, the Voronoi diagram is introduced to model the different sizes and shapes of ferroelectric grains. A comparative study of the device variability with other sources is investigated under different technology nodes. Finally, a machine learning-aided methodology to analyze the variability of FeFET based on the metrology data is proposed.

We have evaluated low temperature epitaxy (LTE) of Phosphorous doped Si (Si:P) and Boron doped SiGe (SiGe:B) on Si(001) substrates. The benefit of LTE is very significant, enabling incorporation of high levels of active dopant for both p- and n-type layers. This translates into lower resistivity compared to layers grown at higher temperature. However, several challenges appear when epitaxy occurs at low temperature (e.g., <500ºC): (i) low growth rate; (ii) loss of selectivity and (iii) crystallinity degradation, particularly on non-(001) surfaces. To overcome these issues, careful selection of precursors and optimization of process conditions is required. In this work, we discuss layer properties obtained on blanket Si(001) wafers. We have also evaluated the most promising SiGe:B growth conditions on patterned nanosheet structures, where the layer was shown to be selective towards SiN and SiO₂ and crystalline growth was realized on Si(110) nanosheet sidewalls. Finally, selective process layer uniformity and wafer-to-wafer reproducibility were assessed over twenty Si(001) wafers showing excellent layer uniformity and wafer-to-wafer repeatability.

We report on selectively grown Si:P layers below 500°C targeting application in stacked nanosheet-based devices. In contrast to conventional approaches where selectivity is obtained at low temperatures using Cyclic-Deposition and Etch (CDE) with HCl/GeH₄ as an etchant, we rely for this work on Cl₂-based etching and the use of a higher order Si precursor which allows to maintain a high wafer throughput at low temperatures. We demonstrate that selective Si:P layers can be obtained with a resistivity below 0.3 mOhm.cm which can be grown selectively on fins and stacks with Si nanosheets.

Our aim was to assess the feasibility of the Low Temperature Cyclic Deposition / Etch (CDE) of tensile-Si:P for use in Raised Sources and Drains of n-type Field Effect Transistors. We were targeting high amounts of tensile strain and low resistivities in tensile Si:P layers grown at 550°C, with (i) mainstream Si₂H₆ + PH₃ gases for the non-selective deposition of t-Si:P and (ii) HCl + GeH₄ for the selective etches of poly-Si:P versus monocrystalline Si:P (to have selectivity on patterned wafers). Thanks to the use of 10 cycles CDE processes with various HCl + GeH₄ etch durations on bulk and SiN-covered Si substrates, we showed that an etching selectivity of ~6 could be expected, for a-Si:P over t-Si:P, on patterned wafers. The presence of numerous nuclei on SiN-covered substrates nominally free of any bi-dimensional a-Si:P layers was evidenced by haze measurements, however, hinting at a lower effective selectivity. We then switched over to patterned SOI wafers with gates. We succeeded, when using 7 cycles CDE processes, in having almost full selectivity with 60s depositions and 40s etches / cycle, respectively. Maybe because there was a mix of a-Si:P and t-Si:P regions on such wafers, we had almost the same deposited t-Si:P thickness / CDE cycle (4.1–4.2 nm) whatever the HCl + GeH₄ duration / cycle in the 15s–40s range. Meanwhile, there was a gradual disappearance of a-Si:P nuclei on dielectrics together with an "apparent" P concentration reduction from 4.0% down to 2.5% as that etch duration increased.

We demonstrate the feasibility of selectively growing highly doped and tensile-strained Si:P layers at temperatures 500°C or less on each side of advanced n-type MOS devices. To that end, we used a Cyclic Deposition Etch (CDE) strategy instead of a conventional "co-flow" approach fit for the high temperature (> 600°C) Selective Epitaxial Growth (SEG) of t-SiP films. A high order silicon precursor was used together with PH₃ to benefit from high t-Si:P growth rates at 500°C and less. Selective etchings were performed with Cl₂ as an etchant gas, as it yielded much higher etch rates than HCl. We first investigated the blanket growth of t-SiP on fullsheet Si wafers. 5 to 15 times higher higher growth rates than with standard precursors were obtained at low temperatures with our new HOS silicon precursor. We then investigated the etching efficiency of Cl₂, with several tens of nanometers per minutes etch rates achieved at very low temperatures. Using a CDE strategy, we then probed phosphorus incorporation in blanket t-Si:P films on fullsheet wafers. High quality and smooth t-SiP layers with up to 5.4%, 4.3% and 5.8% of P and sheet resistances as low as 0.33, 0.27 and 0.21 mohm.cm were obtained at 500°C, 475°C and 450°C, respectively. We then tested our CDE SiP process for SEG, first on test structures then on each side of real FD-SOI devices, with smooth, high quality, tensile SiP layers grown at 500°C with 4.5% of P.

Both forksheet and CFET device layouts contain local dielectric isolation layers to circumvent junction isolation trade-offs which are specific for these designs. Typical fabrication schemes start with the epitaxial growth of complicated SiGe/Si multi stacks with at least two different Ge concentrations where a Ge-rich SiGe layer is later replaced by an isolating dielectric. This work proposes a low temperature Br₂-based vapor etching process as an option for the selective SiGe removal in the isolation fabrication. After initial process screening on blanket epi layers to compare etching behavior for different process gases as function of material composition and crystallinity, it is demonstrated on patterned test structures that Br₂ etching enables high etching selectivity of Si_0.5Ge_0.5 towards Si and Si_1-xGe_x (x = 0.2 - 0.3).

A 45nm BiCMOS process, based on PDSOI CMOS, with SiGe HBT NPNs having f_T/f_MAX = 380/550GHz is presented. The bipolars are integrated on a PDSOI wafer in an epitaxial region above the handle wafer to avoid self-heating concerns. The paper reviews advantages and challenges to integrating SiGe BiCMOS on an advanced node SOI technology.

This paper reviews the recent studies in hot carrier degradation mechanisms of SiGe HBTs under saturation mode and off-state operation. Reliability of these devices gets increased scrutiny as technological scaling drives down device dimensions. Even as the performance of these devices increases, the hot carrier generation and reaction kinetics concepts driving degradation in sensitive regions of the device remain the same. The new mechanisms discussed here can be broadly categorized using the physics of high-voltage or high-current electrical stress conditions that have been well-studied. Measurements and TCAD simulations suggest that voltage-limited mechanisms consistently see worse degradation at lower temperatures while current-limited mechanisms respond to both higher temperature and higher current density. These limitations must be carefully evaluated during the development of new technologies and circuits.

Emitter resistivity should be optimized to increase the electrical performances of bipolar transistors. A non-selective Si:As deposition at temperature higher than 600 °C is currently used to fabricate such emitters: poly Si:As grows on dielectrics whereas monocrystalline Si:As grows on Si. A fully monocrystalline material would be needed to reduce the emitter resistivity, however. Therefore, a new process performed at 550 °C has been developed with Si₂H₆ as the Si precursor. Emitter mono-crystallinity is achieved by coupling amorphous deposition on dielectrics and solid phase epitaxy regrowth. The crystallinity of the structure has been checked by ACOM-TEM. With the Si₂H₆ process, an unusual diffusion of As is observed and has been reproduced on blanket wafers. The study on blankets wafer highlights that the diffusion is enhanced during a period: no enhanced diffusion occurs between 10 h and 24 h annealing at 720 °C. For the first time, transient enhanced diffusion of As is observed after low temperature epitaxy.

A physics-based compact model of band-to-band tunneling (BTBT) and trap-assisted tunneling (TAT) currents in forward bias conditions is presented. The model is demonstrated on SiGe HBTs with heavily doped emitter-base junctions.

This paper presents recent advances in compact modeling of avalanche multiplication in Mextram 505, an industry-standard transistor model, including new model features, improved model implementations, and implications for SiGe HBT RF circuit simulation and device modeling.

Strained isotopically enriched ²⁸Si strained layers in SiGe/Si/SiGe heterostrustructures is an excellent material platform for electron spin qubits. In this work, we report the fabrication of ²⁸SiGe/²⁸Si/²⁸SiGe heterostructures for qubit devices by a hybrid MBE/CVD growth, where the thick relaxed SiGe buffer is realized by a reduced-pressure CVD and the ²⁸SiGe/²⁸Si/²⁸SiGe stack is grown by an MBE. Here, we achieve a fully strained ²⁸Si layer in such heterostructure with a ²⁹Si concentration as low as 200 ppm within the MBE grown layers. It was possible to conclude that ²⁹Si primarily originates from the residual natural Si vapour in the MBE chamber. Furthermore, we also present our studies about the growth temperature effect on the misfit dislocation formation in this heterostructure. It was possible to show that at a low MBE growth temperature, such as 350°C, the misfit dislocation formation is significantly suppressed.

Strained SiGe layers with high Ge concentrations are grown on the Ge and Ge-on-Si substrates with various crystal orientations, and structural properties are studied. Particularly, initial stages of defect formation and related surface morphology are investigated. It is found that cracks are generated in the tensile-strained layer and surface ridge roughness is formed around the cracks although the total relaxation ratio of the SiGe layer is almost 0 %. Due to annealing the tensile strain is partially relaxed by creating additional trench-like roughness with the initially formed ridge roughness left unchanged. This comparative investigation of strain relieving defect formation provides quite useful information toward applications to strained SiGe-based optoelectronic and spintronic devices with enhanced performances.

A method for high quality epitaxial growth of Ge on Si (111) and Si (110) is investigated by reduced pressure chemical vapor deposition. Two step Ge epitaxy (low temperature Ge seed and high temperature main Ge growth) with several cycles of annealing by interrupting the Ge growth (cyclic annealing) is performed. In the case of Ge seed layer growth below 350 °C for (111) and 400 °C for (110) orientation, huge surface roughening due to too high dislocation density is observed after the following annealing step. For both crystal orientations, a high crystallinity Ge seed layer is realized by combination of 450 °C growth with 800 °C annealing. Once the high-quality Ge seed layer is deposited, high crystal quality Ge can be grown at 600 °C on the seed layer for both crystal orientations. For the 5 µm thick Ge layer deposited with the cyclic annealing process at 800 °C, a Si diffusion length of ~400 nm from the interface, RMS roughness below 0.5 nm and threading dislocation density of 5×10⁶ cm^-2 are achieved for both (111) and (110) substrates.

In this paper, epitaxial growths or depositions were performed, in 300 mm RP-CVD chambers, on two types of templates: N-type Si substrates or poly-Si/oxide/ P-type Si substrates. SiH₄+HCl+H₂ and SiH₂Cl₂+HCl+GeH₄+H₂ chemistries were used to deposit Si and SiGe layers between 675-750°C and 10-20 Torr on such wafers. Monocrystalline and polycrystalline growth kinetics were similar for intrinsic SiGe. Meanwhile, growth kinetics and boron incorporation were different for mono-Si:B, mono-SiGe:B, poly-Si:B and poly-SiGe:B layers. While the impact of B atoms is well documented in monocrystalline layers, it is still poorly understood for polycrystalline layers. An attempt has therefore been made to quantify it by measuring the poly-structure, with a focus on the poly-grains size and the number of grain boundaries. A lattice contraction coefficient β = - 9.82 * 10^-24 cm³ has otherwise been extracted from an in-depth study of the incorporation of B atoms into substitutional sites of the SiGe epitaxial lattice.

In this paper, SiGe or SiGeC epitaxy with Silane or Disilane, Germane and Methylsilane precursors was studied in a 300 mm industrial Reduced Pressure-Chemical Vapor Deposition (RP-CVD) reactor. The SiGe growth rate exponentially increased with the temperature in the 500 °C - 600 °C range for both silicon precursors (activation energy E_a = 2.1 eV). It was, at 550 °C, almost twice higher with Si₂H₆ than with SiH₄. At low temperature, Si₂H₆ is indeed more reactive than SiH₄, resulting in SiGe growth rates significantly higher for a given germanium composition. Then, carbon incorporation at 550 °C into Si_0.8Ge_0.2 was studied. The higher reactivity of Si₂H₆ compared to SiH₄ resulted in a better substitutional carbon incorporation. In our experimental conditions, 1.2 at% of fully substitutional carbon atoms could indeed be obtained with Si₂H₆ (without any detectable interstitial ones). Meanwhile, only 0.5 at% of fully substitutional carbon atoms was obtained with SiH₄.

The effect of the growth temperature and the Ga precursor flow on the epitaxy of Si_1-xGe_x:Ga is studied. These parameters are found to have a significant impact on the Ga surface segregation behavior. In particular, Ga in situ doping impacts the growth rate of the epilayer, the Si_1-xGe_x alloy composition, and the onset of strain relaxation. The growth temperature can be used to modulate the Ga segregation, enabling the deposition of materials with enhanced dopant concentrations and improved electrical properties. The Ga local atomic environment was studied in both a Si_0.4Ge_0.6:Ga and a Ge:Ga sample by X-ray absorption fine structure. The local environment of the Ga determined confirmed that the majority of dopants occupy a substitutional position within the lattice.

Years of work have been dedicated to the optimization of thickstrain-relaxed buffers. Thanks to the use of graded Ge content layersbeneath the constant composition layers on top, threadingdislocations densities around 10⁵ cm^-2 have been obtained. Recentlyan innovative phenomenon has been observed concerning SiGe-On-Insulator (SGOI) layer relaxation. We propose to use this approachto obtain fully relaxed SGOI layers without dislocations in industrialconditions on 300mm wafers. This new approach would enable usto fabricate relaxed SGOI layers which are uniform in composition.Such an innovation would be relevant for several applications suchas, for instance, the re-epitaxy of Si_0.5Ge_0.5 layers.

Dislocation free local SiGe-on-insulator virtual substrate is fabricated using lateral selective SiGe growth by reduced pressure chemical vapor deposition. The lateral selective SiGe growth is performed around ~1.25 µm square Si (001) pillar in a cavity formed by HCl vapor phase etching of Si at 850 °C from side of SiO₂ / Si mesa structure on buried oxide. Smooth root mean square roughness of SiGe surface of 0.14 nm, which is determined by interface roughness between the sacrificially etched Si and the SiO₂ cap, is obtained. Uniform Ge content of ~40% in the laterally grown SiGe is observed. In the Si pillar, tensile strain of ~0.65% is found which could be due to thermal expansion difference between SiO₂ and Si. In the SiGe, tensile strain of ~1.4% along <010> direction, which is higher compared to that along <110> direction, is observed. The tensile strain is induced from both [110] and [-110] directions. Threading dislocations in the SiGe are located only ~400 nm from Si pillar and stacking faults are running towards <110> directions, resulting in wide dislocation-free area formation in SiGe along <010> due to horizontal aspect ratio trapping.

The manufacturing of heterostructures is interesting in many fields such as photonics, solar energy production and quantum technologies. This paper, dedicated to germanium on silicon heterostructure manufacturing and stress engineering, builds up on LETI and EVGroup's hot bonding technology (1). The coefficients of thermal expansion (CTE) mismatch between germanium and silicon is used to induce some in-plane tensile stress in a thin germanium layer transferred by the Smart Cut^TM technique onto a silicon substrate. In this approach, a bulk germanium wafer is directly bonded on a bulk silicon wafer, using surface activated hot bonding (SAHB). Process integration advantages are the low defect density of bulk germanium and the tensile stress that can be tuned using the bonding temperature. According to X-Ray diffraction measurements, for a bonding performed at 250°C, the lattice parameter deformation reached +0.06%, resulting in a 82 MPa tensile stress in a 370 nm thick germanium layer.

We fabricate thick strained Si0.1Ge0.9/Ge multiple quantum wells (MQWs) structures on Ge-on-Si, and evaluate their crystallinities and optical properties. As a result, it is found that highly crystalline Si0.1Ge0.9/Ge MQWs are grown both on Ge-on-Si(100) or Ge-on- Si(111), where surface roughness slightly differs between the two. From both MWQs we obtain strong room-temperature photoluminescence (PL) via quantum confinements of carriers in the MQWs. It is also found that the PL peak positions and intensities are different between (100) and (111). Surface roughening is considered to cause reduction in the PL intensity and the peak shift for the (111) case whereas the MQWs on Ge-on-Si(100) shows very smooth surface and resultantly strong PL intensity, indicating that Si0.1Ge0.9/Ge MQWs are promising for applications to light-emitting devices that can be integrated on the Si platform.

We observe strong room-temperature photoluminescence from Ge microbridges formed on Ge-on-Si (110). The Si (110) substrate is employed to fabricate the bridge along [111] direction as uniaxial strain in the [111] direction is expected to be the most effective to bring direct transition. In this study, we grow Ge-on-Si with (110) orientation and fabricate MB along the [111] directions. Due to the low etching rate of the (111) plane, however, etching of the Si under the square-shaped pads is quite difficult. By contrast, we fabricate branch-like MB, where the underneath Si was fully etched owing to the various directions of the etching. As a result, we obtained very strong resonant light emission.

Low contact resistances are required to continue the miniaturization of CMOS devices and improve the performances of group IV semiconductors' photodiodes and light emitting devices. In this study, we tried to enhance the electrical activation in in-situ boron-doped germanium by nanosecond laser annealing (NLA), an ultrafast, non-equilibrium process. Similar annealing regimes than that evidenced on SiGe thin layers were seen. Surface structures with shapes and orientations comparable to that after SiGe NLA were found in the surface melt regime. When the entire Ge:B layer was melted, we obtained a flat surface with a root mean square roughness of 1.51 nm. Laser annealing resulted in a redistribution of B, with the formation of electrically inactive clusters that did not contribute to strain. Accordingly, the sheet resistance increased by 70%, from 39.82 Ω/□ up to 68.62 Ω/□, when the layer was melted. This corresponded to an electrically active carrier loss of around 50%, from 8.1x10²⁰ cm^-3 down to 3.8x10²⁰cm^-3. Even multiple pulses with various energy densities at the same position were not able to improve electrical activation. However, there was some slight improvements of the sheet resistance in the sub melt regime, which needs to be confirmed in future experiments.

Ge epitaxy on nanometer-size Ge pillars was studied in a 300 mm industrial Reduced Pressure-Chemical Vapour Deposition tool. A patterning scheme based on diblock copolymer lithography was used to fabricate honeycombed nanometer-sized Si templates for the hetero-epitaxy of Ge nano-pillars. It was highly selective and uniform at 600°C. Thick Ge layers were then grown with a low temperature/high temperature approach on Ge nano-pillars and characterized by Atomic Force Microscopy, X-Ray Diffraction and cross-sectional Transmission Electron Microscopy. A degraded surface morphology, with otherwise similar structural properties was obtained for 2D Ge layers grown on Ge nano-pillars compared to growth on bulk Si. Defects such as stacking faults and twins also formed during the coalescence process.

Ultra-violet (UV) laser annealing (LA) is a promising technology that is being investigated for next-generation CMOS processing. UV-LA's unique capability of activating dopants very near to the surface due to the very shallow penetration depth can be critical for achieving very low-contact resistivity materials and structures. Here we present a detailed analysis of the effects of UV-LA on very highly As-doped material. Physical and chemical data-sets (SIMS, XTEM and FFTM) are compared with the electrical depth profiles obtained using Differential Hall Effect Metrology (DHEM).

We have fabricated valency-controlled Si-QDs with Ge-core with an areal density as high as ~10¹¹ cm^-2 on ultrathin SiO₂ and studied the effect of phosphorus- and boron-doping on Ge-core from their PL properties. During the Ge deposition, delta doping of phosphorus or boron atoms in QDs was carried out by pulse injection using 1% PH₃ or B₂H₆ diluted with He, respectively. No changes in dot size and density with either P- or B-doping were confirmed by AFM topographic images. Under photoexcitation of undoped QDs with a 976-nm line from a semiconductor laser, broad PL spectra consisting of four Gaussian components originating from radiative recombination through quantized states in QDs were observed in the energy range from 0.62 to 0.85 eV without impurity doping even at room temperature. In the doped QDs, relatively-narrow components peaked at ~0.68 eV and ~0.64eV were observed with P-doping and with B-doping to Ge-core, respectively, in addition to the four components seen in undoped QDs. It is interesting noted that, with an increase in B₂H₆ pulse injection from 1 to 4 times, the integrated PL intensity was enhanced by a factor of 1.4 to 2.4 compared to that of the undoped QDs while no significant change in spectral shape was observable. This can be interpreted in terms of an increase in the number of holes with B-doping to the Ge core since the carrier recombination rates is proportional to the product of the number of electrons and holes confined in QD under weak photoexcitation.

Three-dimensional (3D) self-ordered Ge nanodots in cyclic epitaxial growth of Ge/SiGe superlattice on Si_0.4Ge_0.6 virtual substrate (VS) were fabricated by reduced pressure chemical vapor deposition. By the Ge/SiGe superlattice deposition, dot-on-dot alignment and <100> alignment were obtained toward the vertical and lateral direction, respectively. Facets and growth mechanism of Ge nanodots and key factors of alignment were studied. Two types of Ge nanodots were observed, diamond-like nanodots composed of {105} and dome-like nanodots composed of {113} and {159} facets. The Ge nanodots tend to grow directly above the nanodots of the previous period as these regions show a relative higher tensile strain induced by the buried nanodots. Thus, this dot-on-dot alignment is sensitive to the SiGe spacer thickness, and it degrades when the SiGe spacer is over 82 nm. The Ge content of the SiGe spacer ranging 45-52% affects the lateral alignment and the size uniformity of Ge nanodots because of the strain balance between the superlattice and the VS. When the strain is balanced, 3D aligned Ge nanodots can be achieved.

We investigated stress evaluation of strained group IV semiconductor devices by oil-immersion Raman spectroscopy. In the oil-immersion Raman spectroscopy the high-numerical-aperture lens gives evaluation of complicated stress states in strained group IV semiconductor devices. As an example of the stress evaluation, a clear stress relaxation of the extremely thin body germanium on insulator (ETB GOI) channels was observed. This behavior indicates that the uniaxial stress is applied into GOI channels by patterning narrow channel. We confirmed that the uniaxial stress is applied into GOI channels by narrow channel patterning at even in ETB GOI channels down to approximately 4 nm by oil-immersion Raman spectroscopy, and stress relaxion (quasi-uniaxial stress) in GOI channels and hole mobility enhancement have good correlation.

We evaluated the optical properties and the band structure of strained single crystalline Si_1-xSn_x using spectroscopic ellipsometry. The results suggest a reduction of the band gap at the Γ point and the formation of an optical transition by Van-Hove singularity with higher Sn fraction. In addition, since the reduction of the band gap with increasing Sn fraction at the Γ point is larger than at other points, it is expected the indirect transition type Si_1-xSn_x used in this study may eventually change to the direct transition type. Although higher Sn fraction are required to achieve direct transition type Si_1-xSn_x, the band structure of strained single crystal Si_1-xSn_x was experimentally clarified.

We report on the distribution of the optical properties in strain-relaxed SiGe films. We confirmed that the SiGe film (Ge fraction: 50%) has a larger variation of the extinction coefficient than the SiGe film (Ge fraction: 20%) in the near-infrared region. This result suggests that the distribution of the optical properties of the SiGe film (Ge fraction: 50%) may have a significant effect on process yields while the SiGe film (Ge fraction: 20%) should have a smaller effect on process yields. In addition, we investigate the distribution of Ge fraction, strain and cross-hatch pattern, and consider their relationship to optical properties.