Table of contents

This paper gives an overview of the impact of certain processing steps on the low-frequency (LF) noise behavior of silicon Gate-All-Around (GAA) Vertical Nanowire (VNW) MOS transistors. It is shown that the width of a Replacement Metal Gate (RMG) cap impacts the flicker noise Power Spectral Density (PSD). The type of source contact, i.e., bulk versus a confined top contact significantly changes the nature and the magnitude of the 1/f noise. Finally, the doping density of the silicon nanowires has a subtle influence, whereby the dominant fluctuation mechanism shifts from number to mobility fluctuations, while increasing the doping density. Optimal noise performance is achieved for intermediate in-situ nanowire B doping density.

Si-friendly HfO₂-based ferroelectric devices have been strongly recognized as a novel technology booster for future integrated memory and logic systems. In this paper, we address our recent activities on TiN/Hf_0.5Zr_0.5O₂(HZO)/TiN MFM capacitors, HZO/Si FeFETs for memory applications and a newly-proposed reservoir computing using HZO/Si FeFETs and MFM capacitors for AI applications. We have demonstrated that MFM capacitors with HZO less than 5 nm can realize low crystallization temperature, excellent ferroelectricity, low operating voltage and high read/write endurance by performing sufficient wake-up operations to the thin HZO films. For the FeFET memory, we have found the importance of interfacial layers (ILs) between HZO and Si on the memory window. It has been revealed that the IL thickness is sensitive to the process temperature and that electron trapping around HZO/ILs has significant impacts on the memory operation. Finally, we have proposed and experimentally demonstrated reservoir computing using FeFETs for neuromorphic applications.

Two types of vertically stacked graphene junction diodes were fabricated in this study. Samples of single-crystal graphene measuring 100 mm² were epitaxially grown on SiC substrate using the thermal decomposition method and were bonded using the direct bonding technique. The direct-bonded stacked junction diode exhibited nonlinear current-voltage characteristics and acted as a far-infrared emitter. Fowler-Nordheim tunneling phenomena with a strong nonlinear behavior was observed in the tunneling diode with a thin insulative layer (air gap or structured water). By using simple device-assembly processes, vertically stacked graphene diodes with new functions were successfully fabricated.

We describe single-electron manipulation in a dynamic random access memory (DRAM) composed of an attofarad capacitor and nanometer-scale transistors. The motion of a single electron is controlled and then the electron is stored in the capacitor using the transistors, whose leakage current is suppressed to the theoretical limit. The charge signal of the electron is amplified by another transistor integrated in the DRAM, which functionalizes the single electron as one bit of information for data processing. In addition to such single-electron applications, power generation using a conceptual analogy of Maxwell's demon detecting and manipulating a single-electron motion is demonstrated for an understanding of the essential correlation of data processing to its energy consumption. These demonstrations are promising as a starting point for constructing new technologies for the ultimate reduction in the power consumption of data processing circuits.

High-voltage power rectifiers are widely used in renewable energy processing, electric grids, industrial motor drives, pulse power systems, among other applications. Today's high-voltage rectifier market is dominated by bipolar Si diodes up to 6.5 kV, which suffer from slow reverse recovery. Wide-bandgap SiC unipolar diodes have been pre-commercialized up to 10 kV, which allows for a much higher switching speed. Recently, we have developed a new generation of high-voltage rectifiers based on the multi-channel AlGaN/GaN platform, which highlight a series of novel device designs incorporating the stacked two-dimensional electron gas (2DEG) channels, p-n junctions, and 3-D fin structures. With these innovations, the performances of our unipolar 1.2-10 kV multi-channel AlGaN/GaN Schottky rectifiers well exceed the Si and SiC 1-D limit, at the same time possessing a lower cost as compared to SiC counterparts. This paper reviews our efforts in the design, fabrication and characterization of these GaN devices. Our results show the tremendous promise of GaN for medium-voltage and high-voltage power electronics applications.

Ultra-rapid thermal annealing in millisecond has been performed by atmospheric-pressure thermal plasma jet (TPJ) and temperature measurement based on optical interference contactless thermometry (OICT) is investigated. On the basis of optical interference in silicon wafer induced by the change in refractive index and its analysis, transient temperature variation is obtained with millisecond time resolution. Moreover, OICT imaging allow us to obtain the temperature information in planar and depth direction simultaneously.

Scanning internal photoemission spectroscopy has been developed to map the electrical characteristics of metal/semiconductor interfaces nondestructively. We conducted two-dimensional characterization of wide-bandgap Schottky contacts such as GaN, SiC, and oxide semiconductors. Our experimental demonstrations of the mapping characterization are reviewed from the aspects of (A) thermal degradation, (B) device degradation by applying high-voltage, (C) process-induced surface damages, (D) grain boundaries of semiconductors and printed metal particles, and (E) expansion to semiconductor/semiconductor and metal-insulator-semiconductor interfaces. This technique was confirmed to be useful for the development of the wide-bandgap-semiconductor high-power devices.

This paper presents a high-sensitivity accelerometer module to measure micro muscular sounds. The feature of our microelectromechanical systems (MEMS) accelerometer is the use of high-density gold proof-mass structure fabricated by the multi-layer metal technology for reducing the Brownian noise. The noise floor of the proposed module is 10-dB better than that of a commercial one. The measurement results showed that our module can capture small muscular sounds which are buried in the noise of the commercial accelerometer.

Stable operations as resistive switching memory were demonstrated in amorphous TaO_x (a-TaO_x) thin films with very flat surfaces by conductive atomic force microscopy (c-AFM). The a-TaO_x thin films fabricated on glass and Nb-doped SrTiO₃ substrates by pulsed laser deposition showed high surface flatness with root-mean-square roughness of less than 0.2 nm. The c-AFM observations on the surfaces revealed that the resistive switching in a-TaO_x causes almost no change in the topographic structures, and the significant structural deformation appears after the electrical breakdown by longer-range migration of the constituent ions. The possible mechanisms of the resistive switching phenomena were discussed based on the changes in the topographic structures and conduction states.

We have fabricated Si-QDs with boron-doped Ge core with an areal density as high as ~10¹¹ cm^-2 on ultrathin SiO₂ and characterized their room temperature photoluminescence (PL) properties. With B doping to the Ge core, stable PL observed in the energy range of 0.62 - 0.85 eV was increased by a factor of ~1.5. Note that a new relatively-narrow component peaked at ~0.64 eV emerges in addition to four components derived from the spectral deconvolution of the PL spectrum of undoped QDs and is attributable to radiative recombination between the first quantized state in the conduction band of the Si clad and the B-acceptor level in the Ge core. With H₂ post-anneal at 100°C, the integrated PL intensity of the B-doped QDs was reduced by ~35% and the 0.64 eV component disappeared. With increasing H₂ post-anneal temperature up to 350°C, the PL intensity was increased to ~1.4 times the initial intensity before post-annealing, and the 0.64 eV component was recovered. The observed PL changes with post-anneal are attributable to hydrogen-induced passivation of B acceptors at 100°C and thermal dissociation of B-H complex at higher temperatures up to 350°C accompanied with hydrogen passivation of residual dangling bond defects as seen in the undoped case.

We discussed about usefulness of HfO₂-based high dielectric constant (High-k) materials such as HfO₂, HfSiO_x and HfAlO_x as gate insulator for GaN power device. Here, we systematically studied characteristics of Hf_0.55Al_0.45O_x gate insulator which fabricated by plasma-enhanced atomic layer deposition and post-deposition annealing (PDA) at 800°C in N₂ ambient. The Hf_0.55Al_0.45O_x film had an amorphous structure but Ga diffusion into Hf_0.55Al_0.45O_x film was observed after PDA. The k-value of the Hf_0.55Al_0.45O_x film was 17.2, which was larger than that of HfSiO_x (13.5). The Hf_0.55Al_0.45O_x also showed superior electrical properties such as a minimal flatband voltage (V_fb) hysteresis ( +10 mV) and a relatively small V_fb shift ( £ -0.95 V), as well as a low interface state density (~ 1 ´ 10¹¹ cm^-2eV^-1 at E_c-E=0.25 eV), and a high breakdown electric field (8.6 MVcm^-1). Based on these experimental data and previous our research of HfO₂ and HfSiO_x films, we concluded the HfSiO_x and HfAlO_x had candidate materials as gate insulator for GaN power device.

We investigated characteristics of ZrO₂/Al₂O₃ (ZA) and Al₂O₃/ZrO₂ (AZ) insulators after two annealing step such as post-deposition annealing (PDA) at 600°C before TiN top electrode (TE-TiN) deposition and post-metallization annealing (PMA) at 600°C after TE-TiN deposition. The ZrO₂ layers (2.9-5.7 nm) and Al₂O₃ layer (2.0 nm) were deposited by atomic layer deposition at 300°C. ZrO₂ layer had a polycrystalline structure while Al₂O₃ layer had an amorphous structure. The capacitance of the AZ capacitors after PDA or PMA reasonably decreased as ZrO₂ thickness increased. On the other hand, the ZA capacitors after PDA (ZA wPDA) exhibited almost similar capacitance while the ZA capacitors after PMA decreased as well as the AZ capacitor. The dielectric constant (k) of the ZA wPDA drastically increased to 44 compared to other capacitors (30-37) in the ZrO₂ thickness region of over 4.9 nm. This is because the ZrO₂ layer was annealed with an asymmetric structure sandwiched between Al₂O₃ and TiN with different coefficients of thermal expansion during PDA. Furthermore, the ZA wPDA with the ZrO₂ layers (4.9-5.7 nm) exhibited superior characteristics satisfying a high k-value and a high electric filed value at J = 1 × 10^-5 Acm^-2. These indicated that PDA treatment should perform after 1^st-ZrO₂/Al₂O₃ layer deposition to obtain ZrO₂ layer with high k-value.

We studied a SiO₂ interfacial layer (SiO₂-IL) growth between a ferroelectric Hf_xZr_1−xO₂ (HZO) film, which fabricated by atomic layer deposition (ALD) using a Hf/Zr cocktail precursor, and p-type Si substrate during the metal-ferroelectric-semiconductor (MFS) fabrication. For the annealing process, two types of a post-deposition annealing (PDA) and post-metallization annealing (PMA) were employed before and after the fabrication of the TiN top-electrodes, respectively. An ultra-thin SiO₂-IL of one or two monolayers at the HZO/Si interface was achieved using a 300°C fabrication process of ALD, and PDA or PMA. In contrast, PDA and PMA processes at ≥ 400°C led to an unexpected SiO₂-IL formation, which increased with the annealing temperature, regardless of the formation of TiN top-electrodes. Therefore, we found that a suppressed SiO₂-IL of HZO-based MFS structures can be obtained using the 300°C fabrication process.

This work reports on low temperature epitaxial growth solutions for the processing of advanced CMOS devices beyond the 3 nm technological node. The complex stacking of highly compositionally contrasted strained group IV materials is first demonstrated at 500°C. It enables the formation of active nanosheet channels with bottom isolation, necessary for ultimate transistor scaling. Using high order Si and Ge precursors also offers great opportunities for the epitaxy of advanced source/drain materials. It allows achieving hole active concentrations as high as 1.3x10²¹ cm^-3 in in-situ B-doped Si_0.5Ge_0.5, providing Ti / SiGe:B contacts with low specific resistivity. Grown at temperatures as low as 400°C, the epilayers deposit in a conformal manner, thereby wrapping high aspect ratio 3-dimensional structures and maximizing the contact areas, being an additional option to further decrease device access resistances. As an alternative to B-doping only, we also demonstrate uniformly Ga-doped materials with concentrations ~ 1x10²⁰ cm^-3. B and Ga are finally combined to co-dope SiGe and further reduce the Ti / p-SiGe contact resistivity.

A selective-area epitaxial growth of Ge on the submicron scale is studied using chemical vapor deposition (CVD) on Si in terms of the fabrication of integrated photonic devices operating at the optical communication wavelengths of around 1.55 μm. A mesa structure of Ge on the micron scale, having a vertical pin junction, is effective for fabricating a waveguide-integrated photodetector in the optical receiver. A 3-dB cutoff frequency is obtained up to approximately 50 GHz. For a higher frequency operation, a narrower structure of submicron-wide Ge wire, having a lateral pin junction, is required. Such a wire structure is also important for the application to an electro-absorption optical intensity modulator in the optical transmitter. Structural and optical properties are investigated for a submicron-wide Ge wire on Si selectively grown by CVD.

Ge has been received much interest as a CMOS channel material and a near-infrared optical material due to its superior characteristics. Ge-on-Insulator (GOI) structure is necessary to suppress large leakage current originating from the narrow bandgap for application use. A method combined wafer bonding and layer splitting by hydrogen ion (H⁺) implantation, known as Smart-Cut^TM realized for Si-on-Insulator fabrication, has been tried to apply for fabricating GOI with large diameter, uniform thickness, and single crystal. In this study, we fabricated GOI by Smart-Cut^TM technique and demonstrated electronic and optoelectronic devices on the GOI. Besides, we combined a Ge epitaxial growth method with the Smart-Cut^TM technique to improve GOI quality.

The impact of strain on the growth of in situ boron doped Si_0.5Ge_0.5 epitaxial layers is discussed. The lattice strain has been varied by changing the Si_0.5Ge_0.5 thickness and by growing the epitaxial layer on strain relaxed substrates with different Ge concentrations. With decreasing compressive strain, the B incorporation reduces, and the Ge concentration increases. Through density functional theory calculations, the dependence on the applied strain of the energetic cost for boron incorporation into the Si_0.5Ge_0.5 surface was investigated.

We investigate a new application of germanium tin (Ge_1−xSn_x) binary alloy thin films to realize energy harvesting of low-grade heat to electricity, i.e., thin-film thermoelectric generator (TEG). To clarify the potential of Ge_1−xSn_x for the TEG application experimentally, it needs to choose high-resistivity wafers as the substrate for the Ge_1−xSn_x growth to isolate electrically from the substrates. Specifically, this paper conducts crystal growths of Ge_1−xSn_x on FZ-Si, semi-insulating GaAs, and InP substrates. The impacts of Sn content and crystallographic tilt in the Ge_1−xSn_x on the thermal conductivity will be discussed experimentally and theoretically. We also show the scaling merit of the device sizes in the power density.

Change of band alignment at SiO₂/4H-SiC was observed by extending the duration of interface nitridation process to passivate the interface defects. The conduction-band offset on (0001) stack increases but that on (000-1) and (1-100) stacks decrease, which does not result only in a difference of flatband voltage (V_fb) but also in a difference of gate leakage characteristics among those stacks on different crystal faces. An introduction of an additional dipole layer in the gate stack was demonstrated by depositing a few-nm-thick Al₂O₃ on SiO₂ to cause a positive shift of V_fb without degrading the quality of SiO₂/SiC MOS interface. Control of those factors to cause V_fb shift is crucially important to reduce the mobility degradation in SiC MOSFET inversion channel by increasing the channel doping concentration to tune the threshold voltage.

In this work, we model 3D corner residues based on a process flow simulation using the Coventor SEMulator3D virtual platform. The role of clogging existing during plasma etch process in 3D corner formation has been studied based on the simulation results. In particular, the impacts of clogging and plasma aspect ratio distribution functions on corner size in typical etching steps are assessed. Furthermore, tunable model provides insights on the effect of fin height variation. Higher Fin structure could provide more shadowing effects which encourage the aggregation of 3D corner residue. In an advanced model containing multiple dry etch steps, the window of plasma divergence is also discussed, which is helpful to study and deal with the existing of 3D corner residue.

SiGe channel metal oxide semiconductor field effect transistor (MOSFET) became a choice of material as a performance booster in leading edge logic technologies. In this study, we demonstrate integration solutions for dual Fin formation (Si for nFET, SiGe for pFET) using buried SiGe channel approach on 300 mm Si wafer. Plasma-induced damage (PID) layer, which thickness ranges from 0.5 nm to 2.5 nm, was observed after Si trench (p-trench) etch for SiGe EPI growth. This PID inorganic layer leads to SiGe dislocation defect. And careful sequencing and optimization of oxidation and wet removal steps were able to realize defect-free SiGe EPI channel along with a thin buffer SiGe layer. Besides, margin assessment of p-trench based buried SiGe approach was also presented in this study. Moreover, dual Fin etch was demonstrated via inductively coupled plasma (ICP) using ALD-like function. The depth loading between SiGe and Si Fin was tunable via varying repeated cycles of advanced pulsing step, and less than 40 A of depth loading can be achieved. The progress reported represents a major leap for SiGe channel integration and paves the way for massive production.

Horizontally stacked nanosheet gate-all-around devices enable area scaling of transistor technology, while providing improved electrostatic control over FinFETs for a wide range of channel widths within a single chip for simultaneous low power applications and high-performance computing. Fabrication of inner spacers and Si channels is challenging, but essential to device performance, yield, and reliability. We elucidate these challenges and detail their impact to the device. We overcome these challenges with novel, highly selective, isotropic SiGe dry etch techniques which enable precise, robust inner spacer and channel formation. Finally, we demonstrate substantial improvements to relevant device parameters: resistance, drive current, transconductance, threshold voltage, breakdown voltage, bias temperature instability and overall variability.