Table of contents

Insulator/Si interface flattening effects and gate oxide breakdown characteristics are evaluated for the oxygen radical oxidation and the wet oxidation at 750 °C. The radical oxidation is confirmed to exhibit a superior flattening effect than the wet oxidation. To obtain atomically flat top surface and interface to Si for oxides, radical oxidation on atomically flattened surfaces is indispensable. When the oxides are formed by radical oxidation on conventional flat Si surfaces with R_a≥0.12 nm, early breakdowns occur more frequently than wet oxides. These early breakdowns are eliminated when surfaces with R_a≤0.06 nm are employed before oxidation. It is suggested that the early breakdowns occur at local spots that induce excess electric field due to the flattening of micro-roughness by the radical oxidation. To apply the radical reaction based insulator formation technology to the gate insulator formation, the surface before gate insulator formation must be sufficiently flattened.

In this paper, the thermal stability of Ni-germanide is improved by utilizing Ni/Co/Ni/TiN structure for Ge metal–oxide–semiconductor field effect transistors (MOSFETs) technology. It was shown that the Ni/Co/Ni/TiN structure improved the thermal stability of Ni-germanide mainly due to the suppression of Ni diffusion, and/or the retardation of agglomeration. The incorporated Co atoms distributed, mainly in the top region of the Ni-germanide and it is believed that this Co-rich Ni-germanide layer in the upper region of Ni-germanide enhanced the thermal stability. Therefore, the proposed Ni/Co/Ni/TiN structure is promising for the formation of a highly thermally immune Ni-germanide for nanoscale Ge MOSFETs technology.

Precise stress measurements have been desired in order to apply strained Si substrates to next-generation transistors. Oil-immersion Raman spectroscopy enables the evaluation of the anisotropic stress state in the strained Si layer of the strained Si substrate even under (001)-oriented Si backscattering geometry. First, we found that the phonon deformation potentials (PDPs) reported by Anastassakis et al. in 1990 was the most valid among the three sets of PDP previous reported. Using these PDPs, the precise Raman measurements of biaxial stress in strained Si-on-insulator (SSOI) nanostructures were performed. The biaxial stresses σ_xx and σ_yy decreased with the decrease in SSOI width and length, which was consistent with the finite element method calculation.

We fabricate ultrathin HfO₂ gate stacks of very high permittivity by atomic layer deposition (ALD) and oxygen-controlled cap post-deposition annealing. The HfO₂ layer is directly deposited on a wettability-controlled Si surface by ALD. To enhance permittivity, a cubic crystallographic phase is generated in ALD-HfO₂ by short-time annealing with a Ti capping layer. The Ti layer absorbs residual oxygen in the HfO₂ layer, which suppresses the growth of the interfacial SiO₂ layer. The dielectric constant of ALD-HfO₂ is increased to ∼40, and a gate stack of extremely scaled equivalent oxide thickness (∼0.2 nm) is obtained.

We investigated thermally induced flatband voltage (V_FB) instabilities with single noble metals (Pt, Ir, Pd), their binary metal (IrPt) and control TiN used for gate electrodes in metal oxide semiconductor devices with atomic layer deposited HfO₂ gate dielectric. As-deposited e-beam evaporated noble metals and sputtered TiN gated devices show near band-edge p-type metal–oxide–semiconductor (pMOS) characteristics and higher V_FB than midgap value, respectively. After 450 °C at 30 min forming gas anneal, V_FB of devices with e-beam evaporated single metals and sputtered TiN is substantially shifted toward mid-gap position, indicating thermally induced V_FB instability. However, device with binary metal alloy gate shows suppressed V_FB shifts and work-function as high as 4.95 eV is attained with 450 °C at 30 min FGA. It can be explained by oxygen diffusion within gate stack structure into interfacial layer (IL) between Si and HfO₂ during anneal, leading to thicker IL and vacancy generation in dielectric.

We have confirmed the basic performance of a new logic intellectual property (IP) compatible (LIC) embedded dynamic random access memory (eDRAM) with cylinder capacitors in the low-k/Cu back end on the line (BEOL) layers. The LIC-eDRAM reduces the contact (CT) height, or essentially the RC delays due to the parasitic component to the contact. By circuit simulation, a 28-nm-node LIC-eDRAM with the reduced CT height controls the logic delay with Δτ_d < 5% to that of 28-nm-node standard complementary metal oxide semiconductor (CMOS) logics, enabling us ensure the logic IP compatibility. This was confirmed also by a 40-nm-node LIC-eDRAM test-chip fabricated. The 40-nm-node inverter delays in the test-chip were controlled actually within Δτ_d < 5%, referred to those of a pure-CMOS logic LSI. Meanwhile the retention time of the DRAM macro was in the range of milliseconds, which has no difference to that of a conventional eDRAM with a capacitor-on-bitline (COB) structure. The LIC-eDRAM is one type of BEOL memory on standard CMOS devices, and is sustainable for widening eDRAM applications combined with a variety of leading-edge CMOS logic IPs, especially beyond 28-nm-nodes.

Integrated antennas operating at millimeter-wave (mm-wave) frequency have been implemented on a benzocyclobutene (BCB)-based system-on-package (SOP) substrate. A novel BCB-based SOP substrate with a Si bump and a Si cavity was proposed to increase the BCB thickness, thus enhancing the gain of the microstrip patch array antenna and reducing the transfer loss of the transmission line. The mechanical issues of adhesion and stress of BCB are studied. The adhesion between gold and BCB was improved significantly by the insertion of a layer of Si oxide (SiO₂) by plasma-enhanced chemical vapor deposition (PECVD). SiO₂ can also reduce the wafer bow by stress compensation. Wafer bow of whole structure was decreased from 79.3 to 55.2 µm by the insertion of a 1-µm-thick SiO₂ layer. A series-fed 1 ×8 linear array antenna is impedance matched well at 77 GHz. The process flow including BCB chemical mechanical polishing (CMP) was described. The proposed SOP substrate can be a candidate for overcoming the constraint of BCB thickness.

A three-stage inverter-based stacked power amplifier (PA) in complementary metal oxide semiconductor (CMOS) process is proposed to overcome low breakdown voltage problem of scaled CMOS technologies. Unlike previous reported stacked PAs which radio frequency choke (RFC) was inevitable, we proposed stacked nMOS and pMOS transistors which effectively eliminates use of RFC. By properly setting self-biased circuits' and transistors' parameters, output impedance could reach up to 50 Ω which together with not employing the RFC makes this topology very appealing for the scalable PA realization. As a proof of concept, a three-stage PA using 65 nm CMOS technology is implemented. With a 6 V power supply for the third stage, the fabricated PA shows a small-signal gain of 36 dB, a saturated output power of 16 dBm and a maximum power added efficiency of 10% at 1 GHz. Using a 7.5 V of power supply, saturated output power reaches 18 dBm. To the best of our knowledge, this is the first reported inverter-based stacked PA.

With the progress of complementary metal–oxide–semiconductor (CMOS) process technology, it is possible to apply CMOS devices to millimeter-wave amplifier design. However, the power consumption of the system becomes higher in proportion to its target frequency. Moreover, CMOS devices are biased at a point where the device achieves the highest gain and consumes much power. In order to reduce the power consumption without any compromise, we introduce two types of indicator. One works towards achieving the highest gain with the lowest power consumption. The other works towards achieving the highest linearity with consideration of the power consumption. In this work, we have shown the effectiveness of those indicators by applying measured data of the fabricated metal–oxide–semiconductor field-effect transistors (MOSFETs) to cascade common-source amplifiers.

We have experimentally studied Si monolayers, fabricated by thermal oxidation of silicon-on-insulator (SOI) substrates at high temperature, for future extremely thin SOI (ETSOI) complementary metal oxide semiconductor (CMOS) devices, and have shown the strong quantum confinement effects in the ETSOIs. We have successfully formed 0.52-nm Si monolayers, as confirmed by transmission electron microscopy (TEM) and a UV/visual reflection method. We have experimentally shown the asymmetric broadening and the peak downshift of the Raman peak of ETSOIs evaluated by UV-Raman spectroscopy, which is enhanced in the ETSOI thickness T_SOI of less than about 5 nm. These results are due to the quantum phonon confinement effects in ETSOIs. Using the TEM observation and UV-Raman spectroscopy of ETSOIs, we have also shown the tensile strain of ETSOIs due to the Si bending and the T_SOI variations in ETSOI substrates. In addition, we have observed photoluminescence (PL) from the ETSOIs with a T_SOI of less than about 5 nm and the PL intensity strongly depends on the T_SOI. However, the peak photon energy of about 1.85 eV in the PL spectrum is independent of the T_SOI. We cannot explain the PL results perfectly at present, but we have introduced a possible three-region model of electron/hole pair generation in a two-dimensional Si layer and electron/hole pair recombination at the Si/SiO₂ interface state region.

A novel tunneling field-effect transistor (TFET) with an L-shaped Ge source is investigated. The device comprises a Ge source that extends underneath a Si-channel region and separated from the drain by an insulator (SiO₂). By optimizing the overlap length of the extended source L_OV and the Si body thickness T_Si, the current due to vertical band-to-band tunneling (BTBT) of the Ge–Si hetero-junction could be increased significantly and is scalable with L_OV. This leads to higher I_ON and improved S. The SiO₂ also reduces OFF-state current I_OFF by blocking leakage paths. With extensive simulation, the device physics and design guidelines of this novel structure are outlined.

The characterization and modeling of the hysteresis phenomenon observed in the off-state regime of n-channel polycrystalline thin-film transistors are presented. The shift in I_d–V_g characteristics between upward and downward scan were measured under various bias conditions and ambient temperatures. The localized positive charge build-up induced by band-to-band hot hole injection is responsible for the mechanism for reducing the off-leakage current, and it is recovered through the thermal emission of trapped holes, which is enhanced by self-heating of the device during the on-current conduction. On the basis of this model, the internal device characteristics related to the thermal and oxide trap properties are analyzed.

In this paper, the variabilities of threshold voltage (V_TH), drain-induced barrier lowering (DIBL), and current onset voltage (COV) in intrinsic channel silicon nanowire metal–oxide–semiconductor field-effect transistors (MOSFETs) were evaluated and compared with those of conventional bulk and fully depleted (FD) silicon-on-insulator (SOI) MOSFETs. The random component of variability is extracted by a "within-device" variability method to exclude the systematic component. It is found that the within-device variabilities of DIBL and COV as well as V_TH are extremely small in intrinsic channel nanowire MOSFETs owing to the non-intentionally doped channel and small gate workfunction variability. The intrinsic channel nanowire MOSFET is promising for a future scaled device structure in terms of not only the short channel effect suppression but also the variability suppression.

In this study, we developed a unified reaction–diffusion (R–D) model for the negative bias temperature instability (NBTI) effect over a wide range of stress times. The newly developed model provides a physics-based uniform solution and overcomes the limitations of the classical R–D models that cannot describe both the short and the long term stress regions simultaneously. In our modeling framework, the chemical reaction between inversion channel carriers and Si–H bonds at the Si/SiO₂ interface dominates the short-term NBTI effects at the beginning of the stress application. Then the H₂ diffusion into the polycrystalline silicon (poly-Si) gate becomes responsible for long term stress degradation. Finally, the developed R–D model is implemented into the advanced metal oxide semiconductor field effect transistor (MOSFET) model HiSIM to enable accurate circuit-aging simulation. Simulation results for the current degradation and their comparison with measurements verify the achieved high accuracy and the practical applicability of the developed NBTI model.

Negative bias temperature instability in Si nanowire transistors were systematically studied. Enhanced degradation by negative bias temperature (NBT) stress in narrow nanowire transistor was observed. Nanowire width and height dependences on threshold voltage shift suggest that the larger degradation was caused by the nanowire corner effect such as electric field concentration. High speed measurements elucidated the smaller recovery ratio in nanowire transistors which is attributed to be the local charge trap at nanowire corner. Stress memorization technique does not affect the threshold voltage shift by NBT stress.

The generation process of interface traps by hot-carrier injection in nanoscale metal–oxide–semiconductor field-effect transistors (MOSFETs) was evaluated by the charge pumping (CP) method, and degradation of the threshold voltage by these interface traps was studied. The generation process is found to follow the conventional ΔI_cp∼tⁿ relationship for a short period of stress and then shows a saturation behavior after longer stress times. The factors that determine the interface trap generation before and after saturation are analyzed. A new equation to describe the generation process is given.

The effect of La₂O₃ capping layer thickness on the hot-carrier degradation of n-channel metal–oxide–semiconductor field-effect transistors (n-MOSFETs) with high-k/metal gate stacks is investigated. The hot-carrier degradation is monitored by measuring the threshold voltage V_th, transconductance g_m, and subthreshold slope SS. As the thickness of the La₂O₃ layer increases, V_th degradation is enhanced regardless of whether the La₂O₃ layer is deposited above or below the HfSiO layer. The generation of interface traps induced by hot-carrier stress is intensified with an increase in the bottom capping layer thickness. On the other hand, the generation of oxide traps induced by hot-carrier stress is intensified with an increase in the top capping layer thickness.

In this study, the impact of embedded tip-shaped SiGe in the source/drain (S/D) region on individual trap behavior such as activation energy and depth from the SiO₂/Si interface of the 28 nm p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs) has been investigated on the basis of drain current random telegraph noise (RTN). The purpose of implementing tip-shaped SiGe S/D is to further increase channel stress because it provides a closer proximity of embedded SiGe to the channel. By characterizing RTN, we found that the pMOSFETs underwent uniaxial compressive strain that was provided by tip-shaped SiGe S/D, and the trap energy level being close to the channel valence band resulted in the trap located close to the Si/SiO₂ interface, as compared with the control device without embedded SiGe S/D.

The hot-carrier stress effects on the high-frequency performance characteristics of laterally diffused metal–oxide–semiconductor (LDMOS) transistors were investigated. A constant bias channel hot-carrier stress was applied at room temperature. After applying 3 h of hot-carrier stress, the on-resistance and saturation drain current degradations are 18 and 9%, respectively. However, the degradations of the cutoff frequency and maximum oscillation frequency were less than 2% when the devices were biased before the onset of quasi-saturation. In addition, we found that the degradations of high-frequency parameters are not related to the change in transconductance but to the changes in gate capacitances. Finally, S-parameter variations under hot-carrier stress were also examined in this study. The observations of S-parameter variations are important for RF power amplifier design.

This paper investigates the impact of dynamic stress on the reliability of a nanoscale n-channel metal–oxide–semiconductor field effect transistor (nMOSFET) with a SiON gate dielectric operating in a complementary metal–oxide–semiconductor (CMOS) inverter at an elevated temperature T. Experimental results indicate that the shift of threshold voltage V_th by dynamic stress is much larger than that by various static stresses in short channel nMOSFETs. Under a dynamic stress, the OFF-state stress generated interface traps and unfilled electron traps because of the OFF-state hot carrier effect due to drain induced barrier lowering (DIBL) at high T. Although the subsequent ON-state did not produce any new defects, it filled the electron traps, which increased the V_th abruptly. Consecutive application of OFF- and ON-state stresses caused a buildup of recoverable and permanent electron traps, and interface traps, thereby resulting in the significant increase in V_th. In addition, the dynamic stress degradation was frequency-independent up to 500 kHz and its impact on nMOSFET lifetime depends strongly on gate lengths. These results indicate that OFF-state induced defects are the main cause for dynamic stress degradation and can impose a significant limitation on CMOS device scaling.

In this study, we derive an analytical model of an electric potential of a double-gated (DG) fully depleted (FD) junctionless (J-less) transistor by solving the two-dimensional Poisson's equation. On the basis of this two-dimensional electric potential model, subthreshold current and swing can be calculated. Threshold voltage roll-off can also be estimated with analytical forms derived using the above model. The calculated results of electric potential, subthreshold current and threshold voltage roll-off are all in good agreement with the results of technology computer aided design (TCAD) simulation. The model proposed in this paper may help in the development of a compact model for simulation program with integrated circuit emphasis (SPICE) simulation and in providing deeper insights into the characteristics of short-channel J-less transistors.

Self-heating effects (SHEs) in silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is evaluated and an accurate measurement method for device temperature is developed using the four-point gate resistance measurement method. Although the method of using a polysilicon gate as a temperature sensor was proposed more than 20 years ago, the accuracy of the technique has not been checked. In this work, it is demonstrated that the channel temperature estimated by the conventional method is not accurate under some special conditions. The measurements of gate resistance under various biases revealed that the depletion of the polysilicon gate had a significant impact on gate resistance. We propose a method of accurately evaluating channel temperature, where the effect of poly depletion is successfully subtracted. At an input power of 5 mW the increase in channel temperature is approximately 30 K, corresponding to a thermal resistance of 6.0 K W^-1 m^-1.

A novel nonvolatile static random access memory cell is proposed that consists of four transistors and two spin-transfer-torque magnetic tunnel junctions (STT-MTJs). In the case of the NFET driver cell, the free layers of the magnetic tunnel junctions are connected to the transistors' sources and drains to make the cell read-disturb free. The static power is totally eliminated as the power line is shut down during data hold. The static noise margin of the cell is calculated based on the experimental data on MTJ switching that is enhanced from the resistive load SRAM cell due to the MTJ's switching operation. The cell size is estimated to become smaller than the 6-transistor SRAM cell when it is designed at 45 nm node and beyond owing to the MTJ's area shrink as well as the thinning of its tunnel dielectrics (MgO).

Highly scaled (22 nm-node) capacitorless single-transistor dynamic random access memory (DRAM) cell design is investigated via technology computer-aided design (TCAD) simulations. It is found that the gate-sidewall spacer width and operating voltages can be adjusted to reduce band-to-band tunneling (BTBT) and thereby increase data retention time for bipolar junction transistor (BJT)-based operation. Read current variations due to random dopant fluctuations (RDF) are investigated via three-dimensional Kinetic Monte Carlo (KMC) simulations. It is found that BJT-based operation is more robust to RDF effects than metal–oxide–semiconductor field-effect transistor (MOSFET)-based operation.

In this paper, a half select disturb free compact static random access memory (SRAM) cell with the stacked vertical metal–oxide–semiconductor field-effect transistor (MOSFET) is proposed, and the impacts on its cell size, stability and speed performance are evaluated. The proposed SRAM cell has a small cell size, which is 67% of the conventional eight-transistor (8T) SRAM cell, because of its stacked vertical MOSFET structure. It realizes a half select disturb free SRAM operation; therefore, a larger static noise margin of 5.9 times is achieved in comparison with the conventional 8T SRAM cell. It suppresses the degradation of the write margin, thus its write margin is 84.2% of the conventional 8T SRAM cell. Furthermore, it suppresses the degradation of the write time by 39% (0.249 ns). The proposed compact SRAM cell with the stacked vertical MOSFET is a suitable SRAM cell with a small cell size, immunity to the half select disturb, wide write margin and fast write time.

Recently, the three-dimensional (3D) vertical floating gate (FG) type NAND cell arrays with the sidewall control gate (SCG) structure are receiving attention to overcome the reliability issues of charge trap (CT) type 3D NAND. In order to achieve the multilevel cell (MLC) operation for lower bit cost in 3D NAND, it is important to eliminate reliability issues, such as the V_th distribution with interference and disturbance problems and V_th shift with retention issues. In this paper, we intensively investigated the disturbance problems of the 3D vertical FG type NAND cell with separated-sidewall control gate (S-SCG) structure for the reliable MLC operation. Above all, we successfully demonstrate the fully suppressed disturbance problems, such as indirect programming of the unselected cells, hot electron injection of the edge cells and direct influence to the neighboring passing cells, by using the S-SCG with 30 nm pillar size.

Practical consideration about performance and endurance of two transistor Fowler–Nordheim tunneling (2T-FN) embedded flash cell has been suggested to expand its application not only for subscriber identity module (SIM) but also new various uses in smart-phone. We present practical 35% improvement on endurance characteristics (ΔV_th) without any performance degradation.

The crystallization properties of phase-change memory (PCM) in the presence of thermal disturbances are investigated with a novel micro-thermal stage. It is found that the recrystallization time due to thermal disturbances significantly varies depending on how the PCM cell drifts. The longer crystallization time is obtained following additional resistance drift, which can be described by an increase of the effective activation energy for crystallization. The possibility of achieving better retention in a PCM cell by allowing the PCM cell to drift for a longer time is demonstrated in this work. The activation energy changes at a rate of more than 1 eV/decade with varying time intervals below a second. As the ambient temperature gets higher, the effect of resistance drift on the crystallization process is diminished with respect to the dominant crystallization process which has a higher crystal growth rate at elevated ambient temperatures.

This paper proposes a verify-programming method for the resistive random access memory (ReRAM) cell which achieves a 50-times higher endurance and a fast set and reset compared with the conventional method. The proposed verify-programming method uses the incremental pulse width with turnback (IPWWT) for the reset and the incremental voltage with turnback (IVWT) for the set. With the combination of IPWWT reset and IVWT set, the endurance-cycle increases from 48 ×10³ to 2444 ×10³ cycles. Furthermore, the measured data retention-time after 20 ×10³ set/reset cycles is estimated to be 10 years. Additionally, the filamentary based physical model is proposed to explain the set/reset failure mechanism with various set/reset pulse shapes. The reset pulse width and set voltage correspond to the width and length of the conductive-filament, respectively. Consequently, since the proposed IPWWT and IVWT recover set and reset failures of ReRAM cells, the endurance-cycles are improved.

This work compares the effects of SiN and Ta₂O₅ barrier layers in a multi-level phase change random access memory (PCRAM) cell. The PCRAM cell comprises a phase change material stack between a top and a bottom electrode. The phase change material stack comprises a nitrogen-doped Ge₂Sb₂Te₅ (NGST) layer on top of a thin barrier layer on an undoped GST layer. The thermal conductivity and electrical resistivity of the barrier layer affect multi-level switching performance in terms of endurance as well as power consumption. Extensive electrical characterization was performed on these PCRAM multi-level devices. Thermal analysis was also performed to investigate the thermal efficiency of each barrier layer. It was observed that for a constant barrier layer thickness of 1.5 nm, the endurance of the multi-level device with the SiN barrier layer was better than that with the Ta₂O₅ barrier layer; however, the multi-level device with the Ta₂O₅ barrier layer had a lower power consumption than that with the SiN barrier layer.

Phase change random access memory (PCRAM) is the most promising candidate for the next-generation nonvolatile memory. Recently, elevated-confined PCRAM using an elevated metal column was proposed as a promising approach to achieve lower RESET current. This paper studied the writing strategy to enhance the endurance of elevated-confined PCRAM through both experiment and simulation. Elevated-confined PCRAM incorporating Ge₂Sb₂Te₅ were fabricated and tested. The overwriting test showed that the failure mode of elevated-confined PCRAM was stuck SET. As diffusion, which is the main reason for stuck SET, is highly dependent on working temperature, writing strategies are investigated to minimize the over-heating in elevated-confined PCRAM. From the simulation results, it is found that RESET pulse width is more effective than RESET pulse amplitude in controlling of over-heating. The testing results showed that the endurance cycles can be improved from 10⁶ to 10⁸ with shorter and lower RESET pulse, which is consisted with simulation results.

We developed a comprehensive simulation program of phase change memory (PCM) including the electrical, thermal, phase change and percolation model. The set, reset and retention behavior for a typical thin film phase change material (GST) are simulated and evaluated. Both the resistance evaluation and the micro phase change process are simulated that can help to understand of the phase change physical mechanism. The influence of pre-existing grains on the retention is evaluated considering the pre-existing grains' amount and its distribution.

To improve the sensitivity of silicon photosensors to near-infrared light, we proposed a method in which the photosensor is illuminated from the side. That method allows the PN junction of the photodiode to be formed to a length that covers the entire depth of incident light penetration. The result is efficient collection of the photocharge produced by the injected light and improvement in quantum efficiency. We fabricated a 4.20 ×3.33 mm² test chip using a 0.35-µm complementary metal oxide semiconductor (CMOS) 1-poly 3-metal process. Because side illumination is used, the side of the chip is etched by high-speed deep reactive ion etching (D-RIE). For a 150-µm-long photodiode, the quantum efficiency to 970-nm wavelength near-infrared light is 28 times as high as for a conventional device. It was confirmed that the effectiveness of the proposed method increases with the wavelength of the incident light.

This paper presents a through-silicon-via (TSV) design methodology for three-dimentional solid-state-drive (3D-SSD) system with the 20 V boost converter. Although TSV technologies give compact packaging and high performance compared to the conventional wire-bonding technology, the parasitic resistors and capacitors of TSVs may cause the performance degradation. Additionally, since the number of the activated NAND chip is dynamically changed as access patterns from real processor, the optimum design point for the boost converter is also moved according to the situation. Then, the clustering method with two different sizes of Cu-TSVs and the adaptive TSV number controlling technique for polycrystalline silicon TSVs are proposed to reduce the parasitic resistors and capacitors. With the cluster structure and Cu-TSVs, the performance of the proposed 3D-SSD is improved by ∼10%. Furthermore, the adaptive TSV number controller enhances the performance up to 2 times higher for poly-Si TSV case by reducing the parasitic elements due to TSVs.

A wide-frequency-range phase-locked loop (PLL) with subharmonic injection locking is proposed. The PLL is equipped with a wide tunable ring-type voltage-controlled oscillator (ring VCO), frequency dividers, and a doubler in order to the widen injection-locked tuning range (ILTR). In addition, high-frequency injection signals are used to improve phase noise, which is supposed to be generated by a reference PLL. The proposed circuit is fabricated by using a 65 nm Si complementary metal oxide semiconductor (CMOS) process. The measured frequency tuning range is from 1.2 to 17.6 GHz with a frequency doubler and dividers. The phase noise at 14.4 GHz (=32×450 MHz) with injection locking was -109 dBc/Hz, which shows a 21-dB reduction compared with that in the case without injection locking.

Most microcontrollers (MCUs) have a real-time clock function driven by a 32-kHz crystal oscillator. A low-power 32-kHz crystal oscillator for operation in battery-operated MCUs over a wide voltage range (1.0–5.5 V) is described. The circuit features a proportional to absolute temperature (PTAT) bias-current generator to ensure an oscillation margin and an adaptive comparator for detecting small oscillation signals with little effect from by process and temperature variations. Experimental results indicate that the circuit achieves a small operating current of only 220 nA while ensuring a 10-times oscillation margin with a low-C_L (3.1 pF) quartz crystal, providing sufficient noise tolerance and quick start-up. The duty cycle is 40–60% and start-up time is less than 0.6 s. This circuit is expected to realize the smallest MCU standby current of 420 nA.

A digital processor dedicated to edge-based image vector generation has been developed aiming at real-time image recognition. The processor consists of an on-chip memory and 16 single instruction multiple data (SIMD) processing elements. The capacity of the on-chip memory as well as the overhead for starting the processing have been minimized by introducing a seamless data transferring scheme from memory to processing elements. The 16 SIMD processing elements work together either as accumulators or as shift registers, thus achieving a very efficient generation of two different kinds of feature vector: projected principal-edge distribution (PPED)[3,4] and averaged principal-edge distribution (APED).[5] Concurrent use of these two vectors is shown to be very important for robust image recognition.[5] The chip was fabricated using 0.18-µm complementary metal oxide semiconductor (CMOS) technology and the generation of 64-dimension PPED and APED vectors at 84.7 and 83.9 fps, respectively, from video graphics array (VGA) size images was demonstrated at 62.5 MHz.

An asynchronous pulse transmitter is proposed to achieve low power in inductive-coupling link. The conventional asynchronous transmitter, H-bridge inductive-coupling transmitter, consumes large static (DC) current consumption. Therefore the transmit power dissipation is dominant in the total inductive-coupling power dissipation. The proposed pulse inductive-coupling transmitter eliminates the static (DC) current consumption. It provides linear power scalability which significantly reduces the power consumption especially at low data rate operation for low-power mobile applications. To verify the proposed technique, we designed and fabricated test chips in TSMC 0.18 µm complementary metal oxide semiconductor (CMOS) technology. Both proposed pulsed transmitter and conventional H-bridge transmitter is implemented in the test chip for comparison. Power reduction to 1/4 at 1.5 Gbps and 1/60 at 100 Mbps is achieved compared to the conventional transmitter. Also a crosstalk immune inductive-coupling receiver is presented for low-power relayed transmission using the proposed pulse transmitter. Crosstalk guard circuit is implemented in the receiver to ignore crosstalk. Data is successfully transferred using relayed transmission with proposed transceiver at up to 400 Mbps.

We propose a nonvolatile 16-bit/32-bit magnetic tunnel junction (MTJ) based binary counter with fine-grained power gating scheme suitable for MTJ. We estimate the power consumption of the proposed counter by using simulation program with integrated circuit emphasis (SPICE) simulation. The power of the proposed 16-bit/32-bit counter is 59.1 and 72.5% smaller in case of 45 and 16 nm node, respectively, than that of the conventional complementary metal oxide semiconductor (CMOS) counter at low frequency (100 Hz). The proposed nonvolatile 32-bit counter achieves lower power at operating frequencies up to 49 kHz and 4 MHz in the case of 45 and 16 nm node, respectively, in comparison with the conventional CMOS counter. Moreover, we propose a hybrid 32-bit counter that is constructed with CMOS counter units for the beginning stages and nonvolatile MTJ based counter units for the latter stages. It achieves a lower power at operating frequencies up to 1 GHz than the conventional CMOS counter for 16 nm node. As a result, clear scalability of the proposed MTJ based multi-bit counter is obtained from the viewpoint of suppressing power.

In this paper, a high-voltage-tolerant level converter for embedded complementary metal–oxide–semiconductor (CMOS) nonvolatile memories is proposed. The level converter circuit includes a high-voltage driver and a level shifter, which makes use of 1×V_DD devices to generate 2×V_DD signals without overstress. In addition, it features one select signal to make the level converter have the tri-state. The high-voltage driver efficiently stacks two transistors to allow a voltage drop of V_DD for each transistor, which helps maximize the driving ability. The level shifter using the cross-coupled structure with small metal–oxide–semiconductor (MOS) capacitors drives the high-voltage driver without the "preconditioning" process. The level converter implemented using the 0.35 µm CMOS process on the area of 0.002 mm² was measured at V_DD = 3.5 V to generate the output signal swinging from 0 to 7 V.

This paper presents a two-stage, two-phase, p-channel metal–oxide–semiconductor field-effect transistor (PMOSFET) charge pump with special two-step clocks for ripple reduction. The ripple voltage can be reduced by adjusting the overdrive voltage during charge transfer. The charge pump including the circuit of the proposed clocks and 5 pF boosting capacitance was fabricated using 0.35 µm complementary metal–oxide–semiconductor field-effect transistor (CMOSFET) technology in an area of 0.182 mm². With the new clock scheme, high voltage gain and driving capacity without overstress of the transistors are preserved. The experimental results reveal that the output voltage ripple is reduced from 23.2 to 12.8 mV for an output current of 36 µA at a frequency of 10 MHz and a supply voltage of 1.8 V, which indicates a 45% ripple reduction without increasing filtering capacitance.

In this paper, we describe the development of a circuit system that enables the offset calibration of an operational amplifier (op-amp) circuit after production. A closed-loop feedback system was developed to realize high-speed and accurate offset calibration action. For the digital-to-analog converter (DAC) which occupies most of the area for the additional calibration circuit, the Folded-Alternated Resistor String DAC was developed. This reduced the area by more than 50% and realized low power consumption while maintaining the same accuracy as a conventional type of DAC. The fabrication with standard 0.35 µm complementary metal oxide semiconductor (CMOS), followed by actual measurement, has confirmed that the offset can be confined to no more than 1.5 mV using the new calibration circuit. With this technique, miniaturization of a whole op-amp system can be achieved, because the layout size of each circuit consisting of op-amps can be reduced when using this offset correction circuit.

AlN films deposited by RF magnetron sputtering are applied to AlGaN/GaN metal–insulator–semiconductor heterostructure field-effect transistors (MIS-HFETs) as a gate dielectric. X-ray photoelectron spectroscopy (XPS) was used to characterize the AlN films, showing their chemical bonds and the bandgap by N 1s electron energy loss spectroscopy. The AlGaN/GaN MIS-HFET with a gate length of 150 nm was successfully fabricated, exhibiting low gate leakage currents for both reverse and forward biases, which are at least four orders of magnitude lower than those of reference Schottky-HFETs. Although these results support the possibility of sputtering-deposited AlN as a gate insulator, there are AlN/AlGaN interface states unfavorable for device performance, which were investigated by the frequency dispersion in the capacitance–voltage (C–V) characteristics.

Gate leakage mechanism of the HfAlO plasma-PH₃ passivated and non-passivated In_0.53Ga_0.47As N-channel metal–oxide–semiconductor field-effect transistors (N-MOSFETs) have been evaluated, in order to correlate the quality of the oxide deposited with the gate leakage mechanisms observed. At temperatures higher than 300 K, trap-free space charge limited conduction (SCLC) mechanism dominates the gate leakage of passivated device but non-passivated device consists of exponentially distributed SCLC mechanism at low electric field and Frenkel–Poole emission at high electric field. This Frenkel–Poole emission is associated with energy trap levels of ∼0.95 to 1.3 eV and is responsible for the increased gate leakage of non-passivated device. In addition, the electrical properties of the non-passivated device has also been extracted from the SCLC mechanism, with the average trap concentration of the shallow traps given as 1.3×10¹⁹ cm^-3 and the average activation energy given as ∼0.22 to 0.27 eV. The existence of these defect levels in non-passivated device can be attributed to the interdiffusion of Ga/As/O elements across the HfAlO/In_0.53Ga_0.47As interface. On the other hand, passivated device does not contain Frenkel–Poole emission nor exponentially distributed SCLC mechanism, indicating a reduction in traps in the bulk of the oxide. In addition, the temperature dependent characteristics of off-state leakage have also been evaluated to provide insight into the off-state mechanism. The off-state leakage of both passivated and non-passivated device is determined by junction leakage, with Shockley–Read–Hall mechanism being its main contributor, and has activation energy of 0.38 eV for passivated device and 0.4 eV for non-passivated device. From I_d∝T^-0.37 observed for passivated device, in comparison to I_d∝T^-0.18 for non-passivated device, we have further confirmed the phonon scattering dominance of the passivated device at high electric field.

In this paper, we report the first demonstration of In_0.53Ga_0.47As n-channel metal–oxide–semiconductor field-effect transistors (n-MOSFETs) with a shallow metallic source/drain extension (SDE) and offset n⁺ regions for leakage suppression. A SDE-last process flow was developed, i.e., the Ni–InGaAs metallic SDE was formed last, after formation of n⁺ doped source/drain (S/D) regions. The n⁺ S/D regions were offset from the gate edge with the use of sacrificial spacers. After spacer removal, self-aligned highly-abrupt Ni–InGaAs SDE was formed. Junction leakage between drain and body was effectively suppressed by ∼40 times by the n⁺ S/D regions.

We investigated zinc oxide (ZnO) thin films prepared by plasma assisted atomic layer deposition (PA-ALD), and thin-film transistors (TFTs) with the ALD ZnO channel layer for application to next-generation displays. We deposited the ZnO channel layer by PA-ALD at 100 or 300 °C, and fabricated TFTs. The transfer characteristic of the 300 °C-deposited ZnO TFT exhibited high mobility (5.7 cm² V^-1 s^-1), although the threshold voltage largely shifted toward the negative (-16 V). Furthermore, we deposited Al₂O₃ thin film as a gate insulator by PA-ALD at 100 °C for the low-temperature TFT fabrication process. In the case of ZnO TFTs with the Al₂O₃ gate insulator, the shift of the threshold voltage improved (-0.1 V). This improvement of the negative shift seems to be due to the negative charges of the Al₂O₃ film deposited by PA-ALD. On the basis of the experimental results, we confirmed that the threshold voltage of ZnO TFTs is controlled by PA-ALD for the deposition of the gate insulator.

We investigated the electrical characteristics of 4H-SiC n- and p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with ion-implanted buried channels. The effects of the impurity concentrations of the buried channel (C_bc) on their electrical characteristics were quite different. In the case of n-channel MOSFETs, the threshold voltage decreased and the channel mobility increased with an increase in C_bc. On the other hand, in the case of p-channel MOSFETs, the threshold voltage and the maximum channel mobility were almost independent of C_bc. The conduction mechanism of the buried-channel MOSFETs is discussed in this paper.

We investigate a solid state reaction between Ge and Ni–InGaAs on n⁺ In_0.53Ga_0.47As and its effects on the contact resistance of Ni-based contacts on InGaAs. This reaction was performed by isochronous annealing of Ge on Ni–InGaAs at temperatures ranging from 400 to 600 °C in N₂ ambient. It was found that a regrown InGaAs layer rich in Ge was formed below the metal contact. Compared with Ni–InGaAs contact, more than 60% reduction in contact resistance on Si-implanted n-In_0.53Ga_0.47As was achieved after annealing at 600 °C. This contact structure was characterized by secondary ion mass spectroscopy, high resolution transmission electron microscopy, X-ray diffraction, and scanning electron microscopy.

Using sputtering-deposited AlN insulator films, we fabricated and analyzed AlN/GaAs(001) and AlN/Ge/GaAs(001) metal–insulator–semiconductor (MIS) structures; the former is obtained by the direct deposition of AlN on GaAs, while the latter includes a Ge interlayer between AlN and GaAs. By current–voltage (I–V) measurements, we obtained similar good insulating properties for both MIS structures. On the other hand, we observed rather different frequency dispersions in the capacitance–voltage (C–V) characteristics of the MIS structures; the AlN/Ge/GaAs(001) MIS structure exhibits a significantly smaller dispersion than the AlN/GaAs(001) MIS structure, attributed to a smaller interface state density, as confirmed by analysis using the conductance method. From the X-ray photoelectron spectroscopy analysis results of the MIS interfaces, we found that, in comparison with the AlN/GaAs(001) interface, the AlN/Ge/GaAs(001) interface exhibits suppressed As deficiency and Ga–O bonding, with an indication of their relation to interface states.

We propose and a novel InGaAs/InAlAs multiple quantum well (MQW) Mach–Zehnder (MZ) modulator with a single microring resonator, and a significant reduction of driving voltage is demonstrated for the first time. The modulator is driven by the quantum-confined Stark effect (QCSE) in the MQW and the driving voltage of the proposed modulator is expected to be significantly reduced by the phase-shift-enhancement effect in the microring. A waveguide structure was grown by solid-source molecular beam epitaxy and fabricated by inductively coupled plasma etching. A directional coupler with a shallow gap is employed to control the coupling parameters between a busline and the microring waveguide. An asymmetrical splitter was used as an input coupler to prevent the degradation of the extinction ratio of the MZ modulator. The extinction ratio of the fabricated microring MZ modulator was approximately 17.5 dB. The product of half-wave voltage and phase shifter length V_πL was 2.0 Vmm in static modulation. This value was one-third that of a conventional MZ modulator with the same waveguide structure.

We report on reduced threshold current and enhanced extinction ratio of a magnetically controllable Fe₅₀Co₅₀–InGaAlAs/InP nonreciprocal semiconductor laser. The improved device performance was consistent with calculated results for the modified layer structure and the use of ferromagnetic metal (Fe₅₀Co₅₀). The fabricated laser showed a threshold current 2.0 times smaller than our previous device having Fe. The extinction ratio, defined as the change in light intensity upon magnetization reversal, increased upon the appearance of the first-order transverse mode and reached 46% at a current of 100 mA. The reduced threshold current and enhanced extinction ratio should be useful for realizing low-operating-current, all-optical, robust signal processing devices using nonreciprocal semiconductor lasers.

We propose a new p-down inverted avalanche photodiode (APD) structure suitable for a scaled APD with smaller junctions. The inverted APD structure has an edge-field buffer layer to prevent undesirable edge breakdown and suppress the excess surface leakage current associated with the InGaAs mesa surface. The fabricated back-illuminated InAlAs/InGaAs APDs show excellent multiplication characteristics without edge breakdown. An f_3dB of 27 GHz and a GB product of 220 GHz are obtained for these APDs.

The responsivity characteristics of heterojunction phototransistors (HPTs) with a strained InAs/InGaAs multiquantum well (MQW) absorption layer inserted in the base or collector are investigated. It is shown that although the hetero-emitter injects hot electrons into the base, the effective electron diffusion length in the base with MQWs becomes five times lower than that of a base without MQWs. This results in higher current gain for HPTs with MQWs in the collector. In addition, enhanced absorption coefficient due to excitonic absorption is observed only on HPT with MQW in the collector. Due to these two factors, a high responsivity of more than 10 A/W is realized at a wavelength around 2.35 µm for the device with MQWs in the collector.

The waveguide design of a GaAs based, epitaxially regrown photonic crystal surface emitting laser is discussed so as to optimise the coupling of the photonic crystal and the mode overlap with the quantum wells. Design criteria include the positioning of the quantum well and the photonic crystal layers, and the effect of varying aluminium composition in the lower cladding layer. Room-temperature, pulsed laser oscillation is demonstrated.

In this paper, a highly sensitive gate/body-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with an overlapping control gate is proposed. The proposed photodetector has an overlapping control gate that makes it possible to control the sensitivity of the proposed photodetector. This sensitivity controllability extends the dynamic range and provides a high sensitivity in a low-light environment. The body of the proposed gate/body-tied PMOSFET-type photodetector is connected to the floating gate, and the control gate is placed on top of the floating gate. The proposed device was fabricated using a 0.35 µm standard complementary metal oxide semiconductor (CMOS) process. The amplified photocurrent of the proposed device was more than 100 times larger than that of a conventional n+/p-sub photodiode with the same area. The area of the proposed photodetector is 3.8×4.4 µm², which is 24% smaller than that of a conventional gate/body-tied PMOSFET-type photodetector with a transfer gate. Therefore, the proposed photodetector can be suitable for high-sensitivity active pixel sensors (APSs) because of its much higher responsivity than that of a conventional n+/p-sub photodiode.

Films of Er₂O₃ grown on Si(111) substrates by rf-magnetron sputtering were characterized by synchrotron radiation X-ray diffraction and photoluminescence spectroscopy in spectral and time domains. We measured the photoluminescence and the intensity ratio of the peaks in the photoluminesence as a function of temperature at the excitation wavelength of 800 nm. We determined the energy levels of Er³⁺ ions in poly crystal Er₂O₃ and revealed energy transfers from C₂ to C_3i sites in the Er₂O₃ on the basis of a simple theory.

A sandwiched sub-nano separator (SSNS) growth technique of producing high-density, high-quality InAs/InGaAs quantum dot (QD) structures on GaAs substrates is proposed. The SSNS technique achieved a density of 8.2 ×10¹⁰/cm² by suppressing giant dot formation. The QD structures fabricated by the SSNS technique were used to form a ridge-type waveguide QD optical gain chip for O-band optical gain. With this chip, we successfully demonstrated the generation of a wavelength-tunable fine-tooth optical frequency comb in the O-band from a QD optical frequency comb laser (QD-CML), and synchronized short-optical-pulse generation (∼14 ps) with gigahertz-order repetition from a hybrid mode-locked QD-CML. We also successfully demonstrated a wavelength tunable QD-ECL with a wide wavelength tuning range (1265–1320 nm) and a narrow linewidth (210 kHz) in the O-band. It is expected that these QD coherent light sources will become attractive photonic devices for many scientific applications in the 1.0–1.3 µm waveband.

The effect of the quantum dot (QD) deposition temperature is discussed for dot-in-a-well (DWELL) structures with a view to their optimization for broadband applications. Atomic force microscopy (AFM) analysis allows the measurement of the quantum dot and the defective island density. The reduced QD growth temperature results in broad emission spectrum and increased defective island density. Reduced electroluminescence efficiency, higher reverse leakage currents, and lower reverse breakdown voltage could be correlated to the presence of the defective island density. Maximal output power is obtained for devices with a QD growth temperature of 500 °C, whilst the preferred spectral shape and QD density is obtained at the lowest temperature, 470 °C. To benefit from broad emission bandwidth, the growth conditions need to be further optimized to avoid, or at least reduce, the defective island density.

We investigate the characteristics of oxide film obtained by wet oxidation of Al_xGa_1-xAs with its Al concentration x between 0.55 and 0.99. 300-nm-thick Al_xGa_1-xAs grown on GaAs substrate by molecular beam epitaxy is wet-oxidized in a furnace at 410 °C for 120 min. Samples having x greater than 0.8 are confirmed to be oxidized from their observation, examined by X-ray diffraction showing the vanished crystallographic diffraction peaks. Scanning electron microscopy, X-ray reflectivity, and spectroscopic ellipsometry study determines the thickness, density and refractive index of the oxide films.

The authors report on the fabrication of MnAs/GaAs hybrid nanowires by combining selective-area metal–organic vapor phase epitaxy of GaAs nanowires and "endotaxy" of MnAs nanoclusters. MnAs nanoclusters are embedded in the six ridges of hexagonal GaAs nanowires as a result of endotaxy. From the cross-sectional characterizations by transmission electron microscopy, the average width of MnAs nanoclusters with the hexagonal NiAs-type crystal structure and the average depth in GaAs nanowires are estimated to be about 10 and 8 nm, respectively. The magnetic responses detected from the reference samples grown on planar GaAs (111)B layers show that ferromagnetic MnAs nanoclusters are formed. The diameter of nanoclusters grown in GaAs nanowires increases with decreasing growth temperature and/or increasing distance between the GaAs nanowires, while the density of nanoclusters increases with increasing growth temperature. It is found that the diameter and density of nanoclusters are strongly influenced by the gas supplied during the decrease in temperature after the nanocluster growth.

200-nm-thick N-polar AlN layers were grown on 6H-SiC(000) substrates with 6-bilayer-high steps by molecular-beam epitaxy. During N-polar AlN growth, multinucleation growth occured easily, increasing the surface roughness of AlN. By reducing supersaturation (nucleation probability), the surface roughness was improved. The FWHMs of (0002) and (01) ω-scan diffraction peaks of the AlN layer were 120 and 210 arcsec, respectively. The formation of stacking-mismatch boundaries (SMBs) was successfully suppressed by step-height control of the SiC substrate and the initial layer-by-layer growth. Most of the threading dislocations (TDs) were generated at the step edges of the SiC surfaces. The density of TDs in the AlN layers was 2×10⁹ cm^-2.

We investigated the effects of initial In coverage for the preparation of InSb bilayer on electrical properties of InSb films grown by surface reconstruction controlled epitaxy. The electron mobility of the InSb films was affected by the initial In coverage of the In-induced surface reconstruction on Si(111) surface. Electron mobility increased with the increase in the initial In coverage up to 1.5 monolayers (ML), and decreased with further increase in In coverage. The InSb film grown with an optimal initial In coverage of 1.5 ML has a high electron mobility of about 40,000 cm²/(V·s) at room temperature. This may be due to the reduction of the 2×1-Sb surface phase or In islands on the surface after the preparation of the InSb bilayer, which cause dislocations in the film. Therefore, the perfectness of the order of atomic planes in Si–Sb–In is very important for a uniform InSb/Si interface formation before the subsequent InSb molecular beam epitaxy (MBE) growth.

Metal-induced lateral crystallization (MILC) of amorphous Si using a nickel disilicide catalyst at temperatures up to 770 °C is investigated to produce high-quality polycrystalline Si films in a short period, while 670 °C is the maximum temperature allowed for processing using non alkaline glass substrates. Investigation of crystallization kinetics by isothermal annealing experiments provides activation energy values of 2.3 and 3.6 eV for MILC growth and spontaneous nucleation of amorphous Si, respectively. These values indicate that a MILC region of about 30 µm, which is large enough to place transistor circuits, can be grown by annealing for 15 min at 670 °C, which almost agrees with experimental results. N-channel thin-film transistors are fabricated on MILC films. An average carrier mobility of about 200 cm²·V^-1·s^-1 is obtained from the MILC film crystallized at 670 °C.

Amorphous silicon (a-Si) films deposited by plasma-enhanced chemical vapor deposition (PECVD) were patterned to strips with a width ranging from 1 to 50 µm, and irradiated with an atmospheric pressure micro-thermal-plasma-jet (µ-TPJ) to induce high-speed lateral crystallization (HSLC). From electron backscattering diffraction patterns (EBSPs), the growth of ∼20-µm-long single grains was observed in a narrow line of 1 µm width under a µ-TPJ scan speed as high as 4000 mm/s. TFTs with a large channel length (L)/width (W) of 40 µm/50 µm show a field-effect mobility (µ_FE) of 284 cm² V^-1 s^-1, whereas decreasing W monotonically increased µ_FE to 477 cm² V^-1 s^-1 at W = 2 µm. By applying µ-TPJ to strip a-Si films, we can form single-crystalline Si at predetermined positions and obtain TFTs with reasonably high performance. We confirmed that HSLC is applicable to a-Si films on conventional glass substrates without crack generation by either inserting a buffer layer underneath a-Si films, or heating the samples during µ-TPJ irradiation. A new positioning method using a Si slit mask is also demonstrated. TFTs fabricated on glass with a buffer layer inserted underneath the a-Si films show a high µ_FE of 267 cm² V^-1 s^-1.

The electro-optical (EO) effect of the ZnMgTe/ZnTe waveguide structure grown on (001) ZnTe single crystal substrates using molecular beam epitaxy (MBE) was studied. The EO properties of ZnTe were investigated by optical confinement with an electric field. The effect of the applied electric field and the rotation of polarization wave effect are discussed.

We investigated multi-electron wave packet dynamics considering Coulomb interaction under applied electric field by solving the time-dependent Hartree–Fock equation. We confirm that the Coulomb interaction works to prolong the lifetime of the wave packets. Moreover, we find that the applied electric field also prolongs the wave packet lifetime. This indicates that the particle nature of electrons will be dominant in future nanodevices under high electric field.

We present a theoretical model for electron tunneling through a single Si-donor state in a resonant tunneling diode with a Si δ-doped layer in the central plane of the quantum well, under tilted magnetic field B. The tunneling current is calculated with a transfer Hamiltonian method by assuming that the current is limited by the emitter barrier. Through a variational calculation of the donor state, we show that the component of B parallel to the direction of current, B_|| , provides us with a means of compressing the donor wavefunction in the quantum-well plane. We also show that by measuring the current as a function of the perpendicular component B_⊥ one can probe how the magneto-compression induced by B_|| affects the spatial form of the donor wavefunction. We compare the theoretical results with the experiment.

Tri-gate channel structures were applied to polycrystalline silicon (poly-Si) thin-film transistors (TFTs) fabricated by continuous-wave (CW) laser lateral crystallization (CLC). We had two objectives in using tri-gate structures in CLC poly-Si TFTs. One was the enhancement of effective electron mobility (µ_eff) by using the tensile strain induced by the CLC process and the lateral-strain-relaxation effect in tri-gate structures. The other was the reduction of µ_eff variation caused by increasing the number of surfaces with different crystal orientations by up to a factor of three. By applying tri-gate structures to CLC poly-Si TFTs, both 8% µ_eff enhancement and 41% reduction of µ_eff variation were achieved at the surface carrier density of 5×10¹² cm^-2. These results are expected to be useful for the device size shrinkage of high-performance poly-Si TFT circuits.

The resistive switching properties of the ZrO₂ memory devices with bottom electrode modification by using Au nanodots are investigated in this study. The regular arrays of Au nanodots are fabricated on Pt bottom electrode by nanosphere lithography. Due to the tip of the Au nanodots on the Pt bottom electrode, it causes the higher electric field within the ZrO₂ film above the nanodots due to reduced effective film thickness and induces the localized conducting filaments easily. The operation parameters' variation for switching devices is, therefore, suppressed with lower operation voltage and resistance ratio. Long retention time (>10⁶ s) and stubborn nondestructive readout test (>10⁴ s) at room temperature and 150 °C are also demonstrated in this device.

We demonstrate photon antibunching from a wavelength controlled quantum dot single-photon source with a side gate. The photoluminescence peaks from the quantum dots embedded in the side-gate structure are clearly identified as a neutral exciton and a neutral biexciton by the studies of excitation-power dependence, polarization dependence, and photon correlation. The neutral exciton energy is controlled by the side gate via the quantum confined Stark effect. Measurement of the second-order autocorrelation function indicates g⁽²⁾(0) = 0.07 at 0 V, 0.14 at 0.8 V, and 0.24 at 0.9 V. The results show g⁽²⁾(0)s are below the 0.5 limit necessary for classification as a single photon source even under applied gate voltage. We also show a biexciton-exciton cascade which can be used to create entangled photon pairs.

We present the electronic properties of a triple quantum dot molecule embedded inside a sub-micron mesa, made from a quadruple-barrier triple-quantum-well structure, and surrounded by a single gate electrode. We outline the design principles of the quadruple-barrier triple-quantum-well structure and calculate the energy of the three lowest states as a function of center well thickness. We observe regular and irregular shaped Coulomb diamond regions similar to those for double quantum dot devices. Variation in the Coulomb blockade region shape is introduced by fluctuation in the offset energies between the quantum dots likely associated with device processing and random impurity potential in the material. We also present Coulomb blockade patterns calculated with a constant interaction model for sequential tunneling through the three series-coupled quantum dots.

Quantum dots (QDs) are one of the promising candidates of interconnection between electromagnetic field and electrons in solid-state devices. Dark states appear as a result of coherence between the electromagnetic fields and the discrete energy levels of the system. Here, we theoretically solve the steady-state solutions of the density matrix equations for a thee-level double QD system and investigate the condition of the appearance of a dark state. We also numerically show the appearance of the dark state by time-dependent current characteristics.

We investigate cross spectral density between tunneling currents through closely spaced point contacts (PCs) in a semiconductor heterostructure. Analysis of 1/f noise, which originates from background charge fluctuations, is expected to reveal the characteristics of a charge detector and screened Coulomb potential in the device. However, the common resistance in the measurement circuit and the leads of the PCs causes a significant negative correlation. We find that this negative correlation is enhanced when the common electrical channel becomes so narrow that it has only a few one-dimensional conductive modes. Our finding suggests the importance of the circuit environment in integrating multiple charge detectors.

Columnar type-II GaSb quantum dots (QDs) in GaAs are studied theoretically to clarify how electronic states are affected by the interface grading caused by the interdiffusion of Sb and As. Truncated-cone-shaped QD stacks are analyzed as a function of the diffusion length L_d, where the stacking dot number N is varied from 1 to 4. The energies of heavy- and light-hole ground states E_hh and E_lh, respectively are calculated. The heavy hole is the lowest state when N = 1 and 2, and E_lh is lower than E_hh for N = 4. When N = 3, the lowest state changes from light holes to heavy holes as L_d increases. We also evaluate the overlap Θ between the electron and hole wave functions, which determines the strength of optical transition. It is found that Θ changes by 2–3 orders of magnitude depending on N and L_d.

Small size and good coupling control between dots are the key parameters for useful coupled quantum dot devices. Using a new approach of electrostatically defined silicon double quantum dot device recently proposed, we design and simulate a silicon quantum dot structure that exhibits multi functionality. Control on potential tunnel barrier using side gates, as well as the preparation of series-coupled and parallel-coupled double quantum dot structure are demonstrated and explained by numerical simulation on electron distribution profile.

We investigate an efficient structure for the near-band-edge C-plane emission of a deep-ultraviolet light-emitting diode using first-principles calculations based on density functional theory. We find that a negative crystal-field splitting in the AlN bulk is converted to a positive one in the AlN/GaN superlattice with more than one GaN monolayer. The quantum-confinement Stark effect is minimized by decreasing the GaN thickness down to 1–2 monolayers. The optical matrix element of such superlattices is 57% relative to the GaN bulk, and its C-plane component accounts for the majority of the total; the emission wavelength is found to be 224 nm. The reverse of the negative Δ_CR in the AlN/GaN superlattice is ascribed mainly to two factors: quantum confinement effects and the internal parameter u. Our calculations demonstrate that using the AlN/GaN superlattices with one or two GaN monolayers significantly improves the near-band-edge C-plane emission of deep-UV light-emitting diodes.

This study elucidates the electron emission properties of GaAsN/GaAs quantum well containing N-related localized states under illumination. The N-related localized states in a GaAsN quantum well (QW) are identified as both optical and electrical electron trap states. The mechanisms for the responses of current–voltage (I–V) measurement under illumination and photocapacitance are investigated. N-related localized states in GaAsN QW can extend response range and response sensitivity on photocapacitance, and produce an additional current path for photo-generated electron–hole pairs. Furthermore, exactly how illumination influences the electron emission rate of GaAsN QW electron state is examined. The electron emission rate of GaAsN QW electron state can be modulated by different incident photon energy, which is due to the modulation of depletion width of the bottom GaAs.

p-Type tunneling transistors with polycrystalline silicon were fabricated, and their electrical characteristics were studied. The temperature dependence of the tunneling current proves that the current of our device is indeed due to the band-to-band tunneling effect, rather than to the avalanche effect. The reliability of the polycrystalline silicon (poly-Si) tunneling transistors with a grain direction effect due to the active layer formed by the sequential lateral solidification (SLS) growth technique was examined. The device with a channel parallel to the grains has a high band-to-band tunneling current, low leakage current, and threshold voltage stability with constant current stress. Promising poly-Si tunneling transistors with a gate-controlled current and a low off-current have attracted attention for some applications such as in display backplanes, three-dimensional integrated circuits (3D-ICs), and microwave circuits in the future.

Optical electric-field-induced second-harmonic generation (EFISHG) measurement was employed for studying interfacial processes in pentacene/C₆₀ double-layer organic solar cells (OSCs). Results showed that charging and discharging on the double-layer interface by photoillumination were nonreversible, and a recharging process continued after the illumination stopped. The Maxwell–Wagner model analysis revealed that the photoconductance change is responsible for this anomalous interfacial recharging. The results of impedance spectroscopy (IS) analysis supported this conclusion.

In this study, we systematically investigate the effects of post-annealing on the structural, electrical, and optical characteristics of indium molybdenum oxide (IMO) films. The incorporation of IMO films into organic solar cells (OSCs) is further studied. The optimum content of Mo is 2.36 wt %. Furthermore, a significant improvement in crystallinity, surface morphology, electrical resistivity, and optical transmittance is observed after thermal annealing. The lowest resistivity is obtained with post annealing at 300 °C for 140 s. The OSC utilizing the IMO electrode shows an efficiency of up to 3.77%, which is higher than that of the OSC utilizing the ITO electrode. The diffusion length of the carriers in the OSC is approximately 10 nm. Thus, the higher efficiency can be explained by the smoother surface morphology of the post annealed IMO electrode. These results indicate that the novel IMO films with superior material properties have enormous potential applications for solar cells.

The high fill factor (FF) and high power conversion efficiency (PCE) of organic solar cells (OSCs) were investigated using an inorganic/organic stacked hole-transporting layer (HTL) of vanadium oxide (V₂O₅)/poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) between indium–tin oxide (ITO) and an active layer. The OSC configuration comprises ITO/V₂O₅/PEDOT:PSS/poly(3-hexylthiophene):phenyl C61-butyric acid methylester (P3HT:PCBM)/LiF/Al. The FF and PCE are 44 and 2.67% under simulated AM1.5G illumination of 100 mW/cm², which are approximately double and tenfold, respectively, greater than those of a conventional device without the buffer layer. The V₂O₅/PEDOT:PSS stacked HTL provides a smooth film surface for coating the P3HT:PCBM active layer, in addition to its stepwise hole-transporting configuration, subsequently increasing charge carrier transporting capability and extracting holes from the active layer.

We have investigated the incident-photon-to-current conversion efficiency (IPCE) of thin films of poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl-C₆₁-butyric acid methylester (PCBM) as a function of film thickness, in the presence or absence of silver nanoparticles (AgPs) between the films and the indium–tin-oxide (ITO) electrode. The thickness of the film was evaluated by atomic force microscopy. The absorption and photocurrent action spectra of the films were measured to investigate the effect of the thickness of the P3HT:PCBM film. The results show that IPCE increased steeply in thinner films and the optimal range of thicknesses of the P3HT:PCBM film was 50–120 nm. In this optimal range, the IPCEs were 1.5–1.8 times larger in the presence of AgPs.

We have developed a pressure annealing technique for fabricating low-work-function metal patterns on plastic substrates. The pressure annealing technique can destroy the metal oxide layer and can form a conductive layer on printed metal patterns. Furthermore, we have confirmed that a binary solid solution is easily formed on metal patterns including two kinds of metal particles by using the pressure annealing technique. Changing the composition ratio of the binary metal paste led to the work function control of the pressure-annealed metal patterns. The formation of the binary solid solution was confirmed by X-ray diffraction (XRD) analysis, and work function was measured by photoelectron emission spectroscopy. In the case of the binary metal paste of Cu and Zn, we have succeeded in controlling work function from 3.8 to 5.0 eV. Since the Cu–Zn paste is composed of relatively cheap metals, this would be applicable to large-scale flexible electronic devices.

Organic ferroelectric field-effect transistor (FET) memories have been fabricated using pentacene as the semiconductor and a flat poly(vinylidene fluoride–tetrafluoroethylene) [P(VDF–TeFE)] thin film as the ferroelectric gate. The P(VDF–TeFE) film is prepared by spin coating, and it was cooled slowly with a flattening process after annealing. The polarization–electric field (P–E) hysteresis of the P(VDF–TeFE) thin film prepared by slow cooling is larger than that in the case of quick cooling. Moreover, the flattening process does not have a negative effect on ferroelectric properties. The obtained remanent polarization (P_r) of 5.2 µC/cm² is sufficient for controlling the pentacene surface potential. Good memory characteristics are obtained in the P(VDF–TeFE) gate FET with pentacene deposited on the flat P(VDF–TeFE). The maximum drain current is about twice larger than that deposited on the rough P(VDF–TeFE) prepared by quick cooling, and the memory retention is over 1 week.

The coercive field E_c of ferroelectric poly(vinylidene fluoride–trifluoroethylene) [P(VDF–TrFE)] has been studied by observing the displacement current due to polarization reversal. Unlike in a metal–insulator–metal device, the polarization reversal in a metal–insulator–semiconductor diode (pentacene as the semiconductor) is a two-step process. We used modified current–voltage measurements to intentionally avoid the second-step polarization reversal and observed a reduced E_c. The reduction of E_c is interpreted to be a result of the reduced local dipole-induced field, on the basis of the optical electric-field-induced second-harmonic generation measurements.

The channel formation process in a pentacene field effect transistor was studied by directly probing the carrier motion along the channel in the time domain and the capacitance changes in the frequency domain. With the source and drain electrodes short circuited and the voltage applied only to the gate electrode, the carrier injection from both top electrodes and its motion along the channel was still observable, implying an interface charging process driven by a self-induced electric field. In addition, it was found that when the source and drain electrodes were short circuited, the capacitance of the device was larger than the geometric capacitance and proportional to the channel length, which also supported the interface charging model. The relationship between the two approaches was also discussed.

Pentacene organic field-effect transistors (OFETs) with multilayer graphene (MLG) films as the source and drain electrodes were fabricated. Pentacene OFETs with MLG electrodes showed significantly enhanced electrical property compared to devices with typically used Au electrodes because MLG electrode yields lower contact resistance and lower barrier height. Specifically, the pentacene OFETs with graphene electrodes exhibited increased output current by more than tenfold, high mobility as 0.4 cm² V^-1 s^-1, and high on/off current ratio of 10⁷. Our study may be useful for the development of organic transistors that are capable of producing improved performances.

We demonstrated solution-processed C₆₀ thin-film transistors with high electron mobility. C₆₀ solutions in various organic solvents were dried in a vacuum chamber to obtain uniform thin films. While C₆₀ solution dried under atmospheric pressure produced a large number of crystals, vacuum-dried C₆₀ solution provided flat and uniform thin films of sufficiently high quality to fabricate thin-film transistors. In spite of amorphous-like thin-film formation, C₆₀ transistors showed strong solvent dependence. High performance C₆₀ thin-film transistors with field-effect mobility of 0.86 cm² V^-1 s^-1, threshold voltage of 1.5 V, subthreshold slope of 0.67 V/decade and a current on/off ratio of 3.9 ×10⁶ were obtained from 1,2,4-trichlorobenzene C₆₀ solution.

Thermal annealing effects of the aligned thiophene-based polymer films were studied. Aligned poly2,5-bis(3-alkylthiophene-2-yl)thieno[3,2-b]thiophene (pBTTT) and poly2,5-bis(3-alkylthiophene-2-yl)thieno[2,3-b]thiophene (pBTCT) films were fabricated by utilizing capillary actions of polymer solutions. The optical anisotropies of the aligned films were enhanced by thermal annealing at temperatures below the phase transition. The differences in the optical anisotropies between pBTTT and pBTCT were discussed by taking the lamellar stacking structures in the aligned films and phase transition into consideration.

A smooth surface of the poly(3-hexylthiophene) (P3HT)-doped-(6,6)-phenyl-C61-butyric acid methyl ester (PCBM) thin film was achieved by mixing different solvents for the electrospray deposition method. As a result, the high power-conversion efficiency (PCE) of the bulk-heterojunction organic photovoltaic cell (OPV) was comparable to that obtained in the case of the spin-coating method. By optimizing the additional solvent in o-dichlorobenzene, the P3HT/PCBM active layer with the root-means-square roughness of 2.23 nm and the PCE of 2.2% was fabricated employing acetonitrile as the additional solvent.

The contributions and deposition conditions of ultrathin titania nanosheet (TN) crystallites were studied in an inverted bulk-heterojunction (BHJ) cell in indium tin oxide (ITO)/titania nanosheet/poly(3-hexylthiophene) (P3HT):phenyl-C₆₁-butyric acid methylester (PCBM) active layer/MoO_x/Ag multilayered photovoltaic devices. Only one or two layers of poly(diallyldimethylammonium chloride) (PDDA) and TN multilayered film deposited by the layer-by-layer deposition technique effectively decreased the leakage current and increased both open circuit voltage (V_OC) and fill factor (FF), and power conversion efficiency (η) was increased nearly twofold by the insertion of two TN layers. The deposition of additional TN layers caused the reduction in FF, and the abnormal S-shaped curves above V_OC for the devices with three and four TN layers were ascribed to the interfacial potential barrier at the ITO/TN interface and the series resistance across the multilayers of TN and PDDA. The performance of the BHJ cell with TN was markedly improved, and the S-shaped curves were eliminated following the the insertion of anatase-phase titanium dioxide between the ITO and TN layers owing to the decrease in the interfacial potential barrier.

We have investigated the photovoltaic properties of multilayered organic photovoltaic devices consisting of indium tin oxide (ITO)/(NiO)/donor/C₆₀/bathocuproine (BCP)/Al structures. Open circuit voltage (V_OC) increases with the decrease in temperature between 40 and 350 K. The V_OC was, however, pinned at approximately 0.6 V for the device without NiO, probably owing to the insufficient work-function difference between ITO and Al electrodes. The hole injection was also markedly suppressed at the ITO/donor interface in the device with large IP donor materials without the buffer layer and abnormal S-shaped current density–voltage (J–V) characteristics were observed. On the other hand, the value of V_OC increases with the increase in ionization potential (IP) of donor materials in the device with NiO buffer layers owing to the enhanced work-function difference of about 1 eV, and the S-shaped curves disappeared at the high temperatures above 200 K. The V_OC is further improved to nearly 1.2 V by the UV–ozone treatment of the NiO surface. We have therefore concluded that the increment of work function of the anode caused by the insertion of an oxide buffer layer and the surface treatment of the electrode by UV–ozone treatment are essentially important for the improvement of V_OC and charge transport/injection properties in the multilayered organic solar cell applications.

The effects of doping a liquid crystalline phthalocyanine derivative, 1,4,8,11,15,18,22,25-octaalkylphthalocyanine (CnPcH₂, n = 6, 7), into bulk heterojunction organic thin-film solar cells based on poly(3-hexylthiophene) (P3HT) and 1-(3-methoxy-carbonyl)-propyl-1-1-phenyl-(6,6)C61 (PCBM) were studied. The absorbance spectra and external quantum efficiency spectra in the near-infrared region corresponding to the Q-band of CnPcH₂ were improved by doping C6PcH₂ or C7PcH₂. On the basis of the characteristics of CnPcH₂, obtained optical properties, and results of analysis of X-ray diffraction of the composite films of P3HT:CnPcH₂:PCBM, we discussed the photovoltaic properties of solar cells with CnPcH₂ by taking the micro phase separation in the active layers into consideration.

We fabricated a complementary metal–oxide–semiconductor image sensor with a femtoliter microchamber array. The microchamber array plate is used for trapping microbeads and limiting the incident angle of light detected by the sensor. The sensor has an interference filter for fluorescent microbeads imaging. We detected fluorescent and nonfluorescent microbead with this sensor and showed its capability for counting the number of fluorescent chambers.

Fast and accurate diagnosis is critical in infectious disease surveillance and management. We proposed a DNA recovery system that can easily be adapted to DNA chip or DNA biosensor for fast identification and confirmation of target DNA. This method was based on the re-hybridization of DNA target with a recovery DNA to free the DNA probe. Functionalized silicon nanowire field-effect transistor (SiNW FET) was demonstrated to monitor such specific DNA–DNA interaction using high pathogenic strain virus hemagglutinin 1 (H1) DNA of avian influenza (AI) as target. Specific electric changes were observed in real-time for AI virus DNA sensing and device recovery when nanowire surface of SiNW FET was modified with complementary captured DNA probe. The recovery based SiNW FET biosensor can be further developed for fast identification and further confirmation of a variety of influenza virus strains and other infectious diseases.

We proposed a method to characterize the effect of micrometer-scale walls on the motion of microtubules propelled by dynein, a motor protein. The walls were made of resist polymers, such as OEBR1000, SAL601, and PMGI, using e-beam lithography. The pattern of the walls was designed to make microtubules collide with the wall perpendicularly and the number of microtubules crossing over the wall was counted from sequential images obtained with a fluorescence microscope. It was found that the wall, which was higher than approximately 800 nm, stops microtubules from crossing over the wall. The wall made of OEBR1000 prevents microtubules from crossing it more effectively than that made of SAL601 and the overhang is also useful for guiding the microtubule motion.

The spray coating of a photoresist using a shield plate with an aperture is carried out for uniform deposition onto three-dimensional (3D) trench structures. The shield plate set over a sample blocks resist deposition onto the sample, except in the aperture area. Numerical analysis reveals that the vertical velocity component of gas flow is enhanced in the aperture area. In experiments on spray coating, the difference between the thicknesses of resist films deposited on top and bottom trench surfaces is decreased. On the trench sidewall, resist bump formation, which is frequently observed in spray coating, is suppressed. The profile of the resist film becomes conformal and uniform. Such resist deposition is necessary to realize 3D microdevices. In microfluidic devices using dielectrophoresis, aside from the top and bottom trench surfaces, the trench sidewall can be used for preparing device structures such as electrode. Electric interaction is enhanced for controlling the transport of micro-/nano-scale objects in micro-trench structures.

We propose a SiO₂/HfO₂/Al₂O₃ (OHA)-engineered sensing membrane fabricated by stacking high-k materials in order to improve the electrical and chemical stability of ion-sensitive field effect transistors (ISFETs). The sensing properties of the OHA layer were compared with SiO₂/HfO₂ (OH) and SiO₂/Al₂O₃ (OA) layers. As a result, the OHA layer revealed a high on/off current ratio of 1.05 ×10¹⁰, a low subthreshold swing of 62 mV/dec as gate insulator of the metal–oxide–semiconductor field-effect transistors (MOSFETs) and an excellent pH sensitivity of 57.1 mV/pH, a small drift rate of 0.23 mV/h and a low hysteresis voltage of 1.85 mV as the sensing membrane of the ISFET pH sensors. These improvements could be explained by the rigid band structure of the tri-stacked engineered sensing layer. Consequently, the OHA sensing membrane looks promising for bio-sensor application with improved signal-to-noise ratio.

The effect of MgO barrier insertion on a spin-valve signal in a four-terminal non-local geometry and on tunneling anisotropic magnetoresistance (TAMR) characteristics in a three-terminal geometry was investigated in Co₅₀Fe₅₀/n-GaAs heterojunctions. Inserting a MgO barrier significantly enhanced the spin-valve signal amplitude by a factor of 38, and the sign of spin polarization was opposite that of a sample without a MgO barrier. The TAMR effect was suppressed in the case of a Co₅₀Fe₅₀/MgO/n-GaAs junction. This suppression of the TAMR effect can be explained by the suppression of Fermi-level pinning and the lowering of Schottky barrier height.

The time-resolved switching characteristics of 100×200 nm² size CoFeB/MgO/CoFeB-based magnetic tunnel junction (MTJ) are investigated by using the 20 GHz sampling measurement technique. We focused on the physical quantities of the time-resolved characteristics such as incubation time t_A, transit time t_B, and the standard deviations σV's of the period of the switching waveform. Furthermore, the dependencies of t_A and t_B on the applied pulse waveforms are analyzed. We found t_A exponentially decreases as the applied voltage to MTJ increases, while t_B remains less than two nano seconds regardless of the applied voltage. Furthermore, it is observed that the standard deviations of the waveform during t_A is larger than that of the other periods. Finally, we discuss the switching characteristics with proposed toy model based on spin transfer torque (STT) phenomena.

We have theoretically investigated the wave packet dynamics method for the write characteristics of the nanoscale magnetic tunnel junction with synthetic ferrimagnets based on the microscopic quantum electron model. In this study, we have performed numerical simulation of two bands tight binding electron model. In order to take into account the electron–electron correlation, we consider the on-site Coulomb interaction, Hund exchange coupling and finite electric field. In our simulation, we employ the time dependent molecular field approximation. Based on the simulation using wave packets, we have clarified the role of ferrimagnet in the nanoscale magnetic tunnel junction.

Epitaxial MgAl₂O₄ thin films were grown on Heusler alloy Fe₂CrSi by reactive magnetron sputtering of a MgAl₂ target in an O₂+Ar atmosphere. To grow MgAl₂O₄ on Fe₂CrSi, we inserted a protective layer of MgAl₂ between Fe₂CrSi and MgAl₂O₄ to prevent Fe₂CrSi from being oxidized. Growth of MgAl₂O₄ was found to be very sensitive to the MgAl₂ thickness and P_O2 during deposition of MgAl₂O₄. A strong XRD peak of MgAl₂O₄ (004) was observed with an ultrathin (0.2 nm) MgAl₂ layer. The saturation magnetic moment of Fe₂CrSi was measured to be 370 emu/cm³ (1.84 µ_B/f.u.) at room temperature and it is expected to have a high spin polarization. The Fe₂CrSi/MgAl₂O₄ heterostructure is promising for use in future spintronic devices.

We investigated the MgO layer thickness dependences of the structure and magnetic properties of L1₀-FePt/MgO/GaAs structures. To examine how the crystallinity and growth morphology of the MgO layer affect the L1₀-FePt layer, two kinds of preparation method were employed for MgO deposition: electron beam (EB) evaporation and sputter deposition. The MgO layer deposited by EB evaporation included a large strain because of the cube-on-cube epitaxial relationship despite a large lattice mismatch between MgO and GaAs. For the MgO layer prepared by sputtering, on the other hand, an amorphous MgO layer was initially grown on the GaAs substrate. Subsequently, a crystalline MgO layer was grown in the (001) direction. In the case of the EB-deposited MgO, as the MgO layer thickness increased, the degree of chemical order of the L1₀-FePt layer increased from 55 to 81% owing to the improvement of the crystallinity of the MgO layer. The improvement of chemical order also led to the increase in the remanent magnetization of L1₀-FePt from 84 to 98%.

Towards a low search-energy nonvolatile ternary content-addressable memory (TCAM), we propose a novel nine-transistor/two-magnetic-tunnel-junction (9T–2MTJ) nonvolatile TCAM cell circuit with a high-speed accessibility. Since critical path for switching in the TCAM cell circuit is only a single metal-oxide-semiconductor (MOS) transistor, switching delay of the TCAM word circuit is minimized. As a result, the worst-case switching delay of 0.22 ns is achieved in a 144-bit word circuit under a 90 nm complementary MOS (CMOS)/MTJ technology, which is about 2.6 times faster than that of a conventional CMOS-based TCAM. In order to minimize the active power dissipation in the proposed TCAM, a multi-level segmented match-line scheme that maximally brings inessential cells to standby state is also applied to the 9T–2MTJ-cell-based word circuit. Finally, low search-energy of 0.73 fJ/bit/search is achieved in a 144-bit × 256-word nonvolatile TCAM together with eliminating standby power using nonvolatility.

We have estimated the height of barriers against carriers formed in the metallic carbon nanotube (m-CNT) grown by plasma-enhanced chemical vapor deposition. The result shows that the heights of the barriers against both electrons and holes are about 300 meV. The existence of the barrier in the m-CNT was confirmed by local current modulation using scanning gate microscopy and by the potential drop obtained by Kelvin probe force microscopy.

Quasi-free-standing bilayer graphene was grown by hydrogen intercalation of epitaxial monolayer graphene on SiC(0001). A larger size of stacking domains compared to that of epitaxial bilayer graphene grown on SiC(0001) was observed in a low-energy electron microscopy analysis of its morphology. By evaluating its electronic transport characteristics in top-gated devices, we found that the quasi-free-standing bilayer graphene is p-doped at zero-gate voltage. Further, an increase in mobility was found compared to that of epitaxial bilayer graphene. As a result of the higher mobility, Shubnikov–de Hass oscillations were observed. We attribute the improved quality of the quasi-free-standing bilayer graphene to its structural properties.

We fabricated nanowire light-emitting diodes (LEDs) using InP nanowires (NWs). Indium phosphide NWs with axial p–n junction were grown by selective-area metalorganic vapor phase epitaxy. The results of secondary-electron-microscopy (SEM) observation and photoluminescence measurement showed the formation of wurtzite InP NWs with some mixture of zincblende crystal phase, as expected from the used growth conditions. NW-LEDs were fabricated by sputtering indium tin oxide (ITO) after a planarization process for the top contact and AuZn evaporation for the backside contact. Current–voltage characterisitics showed clear rectifying characteristics with a small leakage current, and fairly linear current–light output characteristics were observed. By designing the pitch of the NW array, emission from individual NWs was confirmed, which opens the possibility for realizing a single NW-LED applicable to single-photon emitters.

First-principles total energy calculations are performed to investigate the electronic and magnetic properties of rhombohedral graphite thin films on hexagonal boron nitride (h-BN) substrate. We find that the ferrimagnetic spin ordering of graphite thin films on h-BN substrate is robust irrespective of the adsorption arrangement. However, by enhancing the interaction between the graphite thin film and the substrate, the interaction suppresses the electron spin polarization of the bottommost graphene layer situated at the interface with the substrate. The electron spin polarization emerges at the second subsurface graphene layer in the thin film. We also find that the magnetic property of the graphite thin film on the insulating substrate is tunable by applying an external pressure.

We study the geometries, energetics, and electronic structures of free-standing graphene with long range structural undulations. Our calculations, which are based on density functional theory, show that the energy cost to induce the structural corrugation is about a few tens of meV per C atom which is similar to the total energy of the C atoms in carbon nanotubes. Our tight-binding molecular dynamics simulations confirmed that graphene exhibits long-range structural undulation at temperatures above 400 K. Moreover, our detailed analysis of the electronic energy band near the Fermi level shows that the linear dispersion band is sensitive to these structural undulations, which leads to semiconducting properties with an energy gap of a few meV.

The change in the conduction type of carbon nanotube field-effect transistors (CNT-FETs) with Au contacts from p-type to n-type by annealing in vacuum was observed. The result was explained by the local work function change of the Au contacts based on the measurement of the surface potential of the Au/CNT contact by Kelvin probe force microscopy (KFM). This work function change became prominent due to the desorption of oxygen by annealing. The degree of the conduction-type change was found to be dependent on the devices. The CNT-FETs with small OFF current showed clear conduction-type change. However, the devices with large OFF current did not show clear conduction-type change. This device dependent behavior was explained by the energy gap difference among devices, in which suppression of OFF current is not sufficient for the devices with thick CNTs with small bandgap.

In-plane asymmetric strain relaxation in lattice-mismatched InGaAs/GaAs(001) heteroepitaxy is studied by in situ three-dimensional X-ray reciprocal space mapping. Repeating crystal growth and growth interruptions during measurements allows us to investigate whether the strain relaxation is limited at a certain thickness or saturated. We find that the degree of relaxation during growth interruption depends on both the film thickness and the in-plane directions. Significant lattice relaxation is observed in rapid relaxation regimes during interruption. This is a clear indication that relaxation is kinetically limited. In addition, relaxation along the [110] direction can saturate more readily than that along the [10] direction. We discuss this result in terms of the interaction between orthogonally aligned dislocations.

Isochronal and isothermal annealing treatments were carried out on GaAsN films grown by chemical beam epitaxy to clarify the evolution of a nonradiative recombination center, at an average energy level of 0.33 eV below the conduction band minimum of the alloy. This lattice defect showed a strong persistence during post-thermal annealing even under critical annealing conditions. By considering as-grown samples as references and after optimizing the temperature and time of annealing, the trapping density of this recombination center could be reduced to one-half. Since the origin of this N-related recombination center was tentatively considered as the split interstitial (N–As)_As, we suggest that the evolution of its density could be explained in great part to the diffusion behavior of As atoms during thermal stress.

Under concentration conditions, it is important to optimize the design of electrodes and cell structures, because high-density energy is emitted to the cell and photocurrent with high density is generated by each subcell of a multijunction solar cell. The in-plane distributions of power consumption by the each resistance component were calculated using a total three-dimensional (3D) simulator. In the case of optical design without a homogenizer, high power consumption at the electrode and top layer was observed in part of the cell. In the middle and bottom layers, power consumption was also observed, though it was slight in comparison with the upper layers. On the other hand, in the case of the optical design with a homogenizer, the power consumption was considerably reduced. This technique can be applied to the structural optimization of solar cells for concentration.

We developed an In₂O₃:H/indium–tin oxide (ITO) stack as the front transparent conductive oxide (TCO) layer of nanocrystalline cubic silicon carbide/crystalline silicon heterojunction solar cells with Al₂O₃ passivation layers. We investigated the solar cell performance and optical and electrical properties of this layer with various annealing temperatures. The solar cells with In₂O₃:H and In₂O₃:H/ITO layers show a higher short circuit current density (J_sc) than that with an ITO layer owing to their lower surface reflection and lower free carrier absorption. The solar cell with the In₂O₃:H/ITO stack shows a higher fill factor (FF) than that with the In₂O₃:H layer. The solar cell with the In₂O₃:H/ITO stack shows an aperture area efficiency of 16.8% (V_oc = 0.638 V, J_sc = 34.5 mA/cm², and FF= 0.762). These results indicate that the In₂O₃:H/ITO stack has good optical and electrical properties after annealing.

Nanocrystalline porous silicon (nc-PSi), a material already widely studied for application in photonics, optoelectronics and sensing devices, is currently under investigation as an active element in photodetection and photovoltaic application as well. Thanks to its unusual properties such as a band gap widening compare to bulk Silicon and its relatively simple and cheap fabrication method, the material could potentially be used as an active top-cell material in multi-junction cells structures. In order to confirm the availability of nc-PSi material as a wide gap absorber for solar cells, free standing layers of the material were fabricated and the results of their optical and photovoltaic characterization are presented in this paper.

This paper presents a compact model of the diode reverse recovery effect for the simulation program with integrated circuit emphasis (SPICE) simulation. We found that the reverse recovery effect can be described with the dynamic carrier distribution within the lightly-doped N^- drift layer of a p–i–n power diode. The proposed model is verified with two-dimensional (2D) device simulation results and compared with a lumped-charge-based conventional model.

Light illumination on a photoelectrode creates separate electron and hole pairs that lead to an oxidation and reduction reaction. Here, we show that CO₂ reduction by means of water and light is realized by a gallium nitride (GaN) photoelectrode in which excited electrons drive CO₂ conversion at the counterelectrode. A copper (Cu) plate was chosen as the counterelectrode. With this system, the generation of formic acid (HCOOH) with 9% Faradic efficiency was confirmed by light illumination alone with the help of NiO co-catalysts.

In multi-crystalline silicon grown by unidirectional solidification, there are many origins of crystalline defects. In this study, we investigated the effect of light-element impurities on the generation of crystalline imperfections during crystal growth. In order to control the interfusion of impurities, we regulate the Ar gas flow in the atmosphere on the basis of a computer simulation. The etch pit densities in the sample fabricated without and with Ar gas flow control in the atmosphere were 1.5×10⁵–7.0×10⁷ and 5.0×10³–4.0×10⁵ cm^-2, respectively. In the sample fabricated without Ar gas flow control, the precipitates consisting of light-elements were observed in the region where the etch pit density markedly increased. In the region with the highest etch pit density, there were small-angle grain boundaries consisting of dislocations. We believed that the precipitates consisting of light-element impurities were the potential origins of small-angle grain boundaries. The light-element impurities should affect the crystalline defect generation induced during crystal growth, and thereby should be controlled.

30-nm-diameter silica nanoparticles with a carboxyl radical (COO^-) were successfully dispersed on an amino-treated silicon wafer at about 20 nm intervals owing to the repulsion among nanoparticles with negative charges. The dispersed silica nanoparticles were used as the mask for the preparation of silicon nanowire (SiNW) arrays by metal-assisted chemical etching (MAE). The diameter of the prepared SiNWs was approximately 30 nm from their transmission electron microscope image.

We fabricated single-phase pyrite thin films of FeS₂ by laser annealing of multi-phase FeS₂ films. Sputter-deposited FeS films followed by sulfurization in sulfur vapor at high temperatures were mainly composed of the high-temperature phase (pyrite) but contained a small amount of the low-temperature phase (marcasite) that likely grew when the samples were naturally cooled after the sulfurization. We applied the rapid cooling feature of laser annealing to preventing the marcasite phase formation. No trace of marcasite phase was observed in Raman spectra and X-ray diffraction patterns of the laser-annealed samples. We analyzed temporal evolution of the sample temperature during the laser-annealing processes to confirm that the laser heating induced phase change of the small amount of marcasite to pyrite and the rapid cooling prevented marcasite regrowth.

Various sizes of TiO₂ hollow nanosphers were synthesized by a hydrolysis followed by the hydrothermal treatment using different water content and titanium isopropoxide (TTIP) while the remaining components such as methylamine, ethanol and acetonitrile were kept as a constant. We synthesized the various sizes of spheres, 150, 250, 400, 450, and 600 nm in diameter; those are represented as SP150, SP250, SP400, SP450, and SP600. The prepared spheres diameters were confirmed by scanning electron microscopy (SEM). These spheres were coated by using a simple spray technique with the TiO₂ colloidal solution as a scattering layer for the TiO₂ photoelectrode of dye-sensitized solar cells. Optical absorption measurements did not find a difference in the dye adsorption amount with and without the scattering layer. The scattering effect was observed by incident photon to current conversion efficiency (IPCE) measurements especially in the wavelength region of 550–700 nm. The current–voltage (I–V) measurements show that the scattering layer with 450 nm spheres coated on the photoelectrode gave the improved photovoltaic performances compared to other diameters of the spheres. In the present study, the best energy conversion efficiency of 9.56% was obtained for the photoelectrode with the scattering layer, while the pure photoelectrode without the layer gave 8.4%.

For the fabrication of very high voltage SiC devices, it is essential to know the surface recombination velocity to accurately control the carrier lifetime. This study shows experimental results on the carrier lifetime in free-standing n-type 4H-SiC epilayers with several thicknesses and under two surface conditions to estimate the surface recombination velocity. The surface with chemical–mechanical polishing (CMP) was found to have lower surface recombination velocities than the as-grown epilayer surface. Similarly, the surface recombination velocity after CMP was low on the Si-face compared with that on the C-face. In addition, the surface recombination velocities on Si- and C-faces after CMP were quantitatively evaluated by comparison of experimental results with numerical calculations.

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