Table of contents

This paper clarifies for the first time that employing Cu–Mn alloy can reduce the resistance of ultralarge scale integration (ULSI) interconnects. It is well known that Cu alloys have higher resistance than pure Cu. However, recent discussion indicates that Cu or barrier metal oxidation by moisture from interlayer dielectrics causes electrical resistance to increase even further. Therefore, Cu oxidation must be prevented. Previously, we have reported a barrier restoration technique using Cu–Mn alloy, and the application of this technique is expected to result in strong tolerance to Cu oxidation. In this work, we investigated the property that copper is protected from oxidation when using the barrier restoration technique with Cu–Mn alloy. This property results in the reduction of interconnect resistance and the improvement of the resistance distribution in ULSI interconnects. We conclude that using the barrier restoration technique with Cu–Mn alloy will be being compatible with further scaling to 22 nm node and beyond.

In this paper, we propose a new method of cap-layer formation. The cap layer of SnO₂ is formed by the displacement plating of Sn, followed by the oxidation of the plated Sn. An excellent plating selectivity was found between Cu and SiO₂, but not with SiOCH. The SnO₂ layer of 90 nm thickness showed a good oxidation resistance of the underlying Cu after heat treatment at 480 °C in air (P_O2=10⁵ Pa). In contrast, the SnO₂ layers of 6 and 9 nm thickness showed oxidation resistance at 400 °C in Ar+10 ppm O₂ (P_O2=1 Pa), but not in Ar+1000 ppm O₂ (P_O2=100 Pa).

We fabricate reliable interconnects via advanced barrierless metallization by cosputtering a pure copper (Cu) film with small amounts of holmium nitride (HoN_x) on a silicon (Si) substrate. No noticeable interaction occurs between the resulting Cu(HoN_x) film and the substrate even after heating at 660 °C for 1 h. The resistivity of the alloy film, which remains stable after five cycles of heating at 600 °C (total: 2.5 h), is high under the as-deposited condition, but decreases to ∼3.0 µΩ cm after annealing. The leakage current of the alloy film is three times lower than that of the pure Cu film. The correlation between the leakage current and the time-dependent dielectric breakdown (TDDB) lifetime reveals that the alloy film has a TDDB lifetime of >10 years. Furthermore, the alloy film adheres better to the Si substrate than does the pure Cu film. Our alloy film thus has improved features that are desirable for a reliable interconnect.

The copper diffusion barrier properties of a 3 nm self-forming InO_x layer on a porous ultralow-k (p-ULK) film have been investigated. A 5 at. % In doped Cu film was directly deposited onto porous low-k films by co-sputtering, followed by annealing at various temperatures. Transmission electron microscopy (TEM) images showed that a 3 nm layer was self-formed at the interface between Cu–In and p-ULK films after annealing at 400 °C for 1 h. An EDS line scan on the region near this interface showed obvious accumulation of In at the interface. X-ray photoelectron spectroscopy (XPS) analyses indicated that the self-formed interfacial layer was InO_x. The self-forming InO_x layer prevented Cu agglomeration on the p-ULK film surface. The XPS atomic depth profiles showed that the self-formed InO_x barrier was thermally stable against Cu diffusion to at least 500 °C for 5 h. The sheet resistance of the post 500 °C annealed Cu–In film was comparable to that of a pure Cu film. The Cu–In self-forming barrier approach may be a viable candidate for Cu/p-ULK interconnects.

We have investigated the evolution of microstructures in a nanocrystalline VN barrier of ∼10 nm thickness to clarify the failure mechanism in a Cu/VN/SiO₂/Si system owing to high-temperature annealing. Transmission electron microscopy observation reveals that the as-deposited VN barrier shows a uniform layer with a columnar structure composed of grains no larger than 10 nm in size. A negligible change in the morphology of the VN barrier is evident even after annealing at 600 °C for 1 h. Annealing at 800 °C brings about noticeable growth of VN grains in the lateral direction without any solid-phase reaction at each interface, resulting in a failure of the VN barrier owing to local discontinuity of the layer. This result is also consistent with the result obtained by Auger electron spectroscopy. It is revealed that the thin VN barrier fails after annealing at 800 °C for 1 h owing to the loss of the continuity in the lateral direction without chemical reaction and intermixing at barrier interfaces.

The results of analyses by X-ray diffraction, transmission electron microscopy, and grazing incidence X-ray reflectivity measurement indicate that a 5-nm-thick ZrN film interposed between Cu and SiO₂ shows excellent barrier properties, tolerating annealing up to at least 500 °C for 30 min. The X-ray diffraction pattern reveals a decrease in the intensity of the Cu(111) reflection upon annealing at 800 °C, suggesting a failure of the thin barrier due to Cu diffusion through the barrier. We are confident that the formation of a continuous nanocrystalline ZrN film in a uniform fashion in a stable phase with a slightly nitrogen-rich composition is a cause of the excellent features obtained. The formation process of the ZrN film is discussed in terms of the nucleation process of reactive sputtering at a low deposition temperature.

The morphological stability of Cu films in narrow trenches during the initial growth of Cu was studied at temperatures of 140–280 °C for the chemical deposition of Cu in supercritical CO₂. Cu seed layers agglomerated and the deposited Cu and the seed layer coalesced at elevated temperatures. This mechanism resulted in bottom-up like growth at lower temperatures of 160–180 °C. The seed agglomeration was suppressed by starting deposition before reaching the temperature at which agglomeration started of about 150 °C. When Ru-lined trenches were used instead of Cu-seeded trenches, no clear agglomeration or grain coarsening was observed and Cu grew with a conformal topography.

The resistivity increase caused by grain boundary (GB) scattering is a challenging problem in the formation of narrow copper (Cu) interconnects less than 100 nm wide. In order to reduce GB scattering, a new annealing method was successfully developed to enhance the grain growth of electroplated Cu films using supercritical (SC) CO₂ with H₂. In order to determine the effect of H₂, the Cu surface was analyzed using X-ray photoelectron spectroscopy (XPS). The amounts of oxygen (O) and carbon (C) at the Cu surface after SC annealing were reduced with increasing H₂ pressure. Surface migration was considered to be enhanced by the reduced amount of O and C, which led to grain growth enhancement. The cross-sectional grain structure in 100-nm-wide interconnect trenches was observed using secondary ion microscopy (SIM). The Cu grains inside the trench were found to be affected by the microstructure in the Cu overburden. Accordingly, Cu grain growth in trenches is also expected to be enhanced by SC annealing.

The formation of palladium silicide on Pd/Ti/Si systems with and without heavy B-doping has been investigated. For comparison, Pd₂Si was also formed on Pd/Si systems. The agglomeration of Pd₂Si could be retarded in Pd/Ti/Si systems with and without B-doping after annealing at 600 °C. The existence of the Ti layer could improve the thermal stability of Pd₂Si. In addition, epitaxial or highly oriented Pd₂Si formed in Pd/Ti/Si systems. The two orientation relationships of Pd₂Si layers were identified to be Pd₂Si[110]∥Si[110] and Pd₂Si[110]∥Si[001], and Pd₂Si[100]∥Si[110] and Pd₂Si[001]∥Si[001]. The formation of strained epitaxial Pd₂Si layers was found in Pd/Ti/Si systems. The improvement in the thermal stability of Pd₂Si and the formation of epitaxial or highly oriented Pd₂Si in Pd/Ti/Si systems were observed with and without B-doping.

Cobalt plasma-enhanced atomic layer deposition (PE-ALD) using cyclopentadienyl isopropyl acetamidinato-cobalt [Co(CpAMD)] precursor and NH₃ plasma was investigated. The PE-ALD Co thin films were produced well on both SiO₂ and Si(001) substrates. The deposition characteristics and films properties such as resistivity, chemical bonding states and quantitative impurity level contents were investigated. Especially, Co deposition using this precursor was possible at very low growth temperature as low as 100 °C, which enable the deposition on polymer-based substrate. We demonstrate that this low growth temperature PE-ALD can be applicable to patterning of Co film by lift-off method, which was realized by direct deposition of Co on photoresist patterned substrate.

Ni plasma enhanced atomic layer deposition (PE-ALD) using bis(dimethylamino-2-methyl-2-butoxo)nickel [Ni(dmamb)₂] as a precursor and NH₃ or H₂ plasma as a reactant was comparatively investigated. PE-ALD Ni using NH₃ plasma showed higher growth rate, lower resistivity, and lower C content than that using H₂ plasma. PE-ALD Ni films were analyzed by X-ray photoelectron spectroscopy (XPS), scanning transmission electron microscopy (STEM), and electron energy loss spectroscopy (EELS). The results showed that the reaction chemistry of ALD using NH₃ plasma was clearly different with that using H₂, probably due to the effects of NH_x radicals.

A manganese oxide (MnO_x) diffusion barrier layer was formed by chemical vapor deposition (CVD) on SiO₂ substrates with or without preannealing. The thickness dependence of the MnO_x layer was investigated in relation to the desorption behavior of water vapor from the substrates. A good correlation was found between MnO_x thickness and the amount of desorbed water vapor. It is necessary to control the amount of absorbed water in the substrate to form a thin MnO_x barrier layer with good thickness reproducibility.

Various silicon nitride (SiN) films were prepared using plasma enhanced chemical vapor deposition (PECVD) by tuning deposition condition to control initial hydrogen in the films. The as-deposited films, which exhibit different tensile stress from 0.2 to 1.2 GPa, were treated by ultraviolet (UV) curing to investigate how the stress and shrinkage response to film initial hydrogen state and how to modify SiN hydrogen state by deposition condition to achieve high tensile stress. The results show that the stress and shrinkage of SiN films response quite differentially to UV curing depending on hydrogen state. Stress of SiN was hardly tuned by UV curing in case of Si–H deficiency, but largely increased in case of balanced Si–H and N–H bonds. Both high and low stress-tunable SiN films were used as contact etch stop layer (CAESL) in 45 nm bulk device. Device performance (I_on–I_off) has been improved by about 5% using high stress-tunable SiN film.

We report herein the demonstration of a simple, low-cost Cu back-end-of-the-line (BEOL) dual-damascene integration using a novel photo-patternable low-κ dielectric material concept that dramatically reduces Cu BEOL integration complexity. This κ=2.7 photo-patternable low-κ material is based on the SiCOH-based material platform and has sub-200 nm resolution capability with 248 nm optical lithography. Cu/photo-patternable low-κ dual-damascene integration at 45 nm node BEOL fatwire levels has been demonstrated with very high electrical yields using the current manufacturing infrastructure. The photo-patternable low-κ concept is, therefore, a promising technology for highly efficient semiconductor Cu BEOL manufacturing.

This study explores the transition of shear force spectral fingerprints during tantalum (Ta) and/or tantalum nitride (TaN) chemical mechanical planarization on patterned wafers using a polisher and tribometer that has the unique ability to measure shear force and down force in real-time. Fast Fourier Transformation is performed to convert the raw force data from time domain to frequency domain and to illustrate the amplitude distribution of shear force and down force. Results show that coefficient of friction, variance of shear force and variance of down force increase during polishing when the Ta/TaN layer is removed thus exposing the inter-layer dielectric layer. Unique and consistent spectral fingerprints are generated from shear force data showing significant changes in several fundamental peaks before, during and after Ta/TaN clearing. Results show that a combination of unique spectral fingerprinting, coefficient of friction and analysis of force variance can be used to monitor in real-time the polishing progress during Ta/TaN chemical mechanical planarization for optimal polishing time.

To reduce the effective dielectric constant (k_eff) value for 32 nm node technology and beyond, the effects of a direct chemical mechanical polishing (CMP) process on porous low-k film without a protective cap layer were investigated. It was confirmed that a capless structure on porous low-k film is effective in reducing the resistance–capacitance (RC) products, but it causes degradation of wire-to-wire breakdown voltage characteristics. The most important point of a direct CMP process is to control the amount of damage to the polished surface. In this study, two types of low-k film were compared in combination with a variety of CMP process conditions. As results, we found that a direct CMP process has a positive effect on wire-to-wire current leakage and time-dependent dielectric breakdown (TDDB) reliability where a porous low-k film deposited by modified conditions is used. By optimizing the deposition and curing conditions, it is possible to control the distribution of different pore sizes in porous low-k film, which allows us to realize a highly reliable capless structure.

A chemical–mechanical polishing (CMP) slurry was developed for use in copper (Cu) damascene interconnects with cobalt (Co) barrier metal by optimizing the corrosion potentials and removal rate selectivities of Cu and Co. A passivation layer was formed on Co surface in an alkaline solution, while no passivation layer was formed in an acidic one even with benzotriazole. In the slurry of pH 10, corrosion potential of Co was the same as that of Cu, which indicates that no galvanic corrosion between Co and Cu could occur. Furthermore, a stable Cu/Co removal rate selectivity of 0.5 was obtained with the slurry.

With continuous shrinkage of advanced ultralarge scale integrations (ULSI), the impact of line resistance on the devices has become more and more important. In order to achieve low resistance and high reliability of Cu interconnects, we have applied a thin Ti-based self-formed barrier layer using Cu–Ti alloy seed to 45 nm node dual-damascene interconnects and evaluated its performance. The microstructure analysis by transmission electron microscope and energy dispersive X-ray fluorescence spectrometer has revealed that 2-nm-thick Ti-based barrier layer is self-formed at the interface between Cu and low-k dielectrics. The line resistance and via resistance decrease significantly, compared with those of conventional Ta/TaN barrier system. The stress migration performance is also drastically improved using self-formed barrier process. These results suggest Ti-based self-formed barrier process is one of the most promising candidates for advanced Cu interconnects.

The sidewall film in low-k/copper interconnects is generally applied to protect the etched low-k surface. However, the existence of this film will become a critical issue with shrinking device sizes. In this work, using intermetal low-k film consisting of scalable porous silica (k = 2.1), we tried to eliminate the sidewall film by reducing pore size in 140-nm-pitched scalable porous silica/copper interconnects. Sufficient wiring resistance yield and low wiring capacitance were obtained even in the structure without sidewall. The degradation in the line-to-line leakage caused by the upper layer fabrication process was improved by this sidewall elimination. The mechanism of the leakage degradation was explained by the moisture diffusion from the upper layer, which reacted with the damage site generated by the sidewall formation process.

This paper discusses integration aspects of a porous low-k film (k ∼2.45) cured with a broadband UV lamp. Different process splits are discussed which could contribute to avoid integration induced damage and improve reliability. The main factor contributing to a successful integration is the presence of a thick (protecting) cap layer partially remaining after chemical mechanical polishing (CMP), which leads to yielding structures with a k_eff of ∼2.6, a breakdown voltage of ∼6.9 MV/cm and time dependent dielectric breakdown (TDDB) lifetimes in the excess of 100 years. Long thermal anneals restore the k-value but degrade lifetime.

Copper (Cu)/low-k interconnects were fabricated using novel Cu diffusion-barrier SiC films deposited with a novel precursor, 1,1-divinyl-silacyclopentane (DVScP). At 46% overetching time, the yield of the via-contact with the dielectric barrier of conventional SiC films was seriously reduced, while that of the novel SiC films was hardly reduced. By using the novel SiC films, the thickness of diffusion barriers was successfully reduced to 15 nm, matching the 32 nm node and beyond. By using the novel SiC films, the dielectric constant of the barrier films was decreased and their thickness was reduced with no yield reduction of the via-contact. As a result, the product of wiring resistance and capacitance (RC product) was reduced by 11.4%. The time-dependent dielectric breakdown (TDDB) lifetime of Cu interconnects with the SiC films was similar to that with the SiCO films.

We propose a method for the statistical analysis of a via-to-line time-dependent dielectric breakdown (TDDB) test under misalignment impacts. The √E and overlay error models are incorporated into the lifetime distribution analysis in the framework of the Weibull regression model. The doubly truncated normal distribution effectively describes the space-decrease distribution that is estimated using the overlay error model. Incorporating these physical and statistical characteristics into the lifetime distribution analysis yields more reliable distribution parameters and helps to distinguish outliers as early failures with rejection of misalignment impacts.

The current conduction in silicon carbon nitride (SiCN) dielectric films subjected to ultraviolet (UV) illumination at room temperature has been investigated. After exposure of SiCN single-layer and SiCN–SiO₂ double-layer films to 4.9-eV UV illumination, leakage currents through both films substantially increased under positive and negative gate biases. The current increased as a function of the change in paramagnetic defect density, which was obtained from electron spin resonance signals of the SiCN and SiCN–SiO₂ films subjected to 4.9-eV UV illumination. We suggest that the paramagnetic defects, which have been identified as neutrally charged silicon dangling bonds, act as generation centers and that their formation is responsible for the current increase. The conduction mechanisms of the photoinduced leakage current are discussed in detail.

Feasibility of step coverage (SC) by supercritical fluid deposition (SCFD) of Cu was evaluated using a finite element method (FEM) simulation with experimentally estimated kinetics and transport properties of the precursor. This SC by Cu-SCFD was compared with that by chemical vapor deposition (CVD). SCFD showed superior SC, especially for ultra narrow features less than 1 µm wide, although CVD has a higher diffusion coefficient. This superior SC was due to the non-linear reaction kinetics of SCFD (CVD has linear reaction kinetics), where precursor concentration had negligible effect on growth rate when the precursor concentration was higher than about 1 mol/L.

SiCH films are a potentially very useful low-k cap layer for covering Cu trenches in ultralarge-scale integration (ULSI) devices. To induce Si–C₂H₄–Si networks in SiCH film structures, 1,1-divinyl silacyclopentane (DVScP) and 5-silaspiro-[4,4]-nonane (SSN) were designed and prepared. Isobutyl trimethyl silane (iBTMS) and diisobutyl dimethyl silane (DiBDMS) were also designed to form Si–CH₂–Si networks in the SiCH molecular structure. SiCH films were formed by plasma-enhanced chemical vapor deposition (PECVD), for use as a low-k cap layer and a Cu diffusion barrier on top of the Cu trenches. We demonstrated additional Si–C₂H₄–Si networks that can effectively suppress Cu diffusion in SiCH low-k barrier films with a reduced k-value of 3.1.

We propose new precursors for bulk low-k films with plasma damage resistance. Our newly designed precursors contain long-chain hydrocarbon groups such as i-butyl and n-propyl groups. Using these precursors, we successfully produced films containing Si–CH₂–Si groups by plasma-enhanced chemical vapor deposition (PECVD). The plasma damage resistance of these films under NH₃ plasma treatment was studied. It was found that the increase in the k-value (Δk) is smaller in films with more Si–CH₂–Si groups.

When post-etch cleaning was carried out in Cu dual-damascene process, Cu at the bottom of isolated via was etched out especially in the wafer edge, and this would become a critical issue as device scale is shrunk. The corrosion was caused in the rinse step rather than chemical cleaning step because dissolved oxygen in rinse water from the air increased oxidation–reduction potential (ORP) and CO₂ included in the rinse water for preventing wafer electrification decreased pH. The corrosion was found to be suppressed by increasing dummy pattern density and by controlling atmosphere and pH of the rinse water.

Photoassisted corrosion of copper (Cu) was evaluated using a photodiode and a quartz crystal microbalance (QCM). A chip-type silicon (Si) photodiode with a large junction area was used in place of actual Si devices. When the illuminated photodiode was connected to the anode and cathode electrodes in an electrolyte, it worked as a voltage source between the two electrodes, and the corrosion rate was governed by the current between the electrodes. The corrosion rate is nearly proportional to the illuminance at less than 100 lx, and corrosion initiates at an illuminance as low as 1 lx. In the geometrical aspect of the photoassisted corrosion system, the corrosion rate is proportional to the square root of the area ratio of a P-connected Cu line to an N line, and is proportional to the illuminated area of the junction in a photodiode. The wavelength of the illuminating light markedly affects the photoassisted corrosion.

In this paper, we describe chemical vapor deposition (CVD) of GeSbTe (GST) films for fabricating phase change memory. A low-carbon-impurity GST film was deposited by CVD. Film composition and structure varied significantly depending on deposition temperature and pressure. The tendency of composition variation on a TiN substrate was the same as that on a SiO₂ substrate. Finally, flat Ge₂Sb₂Te₅ thin films were obtained below 300 °C using tert-butylgermanium, triisopropylantimony and diisopropyltellurium as precursors.

A hybrid electrochemical mechanical planarization and chemical mechanical planarization (e-CMP/CMP) was applied to the Cu dual-damascene through-silicon via (TSV) process for wafer-level three-dimensional integrated circuit (3D-IC) stacking. In this process, an electrochemically deposited Cu film was removed by e-CMP at a removal rate of 3.5 µm/min until the voltage endpoint was detected. Then, residual Cu film was polished off in the CMP mode using the same e-CMP pad. A fine Cu damascene structure was successfully fabricated with a dishing depth of less than 200 nm in a metal pad of 200×200 µm² area. The criterion of dishing without failure in the adhesive coat for 3D-IC stacking is discussed.

To determine a micro electro mechanical systems (MEMS) inductor configuration that gives large inductance variations and high Q-factors, air-suspended MEMS inductor configurations are studied: (a) an inductor with two angularly meandered lines, (b) a solenoid inductor with a pair of movable shields, (c) a planar spiral inductor with a patterned shield of different areas, and (d) a planar spiral inductor with a metallic frame of different sizes. The configuration of (a) is shown to give a large inductance variation of 115%. However, its Q-factor is only about 10, and difficulties in fabrication are also expected. The configuration of (b) could be a reasonable engineering solution. The inductance variation is 67%, and the maximum Q-factor is over 22. The solenoidal inductor configuration is thus considered suitable for realizing an RF MEMS variable inductor with large inductance variations and high Q-factors.

Delamination failure of a low-k interlayer dielectric (ILD) layer of Cu/low-k multilayer interconnects during a thermal cycle test was investigated by mechanical stress simulation. A three-dimensional (3D) multilevel modeling method was used to analyze the stress that occurred in a fine-scale film stack in a large-scale package. The maximum stress occurred at the low-k/cap film interface that was located at the bottom surface of the low-k ILD layer. This maximum-stress interface coincides with the interface where the delamination occurred. Using this method, the effects of the number of ILD layers, the Young's modulus of the ILD, and the package type on the failure were investigated. This method is useful for reducing delamination failure.

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