Effects of consecutive irradiation and bias temperature stress in p-channel power vertical double-diffused metal oxide semiconductor transistors

Development of semiconductor devices has affected technologies in various fields.¹⁾ Because of that there is a great interest for intensive research and improving the device performances.²⁾ In many electronic devices, from metal–oxide–semiconductor field effect transistors (MOSFET) to bipolar integrated circuits (ICs), the parts based on dielectrics are key components. Silicon dioxide (oxide) SiO₂ and oxide–semiconductor interface SiO₂–Si are the most vulnerable parts of the MOS devices subjected to extreme, harsh environmental conditions or to the stress. Namely, irradiation, high electric field (HEF) stressing or bias temperature (BT) stressing lead to creation of oxide and interface defects which can cause degradation of electrical parameters of MOS devices. Hence, these defects have been in the focus of investigation more than 40 years.^3–14)

Numerous methods used in the study of SiO₂ and SiO₂–Si interface nature and their characterization can be roughly divided into two categories: the methods implemented on the MOS capacitor structure and the methods implemented on the complex MOS electron devices. These methods are mostly based on electrical techniques and they generally yield the results related to the energy distribution of defects in the oxide and at the interface, thus allowing the prediction of the defect nature and modelling of their behavior. However, the method based on the electron-spin resonance (ESR),¹⁵⁾ gives an image of the structure of these defects allowing their modelling.¹⁶⁾ The silicon dangling bond defects detected on the SiO₂–Si(111) interface, which are known as P_b centers, are the Si₃≡Si^• amphoteric defects with two energy levels in the silicon bandgap (0.3 and 0.85 eV above the valence band) serving as a correlation energy with broken bonds at SiO₂–Si interface.¹⁷⁾ Other investigations of the SiO₂–Si(100) interface, which have been done by the method based on electron-paramagnetic resonance (EPR),¹⁸⁾ revealed two paramagnetic centres P_b0 and P_b1. The P_b0 centre was found identical to the P_b centre at (111) Si surface, while the nature of the P_b1 centre remained unclear. In the opinion of these authors, the P_b1 centre is a defect of the SiO₂≡Si^• type, while the others think that P_b1 centre is also the Si₃≡Si^• defect without the oxygen as a structural part, but with another broken bond orientation related to the (100) Si surface.^18,19) Beside the interface defects, the silicon dangling bond defects detected in SiO₂ are characterized as E' centres of different varieties and designated as the ≡Si^• defects. It should be noted that the results regarding the SiO₂ and SiO₂–Si interface published so far are of importance since they contribute to the process of determining the nature of the oxide and the interface defects. These defects were mostly responsible for the effects of irradiation, accelerated testing, high electric field stress (HEFS), and bias temperature (BT) stress,^20–36) observed in power MOS transistors, as well. There is particular interest in research of reliability and effects induced by harsh conditions during operation of novel power vertical double-diffused MOS (VDMOS) transistors in different applications. Namely, these devices are very attractive for various specific applications in power control³⁷⁾ because of their numerous advantages (high breakdown voltage, high input impedance, high thermal stability, high switching speed, high current driving capabilities as well as production cost). This interest has continuously risen during the last decades.^{20–22,25–37)}

The results have shown that ionizing irradiation may reduce system lifetime that could be caused by degradation of several electrical parameters of power MOS transistors, especially threshold voltage (V_T) as the most important one. It should be noted that negative threshold voltage shift (ΔV_T) induced by radiation is the most critical reliability problem since it may cause change of operation mode from enhancement to depletion in n-channel power MOS transistors or dramatically reduction of current driving capability in p-channel ones. The negative threshold voltage shift increases with total dose received and is influenced by build-up of both oxide trapped charge and interface traps.^{20–22,38,39)}

Earlier studies of MOS device instabilities have shown that the effects of radiation and high electric field stress are very similar,^40,41) which applies to power VDMOS transistors as well.⁴²⁾ These observations led to the idea that electrical stress could be utilized as a method for accelerated testing (in order to reduce costs of expensive irradiation tests in device test procedure), as well as for the radiation hardening of devices for application in the radiation environment.⁴³⁾ However, subsequent investigations performed on power VDMOS transistors have clearly pointed to inapplicability of electrical stress for radiation hardening⁴⁴⁾ and indicated only partial similarities between the effects of irradiation and electrical stress.^5,45–48)

Beside the above effects, negative bias temperature instability (NBTI) is observed in p-channel MOS transistors operated at temperatures ranging from 100 to 250 °C at gate voltages producing gate oxide electric fields in the range 2–6 MV/cm.^7,8) These electric fields and temperatures are typically found during the device burn-in tests,²⁶⁾ but also can be approached in numerous applications during the routine operation of power MOS transistors at high current and voltage levels, which lead to both self heating and increased gate oxide fields.³⁰⁾ As a result, important electrical parameters of power VDMOS transistors can be degraded by NBT stress. As in the case of irradiation, the most critical reliability problem is the negative threshold voltage shift due to the build-up of oxide trapped charge and interface traps, which is more pronounced at NBT stresses under the higher temperatures and/or electric fields.³²⁾

Numerous investigations revealed high vulnerability of PMOS transistors to a single stress. However, the devices in some applications may even be subjected to simultaneous or consecutive NBT and irradiation stresses, and during operation in radiation environment at higher temperature or at maximum power the mechanisms responsible for both irradiation and NBTI effects can be activated. For example, satellite electronic equipment used in space is continuously exposed to cosmic irradiation with no air convection cooling mechanisms present, so the active p-channel MOS devices may be subjected to both irradiation and NBT stress, while the back-up devices in redundant systems are subjected only to irradiation.

Generally, devices in real applications may be subjected to multiple stresses and recovery, where the stressing scenario and corresponding final effects on device characteristics depend on specific applications and device mission. Hence, it is interesting to study the effects of specific kind of stress in devices that previously had already been stressed by the same or other type of stress. The effects of consecutive irradiation, NBT stress and annealing on threshold voltage of p-channel power VDMOS transistor have been presented in our previous paper.³⁴⁾ However, it is also of great importance to analyse mechanisms responsible for the observed effects, as their clarification may improve possibilities of predicting device behaviour in specific application. Also, there is interest in modelling of device characteristics under severe conditions, which may contribute to the prediction of device behaviour upon appropriate conditions.^49,50)

In this paper, the behaviour of transfer characteristics and corresponding threshold voltage shifts ΔV_T during consecutive irradiation, NBT stress and annealing of p-channel power VDMOS transistors has been presented and analysed in detail, with focus on mechanisms responsible for the observed changes in oxide trapped charge and interface trap densities. Namely, for proper understanding of the effects induced by applied stresses, changes in the electrical parameters of investigated power VDMOS transistors cannot be analysed considering device as a "black box" that gives an output if some kind of stress is applied as an input, and it is important to analyse in detail mechanisms responsible for the observed effects instead. For this reason, clarification of behaviours and nature of oxide and interface defects created during and after the stress is very important in view of device stability and resistivity to applied stress. Accordingly, in this paper the changes in oxide trapped charge and interface trapped charge densities are also presented and analysed in terms of responsible mechanisms. As a result, elucidation of created defects nature may contribute to general understanding of MOS devices behaviour during operation in severe conditions.

The commercial p-channel power VDMOS transistors IRF 9520 were used as experimental samples. These transistors were realized in standard polycrystalline Si (poly-Si) gate technology with hexagonal cell geometry and gate oxide thickness of about 100 nm and encapsulated in TO-220 plastic cases. The devices were with nominal drain current of 6.8 A, and drain-to-source breakdown voltage of 100 V. The initial threshold voltage of virgin devices was approximately V_T0 ≈ −3.6 V.

During the investigation two consecutive gamma irradiation (RAD) and negative bias temperature (NBT) stress experiments were realized. The experimental procedure of the first experiment (NBT-RAD) consisted of NBT stress followed by short spontaneous recovery (T = 25 °C for 24 h), irradiation, spontaneous recovery (T = 25 °C for 168 h), and thermal annealing. The experimental procedure of the second experiment (RAD-NBT) consisted of irradiation followed by short spontaneous recovery (T = 25 °C for 24 h), NBT stress, spontaneous recovery (T = 25 °C for 168 h), and thermal annealing.

In both experiments, NBT stressing, irradiation, spontaneous recovery, and thermal annealing were done under the same conditions. NBT stressing was performed in thermally stabilized Heraeus chambers at 175 °C for the total stress time of 168 h, with device gates biased at V_G = −45 V, while the source and drain terminals were grounded. The stress temperature and voltage values were chosen to produce significant threshold voltage shift. Those conditions have earlier been found to highly enhance NBTI in power VDMOSFETs.³⁰⁾ Gamma irradiation was performed in metrological Laboratory for Radiation Protection and Dosimetry at Institute for Nuclear Sciences, Vinča in Serbia. Devices were irradiated by Co-60 gamma-ray source with dose rate of 0.5 Gy(SiO₂)/min up to the total dose of 75 Gy (total duration of 150 min). In both experiments, devices from the one group were irradiated without gate voltage applied, while devices from the another two groups were irradiated under positive (+10 V) and negative (−10 V) gate voltage. The source and drain terminals of all devices were grounded. Decision to irradiate devices up to relatively low dose level of 75 Gy in the current study was based on our previous experience with irradiation experiments,^21,34) in order to avoid significant radiation-induced device degradation that could mask the NBT stress induced degradation.

Since NBT stressing and irradiation were performed in two laboratories located at different places, it was necessary to include the phase of short spontaneous recovery (24 h) between the two stresses in both experiments. Both phases of spontaneous recovery, the short one (24 h) after initial stress and long one (168 h) after the next stress, were carried out at room temperature (T = 25 °C) without device biasing. The final phase of experiment, thermal annealing, was performed at T = 175 °C, in total duration of 168 h without any bias applied.

Devices were electrically characterized using the highly precise source measurement units (SMUs) Keithley 237 (for drain biasing and drain current measurement) and Keithley 2400 (for sweeping the gate voltage), both controlled by PC over IEEE 488 GPIB. In order to monitor the progress of induced degradation, NBT stressing, irradiation, spontaneous recovery and annealing were interrupted after some pre-defined periods to measure the device transfer I_D–V_GS characteristics, and all measurements were done at room temperature.

Typical transfer characteristics of virgin and stressed devices after each phase of experimental procedure (without and with positive gate voltage applied during irradiation) are presented in Fig. 1 for NBT-RAD and RAD-NBT experiments.

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From Fig. 1(a) (NBT-RAD experiment) it can be seen that NBT stress has induced the shift of transfer characteristics toward higher absolute values of V_GS. Transfer characteristics have been shifted further toward higher absolute values of V_GS by the subsequent irradiation. The shift induced by irradiation was more pronounced in the case of gate voltage applied. During annealing transfer characteristics have been shifted in the opposite direction, toward lower absolute values of V_GS. Although this shift was more pronounced in the devices with gate voltage applied during irradiation, the position of transfer characteristic after annealing was at higher V_GS absolute value than in the case of devices irradiated without gate voltage applied during irradiation. It is interesting that in the case of devices with gate voltage applied during irradiation transfer characteristics after annealing were at the higher V_GS absolute values then after NBT stress, in contrast to the case of no gate voltage applied. The changes of the slope of transfer characteristics during NBT-RAD experiment were not significant.

From Fig. 1(b) (RAD-NBT experiment) it can be seen that irradiation has also induced the shift of transfer characteristics toward higher absolute values of V_GS. This shift was more pronounced in the case of gate voltage applied. The subsequent NBT stress has induced additional shift of transfer characteristics toward higher absolute values of V_GS in devices irradiated without gate voltage applied. However, in the case of gate voltage applied during irradiation, the subsequent NBT stress induced shift toward the lower absolute values of V_GS than that achieved during irradiation. During annealing transfer characteristics have been shifted toward lower absolute values of V_GS in all devices. As can be seen, this shift was more pronounced in the case of devices with gate voltage applied during irradiation. It is interesting that for devices irradiated without gate voltage applied, for given experimental conditions, the position of transfer characteristic after annealing was almost the same as the one after previous irradiation. However, it can be seen that the slope of these characteristics was not the same. It should be emphasized that, during both experiments, transfer characteristics shifts in the case of negative gate voltage applied during irradiation were similar to those in the case of positive gate voltage applied, but somewhat less pronounced.

Threshold voltage was extracted from the measured above-threshold transfer characteristics as the intersection between the V_G-axis and extrapolated linear region of $\sqrt{I_{\text{D}}} \text{--}V_{\text{G}}$ curves. Threshold voltage behaviour during experimental procedures,³⁴⁾ is shown in Fig. 2 for NBT-RAD experiment, and in Fig. 3 for RAD-NBT experiment. As can be seen in Fig. 2 (NBT-RAD experiment), NBT stress has caused negative threshold voltage shifts ΔV_T of approximately 0.3 V in virgin devices [Fig. 2(a)]. Irradiation performed after NBT stress has produced the additional negative threshold voltage shifts [Fig. 2(b)], also according to transfer characteristics shifts in all devices. An additional shift of 0.2 V was obtained in devices irradiated without gate voltage applied, while the shift in devices irradiated with gate voltage applied (somewhat more pronounced in the case of positive gate voltage applied), was almost four times higher. During the last experimental step (168 h of annealing at 175 °C), threshold voltage shift has significantly decreased in all devices [Fig. 2(c)]. Also, it can be noticed that absolute value of threshold voltage shift after annealing in devices irradiated without gate bias applied was lower than after NBT stress, while the shifts in those irradiated with gate bias applied were higher than after NBT stress.

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It can be seen in Fig. 3 (RAD-NBT experiment) that irradiation of virgin devices induced significant negative threshold voltage shifts, which increased with total dose received and depended on applied gate bias, that the shift in devices irradiated without gate voltage applied was somewhat higher than 0.2 V, while in devices irradiated with gate voltage applied, the shift (somewhat more pronounced in the case of positive gate voltage applied) was also almost four times higher [Fig. 3(a)]. Obviously, the observed shifts of threshold voltage are generally the same as those found after irradiation of devices previously subjected to NBT stress [Fig. 2(b)]. It seems that previous NBT stress did not affect ΔV_T caused by subsequent irradiation (Fig. 2). On the other hand, NBT stress after irradiation [Fig. 3(b)] caused different threshold voltage behaviour in devices previously irradiated with and without gate voltage applied. Namely, in the case of devices irradiated without gate voltage applied subsequent NBT stress induced further negative threshold voltage shift, while in the case of devices irradiated with gate voltage applied subsequent NBT stress has actually lead to the decrease of threshold voltage shift. Finally, during the last experimental step (168 h of annealing at 175 °C), threshold voltage shift significantly decreased [Fig. 3(c)] in all devices. It is interesting that threshold voltage shift in devices irradiated without gate voltage applied was just a little lower after annealing than after irradiation, while the shifts in those irradiated with gate voltage applied were significantly lower than after irradiation.

It should be mentioned that short spontaneous recovery (Spontaneous Recovery 1 — during 24 h at room temperature) after the first stress, as well as spontaneous recovery (Spontaneous Recovery 2 — during 168 h at room temperature) after the second stress (and before annealing), in both experiments, did not have substantial effect on threshold voltage behaviour, as can be seen from both Figs. 2 and 3.

The observed changes of threshold voltage are known to be the consequence of underlying changes in the densities of oxide-trapped charge (ΔN_ot) and interface traps (ΔN_it). So, for a complete analysis of the experimental results, it was necessary to determine changes in the densities of oxide-trapped charge and interface traps in our experimental samples during all experimental procedures. For this purpose, a simple and reliable subthreshold midgap technique (SMGT), based on measured subthreshold I–V transfer characteristics, was used.⁵¹⁾ Namely, because at midgap voltage which corresponds to calculated midgap current interface traps are neutral, the difference of midgap voltages ΔV_MG of stressed and virgin device is proportional to ΔN_ot. On the other hand, the difference of stretchout voltages ΔV_SO of stressed and virgin device is proportional to ΔN_it, where stretchout voltage is the difference of threshold and midgap voltages. So, the changes of oxide trapped charges and interface traps densities are determined as ΔN_ot = ΔV_MGC_ox/q and ΔN_it = ΔV_SOC_ox/q, respectively.

Typical subthreshold characteristics during NBT-RAD experiment are presented in Figs. 4 and 5. It can be seen in Fig. 4 that subthreshold characteristics were shifted toward higher absolute values of V_GS during NBT stress. The subsequent irradiation induced further continuous shift of subthreshold characteristics toward higher absolute values of V_GS in all devices, which was more pronounced in the case of irradiation with gate voltage applied (slightly more pronounced in the case of V_G = +10 V than in the case of V_G = −10 V). During irradiation of devices without gate voltage applied, as well as during previous NBT stress, it was not possible to observe significant changes in the slope of characteristics. On the other hand, certain decrease of the characteristics slope could be observed in devices irradiated under gate voltage applied. During annealing (Fig. 5), a continuous shift of characteristics toward lower absolute values of V_GS was observed, and was more pronounced in devices with gate voltage applied during previous irradiation.

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Typical subthreshold characteristics during RAD-NBT experiment are presented in Figs. 6 and 7. It can be seen from Fig. 6 that radiation (inserted figures) has induced continuous shift of characteristics toward higher absolute values of V_GS in all devices, which was more pronounced in the case of gate voltage applied. Also, in this case some changes of the characteristics slope were observed. Besides that, subsequent NBT stress in these devices has induced opposite shift of characteristics toward lower absolute values of V_GS than those achieved during irradiation. In this case some decrease of characteristics slope was observed. In contrast, subsequent NBT stress in devices irradiated without gate voltage applied, induced additional shift of characteristics toward higher absolute values of V_GS, with no pronounced changes in the slope observed. During annealing (Fig. 7), the shift of characteristics toward lower absolute values of V_GS than after irradiation was observed in all devices. This shift was more pronounced for devices irradiated with gate voltage applied. Some increase in the slope of the characteristics was also observed in all devices. Also, it should be mentioned that, during both experiments, subthreshold characteristics behaviours in the case of negative gate voltage applied during irradiation were similar to those in the case of positive gate voltage applied, but their shifts were somewhat less pronounced.

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The corresponding changes in gate oxide charge and interface trap densities are shown in Figs. 8–11. In Fig. 8 (NBT-RAD experiment) it can be seen that during NBT stress [Fig. 8(a)] the values of ΔN_ot after sudden increase at first 15 h of stress were followed by their very light increase. However, during the subsequent irradiation [Fig. 8(b)], the values of ΔN_ot have significantly increased in all irradiated devices (without and with gate voltage applied during irradiation). This increase was more intensive in the case of gate bias applied. During the first 15 h of thermal annealing [Fig. 8(c)], some oscillations of ΔN_ot values were observed, but generally with significant tendency to decrease. This was followed by light decrease in all irradiated devices, which was somewhat faster in the case of gate bias applied.

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Figure 9 (NBT-RAD experiment) shows that during NBT stress [Fig. 9(a)] the values of ΔN_it slightly increased. This small increase of ΔN_it continued during the subsequent irradiation [Fig. 9(b)], and was somewhat faster in the case of irradiation with gate bias applied. After some oscillations during initial period of annealing, the values of ΔN_it during annealing generally decreased (Fig. 9). The changes of ΔN_it during annealing have also been somewhat more pronounced in devices irradiated with gate bias applied.

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In Fig. 10 (RAD-NBT experiment) it can be seen that values of ΔN_ot during irradiation [Fig. 10(a)] significantly increased in all irradiated devices, and the increase was even more intensive in the case of gate bias applied. Initial phase of NBT stress [Fig. 10(b)] in devices previously irradiated with gate bias applied was characterized by alternating decrease and increase of ΔN_ot values (though with general tendency to decrease), which was followed by continuous decrease of ΔN_ot values until the end of NBT stress. Initial phase of NBT stress of devices previously irradiated without gate bias applied was also characterized by alternating decrease and increase of ΔN_ot values (but with generally increasing trend), which was followed by continuous decrease of ΔN_ot values up to the end of NBT stress. However, the changes of ΔN_ot values were more pronounced in the case of irradiation with gate bias applied. Similarly, the oscillations of ΔN_ot values in all devices have been observed at the beginning of thermal annealing as well [Fig. 10(c)]. The initial oscillations have been followed by their decrease until the end of annealing. Here we should note that the above behaviour of ΔN_ot was also observed in our previous HTGB and HTRB investigations.²⁶⁾ It should be also noted that numerous publications by other authors, which were related to investigation of different annealing treatments of previously irradiated devices, generally did not present data obtained at the beginning of the treatment.

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In Fig. 11 (RAD-NBT experiment) it can be seen that the changes of ΔN_it values during irradiation (which are somewhat higher in the case of irradiation with gate bias applied) were slightly increased [Fig. 11(a)]. However, the values of ΔN_it found at the beginning of the subsequent NBT stress [Fig. 11(b)] were higher than those found immediately after irradiation. The oscillations of ΔN_it values during the first part of NBT stresses were initially followed by a slight decrease and after that by an increase of ΔN_it values until the end of NBT stress. The ΔN_it values in the case of gate bias applied during irradiation were still more pronounced during NBT stress. During the thermal annealing [Fig. 11(c)] ΔN_it values slightly decreased. These changes are qualitatively the same as the changes of ΔN_it in RAD-NBT experiments, but the differences of their values are smaller.

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It should be emphasized that, during both experiments (NBT-RAD and RAD-NBT), changes of ΔN_ot and ΔN_it in the case of negative gate voltage applied during irradiation were similar to those in the case of positive gate voltage applied, but slightly less pronounced. Such changes of ΔN_ot and ΔN_it are in accordance to described behaviours of devices transfer characteristics.

From the behaviour of ΔN_ot and ΔN_it values during the performed experiments it is obvious that in all cases (with gate bias applied and with no gate bias applied) irradiation of previously NBT stressed devices leads to almost the same increment of ΔN_ot and ΔN_it as irradiation of virgin devices. It should be emphasized that irradiation phase in both experiments has contributed to consecutive defect formation. On the other hand, NBT stress effects in previously irradiated and virgin devices were different. While the NBT effects in virgin devices and devices previously irradiated without gate bias applied were similar (i.e., contributed to increase of defect density), the effects of NBT stress in devices previously irradiated with gate bias applied appeared similar to the effects of annealing, contributing to the decrease of defect density. The above changes of ΔN_ot and ΔN_it values have caused the corresponding behaviour of ΔV_T during NBT stress [Figs. 2(a) and 3(b)], which is shown and compared in Fig. 12.

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As mentioned before, numerous models for explanation of the mechanisms responsible for the N_ot and N_it changes during NBT and gamma radiation stress, as well as during the annealing of stressed devices, are published in the literature. The proposed electro-chemical reactions in these models are based on the charge traps precursors existing in the gate oxide and at SiO₂–Si interfaces.

The results obtained in this investigation can be explained by models based on transport of hydrogen species (H^•, H₂, H⁺, OH^•, H₂O, H₃O⁺). These models include reactions at Si–SiO₂ interface involving holes and various hydrogen species (neutral or charged), followed by their transport through the oxide. The presence of mentioned hydrogen species is associated with the presence of hydrogen as a common impurity in MOS devices.

4.1. NBT stress

Investigated VDMOS devices normally operate at lower gate voltages (±20 V). However, regarding the thick gate oxide, accelerated NBT stressing of these devices requires specific testing and instrumentation for application of gate stress voltages even over 40 V.^52–55)

Widely explored assumption is that electric field applied during typical NBT stress can dissociate interfacial Si–H bonds leading to the release of hydrogen and creation of interface traps.^7,9,10) In this study the stress electric field of 4.5 MV/cm falls in the range typical for NBTI (2–6 MV/cm). As the binding energies of Si–H bonds have actually been reported to exhibit Gaussian broadening,^56,57) typical NBTI conditions may suffice to break at least some of the weaker bonds and thus initiate degradation at the interface.

The obtained NBTI effects (as can be seen in Figs. 8–11) in the performed experiments are different, so it is logical to propose different responsible mechanisms. Thus, the buildup of N_ot (positive charged oxide traps) under the high negative oxide field at elevated temperatures during the NBT stress, presented in Fig. 8(a) (NBT-RAD experiment), can be attributed to hole trapping at oxygen vacancy defects³⁰⁾ and at dangling Si–H bonds near the SiO₂–Si interface:

$$\begin{align} &\text{O$_{3}$$\equiv$Si$^{\bullet}$ $^{\bullet}$Si$\equiv$O$_{3}$} + \text{h$^{+}$} \rightarrow \text{O$_{3}$$\equiv$Si$^{+}$ $^{\bullet}$Si$\equiv$O$_{3}$}, \end{align} \tag{ 1 }$$

$$\begin{align} &\text{O$_{3}$$\equiv$Si--H} + \text{h$^{+}$} \rightarrow \text{O$_{3}$$\equiv$Si$^{+}$} + \text{H$^{\bullet}$}. \end{align} \tag{ 2 }$$

The buildup of N_it during the NBT stress, presented in Fig. 9(a) (NBT-RAD experiment), can also be ascribed to mutual influence of high electric field and increased temperature when Si–H bonds at the SiO₂–Si interface can dissociate:⁷⁾

$$\begin{equation} \text{Si$_{3}$$\equiv$Si--H} \leftrightarrow \text{Si$_{3}$$\equiv$Si$^{\bullet}$} + \text{H$^{\bullet}$}. \end{equation} \tag{ 3 }$$

Released hydrogen atoms are highly reactive and they also can dissociate the interfacial Si–H bonds, thus leading to additional creation of interface traps:^7,9,58)

$$\begin{equation} \text{Si$_{3}$$\equiv$Si--H} + \text{H$^{\bullet}$} \leftrightarrow \text{Si$_{3}$$\equiv$Si$^{\bullet}$} + \text{H$_{2}$}. \end{equation} \tag{ 4 }$$

Note that the reactions between H^• atoms and holes from the substrate are also possible:⁵⁸⁾

$$\begin{equation} \text{H$^{\bullet}$} + \text{h$^{+}$}\leftrightarrow \text{H$^{+}$}. \end{equation} \tag{ 5 }$$

Formed H⁺ ions, which are drifting away from the interface under the negative oxide field, can dissociate the Si–H bonds in the gate oxide near the interface:^7,58)

$$\begin{equation} \text{O$_{3}$$\equiv$Si--H} + \text{H$^{+}$}\leftrightarrow \text{O$_{3}$$\equiv$Si$^{+}$} + \text{H$_{2}$}. \end{equation} \tag{ 6 }$$

In this way hydrogen ions can additionally contribute to increase of N_ot. It should be emphasized that above reactions (3)–(6) can also occur in the opposite direction.

The trapped positive charge gradually decreases local electric field in the vicinity of SiO₂–Si interface, leading to slower buildup of N_ot as the stress time increases. Also, the trapped oxide charge may be transformed into the interface traps in the later phase of NBT stress:³⁰⁾

$$\begin{align} &\text{O$_{3}$$\equiv$Si$^{+}$ $^{\bullet}$S$\equiv$O$_{3}$} + \text{Si$_{3}$$\equiv$Si--H} + \text{e$^{-}$}\\&\quad\rightarrow \text{Si$_{3}$$\equiv$Si$^{\bullet}$} + \text{O$_{3}$$\equiv$Si$^{\bullet}$ $^{\bullet}$Si$\equiv$O$_{3}$} + \text{H$^{\bullet}$}, \end{align} \tag{ 7 }$$

$$\begin{align} &\text{O$_{3}$$\equiv$Si$^{+}$} + \text{Si$_{3}$$\equiv$Si--H} + \text{e$^{-}$} \\&\quad\rightarrow \text{Si$_{3}$$\equiv$Si$^{\bullet}$} + \text{O$_{3}$$\equiv$Si$^{\bullet}$} + \text{H$^{\bullet}$}. \end{align} \tag{ 8 }$$

On the other hand, two mechanisms might be responsible for the effects observed during the NBT stressing after irradiation (RAD-NBT experiment) presented in Figs. 10(b) and 11(b). The first one is the activation of electrochemical reactions contributing to NBTI, which leads to additional creation of oxide charge and interface traps, and another is annealing/transformation of irradiation-induced oxide charge due to high temperature (175 °C) applied. The density of defects induced during irradiation at zero gate bias was rather small. That is why the number of available defect precursors remained rather high, so the subsequent NBT stress in this case has been dominantly accompanied by additional defect creation (the final values of N_ot and N_it densities are somewhat higher than their initial values during NBT stress, which indicates that mechanisms responsible for NBT instabilities — reactions 1–6 are dominant). In general, the observed effects of NBT on N_ot and N_it during these conditions are similar to behaviours during NBT stress of virgin devices. However, some decrease of N_ot could be observed after one hour of NBT stress, indicating the more pronounced transformation mechanisms of N_ot and N_it. On the other hand, irradiation with gate bias applied produced much higher density of defects (slightly more pronounced in the case of V_G = +10 V than in the case of V_G = −10 V). Hence, the annealing/transformation of these defects was actually dominant over the new defect creation during the subsequent NBT stress, thus leading to significantly lower N_ot at the end of stress than that at its beginning. A slight simultaneous increase of N_it is the consequence of transformation of N_ot in N_it.

The final value of N_ot after annealing is smaller in RAD-NBT experiment (with gate bias applied) than that in NBT-RAD experiment [Figs. 8(c) and 10(c)]. The reason for observed effect is N_ot decrease during NBT stress [Fig. 10(b)], which also leads to smaller annealing rate in this case.

It should be emphasized that the presented results obtained during NBT stressing of power VDMOSFETs represent mostly permanent (non recoverable) component and perhaps only the slowest part of the recoverable component of NBT stress induced degradation.^6,36) Namely, due to delay time for measurement we generally refrain ourselves from discussing the quickly recoverable component of degradation and only consider cummulative data, mostly related to the permanent component and slow component of degradation that does not recover so quickly.

4.2. Irradiation

Regarding different behaviour of N_ot [Figs. 8(a) and 10(a)] and N_it [Figs. 9(a) and 11(a)] in irradiated and NBT stressed devices, it must be emphasized that the mechanisms occurring during irradiation are in fact different from those occurring during NBT stress, although the number of related electro-chemical reactions involving hydrogen species and holes seem almost the same. The well known consequence of reactions occurring during the irradiation is the buildup of N_ot and N_it, which can be seen in Figs. 10(a) and 11(a) (RAD-NBT experiment), as well as in Figs. 8(b) and 9(b) (NBT-RAD experiment). Namely, a high energy gamma-radiation (MeV in magnitude) breaks not only the weak Si–H and Si–OH bonds in the oxide, but also the regular Si–O–Si bonds:

$$\begin{align} &\text{O$_{3}$$\equiv$Si--H (O$_{3}$$\equiv$Si--OH)} \\&\quad\xrightarrow{h\nu} \text{O$\equiv$Si$^{\bullet}$} + \text{H$^{\bullet}$ (OH$^{\bullet}$)} + \text{e$^{-}$} + \text{h$^{+}$}, \end{align} \tag{ 9 }$$

$$\begin{align} &\text{O$_{3}$$\equiv$Si--O--Si$\equiv$O$_{3}$}\\&\quad\xrightarrow{h\nu} \text{O$_{3}$$\equiv$Si$^{\bullet}$} + \text{O$_{3}$$\equiv$Si--O$^{\bullet}$} + \text{e$^{-}$} + \text{h$^{+}$}. \end{align} \tag{ 10 }$$

During irradiation, the part of the created e⁻–h⁺ pairs can be recombined, so the broken atomic bonds can be reestablished.³⁾ Also, covalent atomic bonds in the oxide can be broken by electrons that escaped the recombination, the process being more dominant than breaking the bonds by radiation.²¹⁾ Thus, new e⁻–h⁺ pairs can be formed. The electrons will be almost immediately removed through the gate (within picoseconds³⁹⁾) in the case of V_G = +10 V. On the other hand, in the case of V_G = −10 V electrons will be removed through the semiconductor (bulk is internally connected to source, which is grounded during irradiation).

The holes move toward the SiO₂–Si interface, supported by the local electric field in the case of no bias applied or by both local and external electric fields in the case of positive gate bias applied. The holes arriving near the SiO₂–Si interface react with numerous trap precursors, leading to N_ot increase:

$$\begin{equation} \text{O$_{3}$$\equiv$Si$^{\bullet}$} + \text{h$^{+}$} \rightarrow \text{O$_{3}$$\equiv$Si$^{+}$}. \end{equation} \tag{ 11 }$$

Considering that the holes are trapped very close to the top of oxide valence band, the probability of their excitation into the oxide valence band is very high:

$$\begin{equation} \text{O$_{3}$$\equiv$Si$^{+}$} \rightarrow \text{O$_{3}$$\equiv$Si$^{\bullet}$} + \text{h$^{+}$}. \end{equation} \tag{ 12 }$$

A fraction of the holes may dissociate weak Si–H and Si–OH bonds and can be trapped again in the oxide contributing to N_ot increase:

$$\begin{equation} \text{h$^{+}$} + \text{O$_{3}$$\equiv$Si--H (O$_{3}$$\equiv$Si--OH)} \rightarrow \text{O$_{3}$$\equiv$Si$^{+}$} + \text{H$^{\bullet}$ (OH$^{\bullet}$)}. \end{equation} \tag{ 13 }$$

Another fraction of the holes could be trapped at oxide defects, such as oxygen vacancies, also contributing to N_ot increase by a reaction identical to (1). Note that holes in this case can also react with hydrogen atoms forming the ions [reaction (5)]. These hydrogen ions also could contribute to the oxide trapped charge increase.⁵⁸⁾ Released holes can dissociate weak Si₃≡Si–H and Si₃≡Si–OH bonds at the interface creating interface traps:

$$\begin{align} &\text{h$^{+}$} + \text{Si$_{3}$$\equiv$Si--H (Si$_{3}$$\equiv$Si--OH)} + \text{e$^{-}$ (from Si)}\\&\quad\rightarrow \text{Si$_{3}$$\equiv$Si$^{\bullet}$} + \text{H$^{\bullet}$ (OH$^{\bullet}$)}. \end{align} \tag{ 14 }$$

Similarly, hydrogen ions can also contribute to creation of interface traps:

$$\begin{align} &\text{H$^{+}$} + \text{Si$_{3}$$\equiv$Si--H (Si$_{3}$$\equiv$Si--OH)} + \text{e$^{-}$ (from Si)}\\&\quad\rightarrow \text{Si$_{3}$$\equiv$Si$^{\bullet}$} + \text{H$_{2}$ (H$_{2}$O)}. \end{align} \tag{ 15 }$$

It is obvious that irradiation under the gate bias applied in both experiments (NBT-RAD and RAD-NBT) leads to significantly higher increase of N_ot and N_it (somewhat higher in the case of V_G = +10 V than in the case of V_G = −10 V), then irradiation without gate bias applied. These results are in good agreement with the results of low-dose bias irradiation experiment (up to 150 Gy at ±9 V), by Johnson et al., performed on power p-channel DMOS devices at cryogenic temperatures.⁵⁹⁾ The reason for these differences is found in electric-field dependence of radiation effects.³⁹⁾ The higher the electric field, the more unrecombined holes remain trapped on O₃≡Si^{• •}Si≡O₃ defects.

In addition, a small difference between effects of irradiation with +10 and −10 V gate bias can be explained by small difference between the corresponding values of electric field in the oxide, which affects the removal of electrons. Namely, the value of oxide electric field is somewhat higher in the case of positive gate bias (accumulation) than in the case of negative gate bias (strong inversion) because the difference in surface potential is about 0.8 V, so the irradiation effects at positive gate bias are somewhat more pronounced. A small positive electric field exists in the oxide as a consequence of small work-function difference between the poly-Si gate and n-bulk of pMOSFET, even in the case of zero bias. Because the fractional yield of holes for Co-60 source is very sensitive at lower electric fields,⁶⁰⁾ radiation response is evident even in the case of V_G = 0 V.

Positive electric field in the oxide, not only efficiently separates generated carriers, but also forces the motion of positive gate oxide charge toward the interface (SiO₂–Si) over the hole hopping process,⁶¹⁾ while negative electric field forces their motion toward the gate. Small difference in radiation responses between devices irradiated at V_G = +10 and −10 V suggests that gate oxide charge has not been moved deeper into the oxide by negative electric field.

Also, the final values of N_ot and N_it after irradiation of previously NBT stressed devices are significantly higher than values of N_ot and N_it after irradiation of virgin devices. However, the rates of radiation-induced increase of both N_ot and N_it is somewhat lower in the case of previously NBT stressed devices, and the reason is found in reduced number of defect precursors after NBT stress.

4.3. Annealing

Annealing step has been only thermally supported (without gate bias), so the observed decrease trend of N_ot and N_it values during annealing in both experiments [Figs. 8(c)–11(c)] might be in conjunction with diffusion of hydrogen molecules from the areas of high concentrations in oxide toward lower concentrations near the interface. The hydrogen molecules can be cracked not only at charged O₃≡Si⁺ oxide traps by the reverse reaction (6), but also at O₃≡Si^{+ •}Si≡O₃ by the reaction:

$$\begin{equation} \text{O$_{3}$$\equiv$Si$^{+}$ $^{\bullet}$Si$\equiv$O$_{3}$} + \text{H$_{2}$} \rightarrow \text{O$_{3}$$\equiv$Si--H} + \text{H$^{+}$}. \end{equation} \tag{ 16 }$$

The result of these reactions is neutralization of positive oxide traps accompanied by the release of H⁺ ions.⁶²⁾

The decrease of N_it during the annealing might be also attributed to the hydrogen species (molecule H₂ and highly reactive atom H^•) involved in reverse reactions (3) and (4).⁶³⁾ These reactions have obviously resulted in interface traps passivation.

Described mechanisms are reflected in the above changes of N_ot and N_it, which have caused the threshold voltage changes [Figs. 2(c) and 3(c)]. These results are in agreement with comparable published results, and they also correspond to so-called HDL model in interpreting irradiation effects and later in NBTI phenomena.⁶⁴⁾ The noticed change in tendency direction from decrease of N_it (RAD-NBT experiment) to increase (after more than 100 h of annealing) is quite possible to ascribe to border traps associated with hydrogen near the interface.⁵⁸⁾ The obtained results are also in excellent agreement with results regarding annealing of p-channel DMOS devices which have been low-dose bias irradiated at cryogenic temperatures.⁵⁹⁾

The results of consecutive irradiation, bias temperature stresses, and annealing of p-channel power VDMOSFETs have been reported in this paper. The purpose of this research has been to examine the specific stress effects in devices which previously have been subjected to the other stress. The results have shown that irradiation of previously NBT stressed devices activates the mechanisms of additional defect creation in the oxide and at the interface, leading to further increase of threshold voltage shift. On the other hand, NBT stress in previously irradiated devices has lead to different effects, depending on the irradiation conditions. In the case of irradiation with low irradiation doses or without gate bias, NBT stress has led to further device degradation indicating that mechanisms responsible for additional creation of oxide trapped charge and interface traps are dominant in the initial period of NBT stress. It is interesting that, under these conditions, mechanisms responsible for transformation of oxide trapped charge into interface traps are activated after one hour of NBT stress leading to slight decrease of N_ot. These mechanisms are more pronounced in the case of gate bias applied. Namely, in the case of irradiation with gate bias, NBT stress has led to gate oxide charge decrease and interface trap increase, indicating that mechanisms responsible for transformation are dominant. In this case, NBT stress practically had a positive role because that it annealed a part of irradiation-induced degradation.

This research was supported by the Ministry of Education, Science and Technological Development of the Republic of Serbia under Grants Nos. OI171026 and TR32026, and by Serbian Academy of Sciences and Arts (SASA) under the Grant No. F-148. Also, the authors would like to thank the staff of Metrological Laboratory for Radiation Protection and Dosimetry at the Institute for Nuclear Sciences, Vinča, Serbia, for providing the facilities for radiation experiments.