Scaling of three-dimensional interconnect technology incorporating low temperature bonds to pitches of 10 µm for infrared focal plane array applications

Infrared imaging arrays are uniquely suited to take advantage of advances in low temperature metal–metal bonding and through-silicon via (TSV) fabrication. These focal plane arrays (FPAs) rely on pixel-level electrical connections between the infrared detector layer and the silicon (Si) readout integrated circuit (ROIC). High-density area-array three-dimensional (3D) integration employing low temperature bonding makes it possible to stack multiple layers of ROICs under the detector layer, enabling dramatically more processing capability within each pixel.¹⁾ The 3D integration is particularly important as FPA manufacturers continue to decrease the pixel size in order to enhance the FPA performance and lower the power consumption and cost of imaging systems.²⁾

In our previous work, we demonstrated the use of high-density 3D integration employing low temperature epoxy bonding to fabricate massively parallel signal processors for FPA sensors; this work resulted in fully functional high performance infrared imagers.^3–5) Figure 1 illustrates the integration concept and shows cross-section scanning electron microscope (SEM) micrographs of a mercury–cadmium–telluride sensor array with the pixel size of 30 µm, integrated with a Si 3D ROIC. The 3D ROIC is composed of a thinned analog and a full thickness digital IC layer fabricated in bulk complementary metal–oxide–semiconductor (CMOS) technology and interconnected at the pixel level. Building on this functional demonstration, in this paper we present details of a 3D integration process that supports the interconnect density required for much smaller pixel sizes, 10 µm and below. The vias-last process that produced the 3D IC of Fig. 1 is not readily scalable to such small pixels due to the limitations associated with masking and etching high-aspect-ratio vias in thick silicon oxide (SiO₂) films. To avoid this limitation, we designed a second-generation process that uses a vias-middle approach in which the TSV fabrication is performed as part of the IC manufacture.^6–12) Figure 2 is a schematic representation of the 3D integration process applied to the integration of an analog IC with a digital IC to fabricate a 3D ROIC.⁵⁾ TSVs are inserted between front- and back-end-of-the-line portions of the analog CMOS process. The analog wafers with TSVs undergo thinning, which exposes the TSVs from the back. After the TSV reveal step, metal bond pads are formed over the TSVs. Both the analog and the full thickness digital wafers are diced, and known-good-die (KGD) from analog IC wafers are bonded to KGD from digital IC wafers using low temperature metal–metal bonds.

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Previous demonstrations of die-to-die integration of silicon device layers with copper (Cu)-filled TSVs and metal–metal bonds have focused on either small arrays or much larger pitches. For example, Huyghebaert et al. demonstrated small arrays of 5 µm diameter TSVs used in conjunction with Cu–Cu thermocompression bonds on a 10 µm pitch to interconnect 50-µm-thick Si die to full thickness Si die.¹³⁾ Wordeman et al. used Cu-filled TSVs 20 µm in diameter and 100 µm deep in conjunction with 50 µm pitch solder bonds to stack a silicon memory chip on a processor chip.¹⁴⁾

In distinction to the previous investigations, the objective of this work was to demonstrate 3D interconnects in area-array formats large enough to be of direct relevance for high-resolution infrared imaging sensors, and to demonstrate array operabilities approaching 100%. The proof-of-concept test vehicle employed 2 µm diameter, 15 µm deep TSVs positioned on 10 µm centers in 640 × 512 arrays. To enable a robust bonding across these large arrays, we used a Cu/tin (Sn)–Cu solid–liquid diffusion bonding process.^15–17) Relative to Cu–Cu thermocompression bonds, the Cu/Sn–Cu bonds offer the advantage of lower bonding temperature and more relaxed die planarity and bond pad height uniformity requirements, and — unlike solder bonds — they are scalable to 10 µm pitch. To increase the probability of a successful demonstration, given the smaller thickness target for thinned surrogate analog wafers than the commonly employed value of 50 or 100 µm,^6,18–20) we fabricated test vehicles in two lots using two different temporary wafer bonding systems to support device wafers through thinning and backside processing.

2.1. Design of test vehicle

The two-die stack test vehicle incorporates area arrays of TSVs and Cu/Sn–Cu bonds connected into daisy chains. The vertical interconnects are arrayed in a 640 × 512 format on a 10 µm pitch. Figure 3 shows the configuration of the daisy chains. Each test channel contains 1280 interconnects from four neighboring rows. There are 256 test channels.

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2.2. Fabrication of interconnect arrays

Passive Si wafers were used for the fabrication of the test vehicle. Surrogates for analog IC wafers were of the silicon-on-insulator (SOI) type to emulate a ROIC implemented in a thick film SOI CMOS process.^21,22) The thickness of the top Si and the buried oxide (BOX) layers in the SOI wafers were 15 and 2 µm, respectively. For the purpose of the proof-of-concept demonstration, TSVs were fabricated in-house, whereas in the ultimate implementation the TSV module will be executed by a CMOS foundry. The proxy fabrication process employed a conformal SiO₂ layer to serve as the TSV insulator and Cu deposited by metal–organic chemical vapor deposition (MOCVD) as the bulk of TSV metallization.²³⁾ Figure 4 shows a cross-section of a bulk Si monitor wafer following the deposition of Cu. The dashed lines added to the SEM micrograph indicate the position of the BOX layer in SOI device wafers.

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Following the TSV metallization, the Cu overburden on the top surface of the wafer was removed using chemical mechanical polishing (CMP), leaving Cu only in the blind vias.²⁴⁾ A thin film of tungsten was subsequently deposited on the top surface and patterned using reactive ion etching (RIE) to form the top links of the daisy chain connections. Figure 5 shows the plan-view SEM of the top routing pattern. The position of TSVs can be seen by the slight dimples in the metal lines.

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Figure 6 shows details of the processing that the wafer with TSVs and the top metal routing underwent in preparation for stacking.⁵⁾ The thinning process begins by mounting the wafer face down on a temporary carrier, using a layer of adhesive that is applied onto the carrier, as shown in Fig. 6(a). We used Si wafers as carriers. We used TMAT temporary adhesive material (Thin Materials AG) in one lot of wafers (lot 1) and WaferBOND 9001 material (Brewer Science) in the second lot (lot 2).^25,26) Top wafers in each of the two lots were thinned by backgrinding, followed by high-rate wet spin etching [Fig. 6(b)]. The BOX layer provided an effective etch stop for the thinning. In the next step, the BOX layer was removed using an RIE process. The wafers were then exposed to fluorine-containing plasma to recess the Si surrounding the insulated Cu TSVs [Fig. 6(c)]. Next, a conformal SiO₂ layer was deposited at 150 °C using a plasma-enhanced chemical vapor deposition (PECVD) technique to passivate the wafer surface and the exposed portion of the TSVs [Fig. 6(d)]. Then, as shown in Fig. 6(e), CMP was used to re-planarize the top surface. The fabrication of Cu/Sn bond pads, described in detail elsewhere,^27–29) completed the backside processing of the analog surrogate wafer [Fig. 6(f)]. The bond pads were 5 µm thick and 6 µm wide. Figure 7 shows an SEM micrograph of the backside of the analog surrogate wafer following the CMP step that exposes TSVs, and Fig. 8 shows a micrograph of electroplated Cu/Sn bond pads.

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Surrogates for digital wafers which provide bottom die for the stack underwent processing to form routing lines for daisy chains and probe pads. The process includes the deposition of a Ti/Cu seed layer on wafers coated with a 0.3 µm SiO₂ layer. Next, Cu is electroplated into a photoresist template to form 4 µm thick and 6 µm wide bond pads. Figure 9 shows an optical image of the routing pattern formed on the wafers.

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Completed analog and digital surrogate wafers were diced. During the dicing operation, the thinned analog surrogate remained on the carrier wafer. To maximize the die yield in the case of device wafers that were bonded to carrier wafers using the TMAT adhesive, we applied a dice-by-etch technique to singulate the wafers. This approach involves the fabrication of trenches in the dicing streets of the thinned wafers using RIE. The second step employs a standard dicing saw; the blade cuts through the adhesive and the thick carrier but does not come into contact with the thin Si layer.

Analog surrogate and digital surrogate die were integrated using Cu/Sn–Cu solid–liquid diffusion bonding at a temperature of 250 °C in an SET FC150 bonder with N₂ ambient atmosphere.^27,30) The bond pressure used was 50 MPa which correlates to approximately 0.1 g/bump. Before bonding, the Cu bond pads were treated with diluted sulfuric acid and the Cu/Sn bond pads were treated with plasma assisted dry soldering (PADS) process.³¹⁾ After the bonding was completed, carrier die were removed from the thin stacked die. Any adhesive residue was removed using solvents. Figure 10 presents an SEM micrograph of the top surface of a completed die stack. Figure 11 shows a cross-section of the interconnected test vehicle.⁵⁾

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Mechanical strength of the bonded die pairs was estimated through the measurement of the shear force required to separate full thickness monitor die pairs in a Nordson DAGE die shear apparatus. The measured value of the die shear force was greater than 10 kgf for the majority of tested die, translating into the die shear strength greater than 11 MPa, in agreement with our previously published data.^27,30) After die shear, Cu–Sn intermetallic was seen on the bond pads of both die indicating that the failure interface was in the Cu–Sn intermetallic. A smaller number of bond pads, usually near the corners of the die, were seen to have failed at the interface of the Ti adhesion layer to the silicon dioxide.

The bonded die pairs were electrically tested, with all channels of the test vehicle probed in a two-wire configuration to determine the channel resistance R. The measured R value contains contributions from TSVs, Cu/Sn–Cu bonds, metal lines connecting the vertical interconnects into chains, and probe-to-pad contacts. Figure 12 shows a plot of the channel resistance for each channel of one of the tested arrays. The average channel resistance for this sample, calculated excluding nonfunctional channels, was 647 Ω, and the standard deviation was 35 Ω. The channels in Fig. 12 with low resistance values are believed to contain a shorting path between the vertical interconnects in the neighboring rows of the daisy chain that effectively eliminated a portion of the tested channel. We will refer to such channels as shorted channels.

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In Fig. 13, we plot the average channel resistance for a set of bonded die. It can be seen that the channel resistance is consistent from sample to sample. In the same figure, we also plot the channel yield, which is defined as the ratio of the number of operational (conducting) channels to the total number of channels. We denoted as operational the channels with the resistance in the range from 540 to 750 Ω.

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Figure 14 shows a current–voltage plot for a single channel of 1280 TSVs in the two-wire configuration. The plot is linear, indicating ohmic contacts between TSVs, metal bonds, and metal routing lines. The resistance calculated from the slope of the straight line is equal to 707 Ω; an average resistance of one link of the chain is equal to 0.55 Ω. We also tested individual vertical interconnects in four-wire configurations, with the average resistance value of 0.34 Ω, smaller than the link resistance as expected.

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In the layout of the test die, each pair of neighboring channels contains 320 pairs of interconnects that are located 10 µm, center to center, from each other. Measurements of leakage currents between neighboring channels of interconnects can therefore be used to assess the effective isolation between vertical interconnects. Six randomly selected channel pairs were tested on three bonded die. The leakage current data from one of the die are shown in Fig. 15. All the channel pairs tested exhibited less than 15 pA of current at up to 5 V of applied bias, a resistance of over 330 GΩ, indicating good electrical isolation between neighboring interconnects.

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Table I shows a summary of the electrical tests for the two device lots corresponding to the two different temporary adhesive materials. The table lists values of the two-wire channel resistance, the four-wire TSV resistance, the number of open channels, the number of shorted channels, the channel yield (defined as the ratio of the number of functional channels, m, to the total number of tested non-shorted channels, M), and the calculated operability of the 640 × 512 array of interconnects. If we assume that the distribution of defective interconnects in the array is random, the probability P that a channel is conducting can be calculated as P = pⁿ, where p is the probability that an individual link, consisting of a routing line, TSV, and Cu/Sn–Cu bond, is conducting, and n is the number of interconnects in the channel. Since P = m/M, one can estimate the probability of a functional interconnect in the array as p = (m/M)^1/n.

As seen in Table I, both of the process splits resulted in the estimated interconnect operability greater than 99.99%, satisfying operability requirements of imaging arrays. Any small differences between values listed for the two lots are believed to reflect lot-to-lot process variations rather than factors specific to the use of the particular temporary adhesive.

We successfully integrated silicon die with high-density area array vertical interconnects consisting of TSVs and Cu/Sn–Cu bonds. The passive test vehicle emulated a 3D IC composed of digital and analog ICs for use as an advanced massively parallel signal processor for high-performance infrared imaging devices. The vertical interconnects were arrayed in a 640 × 512 format, with the pixel size of 10 µm. We have demonstrated the full integrated process, the key parts of which involve silicon wafer thinning to 15 µm, metal and dielectric thin film deposition and patterning on the back surface of the thin wafers, low temperature Cu/Sn–Cu bonding, and the carrier release. The calculated operability of the array of vertical interconnects exceeded 99.99%. The vertical interconnect resistance was found to be in the hundreds of milliohms range, within required specifications of infrared FPAs. The successful demonstration of the interconnect technology paves the way to a functional demonstration of 3D signal processors in infrared imagers with 10 µm pixels, currently in progress. Similar architectures and integration processes employing low temperature bonding can be applied to other advanced pixilated sensors or actuators.

This work was supported in part by the Defense Advanced Research Project Agency (DARPA). The views expressed are those of the authors and do not reflect the official policy or position of the Department of Defense or the U.S. Government. The authors thank the staff of the RTI Microfabrication Facility and RTI Analytical Laboratories for their contributions.