Near unity ideality factor for sidewall Schottky contacts on un-intentionally doped β-Ga₂O₃

β-Ga₂O₃ has recently attracted significant research interest because of its excellent intrinsic material properties, including the wide bandgap energy of 4.8 eV,¹⁾ the high breakdown field projected near 8 MV cm⁻¹²⁾ and the feasibility of n-type doping and contacts.^2–4) The availability of high quality bulk substrates^5,6) also ensures excellent device reliability under high electric field stress, making β-Ga₂O₃ especially promising for power switching applications. However, a significant drawback of the material system is the lack of p-type conduction because of a nearly flat energy dispersion profile in the valence band.^7,8) As a result, several unipolar device topologies have been investigated extensively, including both lateral transistors (MESFETs,^2,9) MOSFETs,^10–15) MODFETs^16–19)) and vertical devices (Schottky diodes^20–23) and vertical MISFETs²⁴⁾). Excellent device results with high breakdown voltage above 1 kV have been demonstrated for various device topologies.^22,24–26) However, the electrical properties of the β-Ga₂O₃ films was found to be sensitive to plasma damage,^14,27) and this brings significant challenges for the fabrication of novel device architectures. For instance, gate recess by inductively coupled plasma (ICP) etching has contributed to a substantial reduction of the channel mobility from 80 to 34 cm² V⁻¹ s⁻¹ for Si delta-doped MOSFETs.¹⁴⁾ Additionally, both vertical MISFETs²⁴⁾ and lateral fin-channel MOSFETs²⁸⁾ with thin channels defined by BCl₃-based plasma etching demonstrated low field effect mobility and high on-resistances, indicating signs of plasma damage-induced reduction of the electrical conductivity. Removal of the plasma damaged layer and sustaining low defect density after device fabrication is therefore essential for the realization of high performance β-Ga₂O₃ power switching devices.

Chemical wet etching has been utilized as an effective method for the removal of dry etching damages for a range of semiconductor devices, including TMAH etching for GaN vertical transistors,²⁹⁾ and thermal oxidation and subsequent HF etching for both Si³⁰⁾ and SiC³¹⁾ devices. However, wet etching methods have not been explored for the etch damage removal for β-Ga₂O₃ devices. While β-Ga₂O₃ is chemically unreactive at room temperature, it can be etched effectively in heated H₃PO₄, HNO₃ or H₂SO₄ solutions with an etch rate up to a few microns per hour.^32,33) Recently, we observed strong anisotropic etching behavior of β-Ga₂O₃ in hot H₃PO₄ solutions, which provides a great opportunity for the fabrication of ultra-scaled vertical devices with low sidewall damage. In this work, we report improved performance for lateral Schottky diodes fabricated on MOCVD-grown un-intentionally doped (UID) films through sidewall damage removal using hot phosphoric acid etch.

The UID β-Ga₂O₃ films were grown in an Agnitron Technology Agilis R&D MOCVD system.^34,35) A 3.2 μm thick epi-layer was grown at a rate of 0.8 μm h⁻¹ on 10 × 15 mm² (010)-oriented Fe-doped semi-insulating substrates from Novel Crystal Technology, Inc. The samples showed smooth surface morphology with rms surface roughness in the range of 0.5–0.8 nm for 20 × 20 μm² AFM scans. Both Hall measurement and capacitance–voltage measurement indicate a low free carrier concentration of 1 × 10¹⁶ cm⁻³ in the UID β-Ga₂O₃ layer. For the fabrication of lateral Schottky diodes, a 15 nm heavily doped n⁺-Ga₂O₃ contact layer was grown on the MOCVD-grown UID β-Ga₂O₃ film using oxygen plasma-assisted molecular beam epitaxy.³⁶⁾ Sn was used as n-type dopant for the contact layer with a doping concentration of 3 × 10¹⁹ cm⁻³ as estimated from secondary ion mass spectrometry measurement.

The sample was diced into 5 × 5 mm² pieces and further fabricated into sidewall Schottky diodes as shown in Fig. 1. A 350 nm SiO₂ layer was first deposited on the sample surface using plasma-enhanced chemical vapor deposition to protect the top surface of the β-Ga₂O₃ film from any etch damage. Then, deep mesa structures with a dimension of 80 × 25 μm² were patterned using BCl₃-based ICP etching.³⁷⁾ Surface profile measurement using Dektak confirmed an etch depth of 3.4 μm in the β-Ga₂O₃ film, which ensured complete removal of the 3.2 μm MOCVD-grown UID layer. To investigate the effect of anisotropic wet etching of the sidewalls on the Schottky diode performance, the long edges of the mesa structures were aligned to different [h0l] crystal orientations on the same sample. This was followed by wet etching of the samples in hot phosphoric acid (w.w. > 85%) at 140 °C as measured and feedback controlled by a thermocouple. Two samples with etch times of 6 and 12 min and a control sample without wet etching were prepared. Figure 2 shows the bird's eye SEM images measured at a tilt angle of 60° after different fabrication steps, as well as the illustrating schematics. Direct dry etching resulted in rough sidewalls as shown in Fig. 2(a). The sidewall SEM image of a device aligned to [001] direction for the sample wet etched in hot H₃PO₄ solution for 12 min is shown in Fig. 2(b), which demonstrated a significant reduction of the sidewall roughness. Additionally, the lateral etch removal of the [001]-oriented sidewalls is estimated to be 134 nm and 268 nm for 6 min and 12 min etches, respectively, making it possible to remove the dry etch damage.

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The Pt/Au (=40/30 nm) Schottky metal stack was deposited on the samples using e-beam evaporation with a planetary rotation setup, which enabled metal coverage on vertical mesa sidewalls. The metal layers on the top of the mesas were then lifted-off by the removal of the SiO₂ protection layer using buffered HF solution immersed in ultra-sonic bath. The samples etched in hot H₃PO₄ solutions were found to be especially favorable for the lift-off process because of the undercut formation through lateral sidewall etching as schematically shown in Fig. 1. Finally, a Ti/Au (= 30/120 nm) metal stack was deposited on the top of the mesa, followed by a rapid thermal annealing at 500 °C in N₂ ambient, to define ohmic cathode contact. To avoid sidewall Schottky contact to the heavily doped thin contact layer, the sample without phosphoric acid etching was then blankly etched for 18 nm using low power plasma etching. The SEM images of the devices post-fabrication are shown in Figs. 2(d) and 2(e). The Pt/Au Schottky contact remained on the sidewalls and there was a clear separation between the anode and cathode contacts. This was further confirmed by the cross-sectional SEM image shown in Fig. 2(f). Since the mesa structures were electrically isolated from the semi-insulating substrate, the fabricated lateral Schottky diodes provided a direct measurement of the sidewall properties.

The electrical characteristics of the sidewall Schottky diodes were compared for the samples without and with wet etching. Since a strong anisotropic etching behavior was observed for the sidewalls and this translated to differences in the electrical characteristics, the electrical performance of the devices aligned to [001] direction will be discussed first. A summary of the anisotropic behavior will be given at the end of the report.

The capacitance–voltage characteristics measured at 1 MHz of the sidewall Schottky diodes for the samples without wet etching and with a 12 min wet etching are compared in Fig. 3. The device without wet etching showed a large hysteresis with a voltage shift (∆V) up to 1 V between the forward and reverse scans. In comparison, the hysteresis for the [001]-oriented devices became negligible after sidewall etching, suggesting a significant reduction of the density of damage-induced traps through wet etching. 1/C² is expected to have a linear dependence on the applied bias for ideal Schottky diodes, and the Schottky barrier height could be extracted from the intercept on the voltage axis. While both samples could show deviations from the ideal case because of the highly non-uniform electric field profile, the sample without wet etching projected a substantially higher Schottky barrier height. This again indicates the existence of a parasitic capacitance because of interface defects formed after dry etching. The CV measurements showed negligible frequency dispersion for both the capacitance and conductance of the Schottky diodes in the frequency range from 1 kHz to 1 MHz. Therefore, the traps introduced by plasma damage could have a lifetime longer than 1 ms. Estimation of the trap density is challenging for the sidewall Schottky diodes due to the non-uniform electric field profile and the difficulty in the determination of the anode area. Further studies on the trap spectrum and the extraction of interface trap densities will be investigated.

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The current–voltage characteristics of the devices without wet etching is shown in Fig. 4. The device showed low reverse leakage current. However, the forward current showed strong hysteresis especially in the subthreshold region, which exhibited two distinct slopes and a positive voltage shift above 0.8 V between the forward and reverse voltage scans. The lower current in the subthreshold region during reverse scan is attributed to reduced trap assisted tunneling due to a larger depletion width. For the forward scan, the traps were empty initially and get filled during the forward voltage sweep, while the reverse scan started with traps being filled and the trapped electrons got emitted gradually during the scan. Because of the long trapping and emission lifetime, more traps could remain filled in the subthreshold region during the reverse scan. When traps are filled with electrons, the trapped negative charge reduces the net charge density in the depletion region to N_D⁺–N_t⁻ as shown schematically in Fig. 4(c), where N_D⁺ is the activated donor concentration and N_t⁻ is the trapped electron density in the depletion region. As a result, the same voltage bias leads to an increase in the depletion width during reverse voltage sweep, which then reduces the shunt leakage current through trap assisted tunneling in the subthreshold region as shown in Fig. 4(a). This also contributed to a better ideality factor of 1.7 for the reverse scan, as compared to 2.1 for the forward scan as shown in Fig. 4(b). However, both values are substantially worse than that for planar Schottky diodes^20–22,38) because of the existence of sidewall etch damages.

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The IV characteristics of the devices aligned to [001] direction after 12 min etching in hot H₃PO₄ are shown in Fig. 5(a). Apart from the low leakage current at reverse bias, the device showed negligible hysteresis and a clean subthreshold current. The ideality factor has a lowest value of 1.01, and it remained below 1.03 over 5 decades of the subthreshold current, suggesting a low trap density after sidewall etching in hot phosphoric acid.

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The anisotropic behavior of the devices aligned to different crystal orientations is summarized in Fig. 6. Because of the strong anisotropic etch rate of the sidewalls and the differences of the sidewall roughness after wet etching, both the ideality factor and the hysteresis of the applied bias showed variations for the devices. The sidewall etch rate of the devices in 140 °C H₃PO₄ solution are shown in Fig. 6(a). The etch rate varies from 0.2 to 2.2 μm h⁻¹ for different sidewalls. Most of the devices showed a positive correlation between the etch rate and the improvement of both the ideality factor and the subthreshold voltage hysteresis as shown in Fig. 6. The devices along [001] directions showed near unity ideality factor and low hysteresis after 6 min of wet etching because of the high lateral etch rate of the sidewalls. However, the devices aligned in the angular range between [203] and [201] directions showed high ideality factor after 6 min wet etching regardless of the higher etch rates. SEM measurement indicated slight roughening of those sidewalls rather than the smooth sidewalls observed for [001] oriented devices, and therefore, it could contribute to the high ideality factor. Longer etching resulted in near ideal sidewall Schottky diodes for the devices along almost all the directions. Those results suggest that wet etching in hot phosphoric acid could be an effective technique to remove the plasma damaged layers and recover a pristine surface for device fabrications.

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To conclude, we demonstrated an etch damage removal method for β-Ga₂O₃ devices using hot H₃PO₄ solution. Sidewall Schottky diodes were fabricated on a MOCVD-grown UID β-Ga₂O₃ film. The devices without wet etching for plasma damage removal showed high ideality factor and large hysteresis in both IV and CV measurements. Through wet etching in phosphoric acid heated at 140 °C, the sidewall Schottky diodes showed near unity ideality factor of 1.01 and absence of hysteresis. The anisotropic etching behavior of β-Ga₂O₃ was also evaluated. While the devices along various directions showed improved performance, the [001] direction was found to be a favorable direction for vertical device fabrications. The demonstrated anisotropic wet etching method for etch damage removal could be beneficial for various device applications, including vertical transistors and diodes, ultra-scaled devices, and it could enable a new paradigm of damage-free nano-electronics for β-Ga₂O₃.

Acknowledgments