High-performance InGaAs FinFETs with raised source/drain extensions

III–V high mobility semiconductors^1,2) are among the most promising materials to replace or complement silicon technology, mainly targeting low power and RF applications.^3,4) Therefore, achieving high-quality compound semiconductors integrated on silicon and featuring fabrication compatibility with standard CMOS technology is extremely important in order to enable this transition. Different integration techniques have been explored. Selective area growth schemes include aspect-ratio trapping^5,6) and template-assisted selective epitaxy.^7–10) These methods make possible the local integration of ultra-scaled structures as well as the direct nucleation on silicon, independently of the lattice mismatch. Alternatively, direct wafer bonding (DWB)¹¹⁾ provides large areas of III–V materials integrated on Si as well as pre-processed wafers, enabling 3D sequential integration (3DSI).^12–14) Moreover, III–V semiconductors benefit from a relatively small fabrication thermal budget (compared to silicon), making them particularly suitable 3DSI applications.

In(Ga)As n-FinFETs outperforming silicon state-of the art FinFETs have recently been demonstrated.^15–17) A main limitation of these kinds of devices is the parasitic bipolar effect (PBE), caused by the lack of body contacts due to insulator back-barrier or 3D geometries. Holes are accumulated in the channel and confined by the buried oxide layer. PBE enhances band-to-band tunneling (BTBT) current at the drain/channel interface and contributes to a further increase of the already significant off-current typical for InGaAs FETs, resulting from the narrow band gap of In-rich InGaAs.¹⁸⁾ 2D TCAD simulations on InGaAs FETs¹⁹⁾ have been shown to mitigate both BTBT as well as trap-assisted tunneling and therefore reduce the off-state transistor current. Moreover, the access resistance degradation due to ungated channel regions underneath the spacers can be prevented by the use of source-drain extensions.

In this work we experimentally demonstrate InGaAs FinFETs with improved off-state performance and among the highest reported I_ON for these kinds of devices.²⁰⁾ This is achieved by introducing carefully designed spacer extension regions. We characterize the spacer extensions in terms of dimensions, fabrication, material quality and influence on transistor performance.

The InGaAs FinFETs are fabricated with a replacement-metal-gate process that includes a raised source-drain (RSD) module and gate sidewalls spacers. A cross-section schematic of the fabricated transistor is shown in Fig. 1(a). A 20 nm thick InGaAs layer is transferred on a silicon substrate by DWB. The process starts with 2'' active InGaAs layer as well as an InGaAs/InAlAs etch-stop heterostructure grown by metal-organic chemical vapor deposition (MOCVD) on (100) InP at 550 °C. Next, a SiO₂ buried oxide layer is deposited on the III–V active layer and the adhesive layers are prepared. After cleaning the donor and substrate wafer by megasonic and ozone water, the wafers are brought to contact and annealed at 250 °C for two hours. The active III–V layer is then released from the donor wafer by wet etching in hydrochloric acid, stopping at the InGaAs/InAlAs etch-stop layers. The etch-stop layers are then wet-etched slowly to stop on the active layer, which completes the DWB process. As a result, a buried oxide layer 25 nm thick separates the InGaAs layer from the Si substrate. Following, InGaAs fins are patterned by using HSQ (Hydrogen Silsesquioxane) resist and dry etched. Next, we deposit an Al₂O₃ liner and 150 nm of amorphous silicon (dummy gate). The gates are then patterned by HSQ and etched with an optimized inductively-coupled plasma reactive ion etching process. A SiN_x layer is then deposited by atomic-layer deposition and dry etched by RIE, resulting in 10 nm sidewall spacers. At this point, doped extension regions are formed underneath the spacers as schematized in Fig. 1(b). Sn-doped InGaAs (n+) is then regrown by MOCVD at 550 °C to form RSD contacts. Then, an encapsulating inter-layer dielectric (ILD0) is deposited and planarized by chemical-mechanical polishing (CMP). Once the top part of the dummy gate is exposed, it can be removed by a selective dry etch process. High-k dielectric (a scaled bilayer of Al₂O₃/HfO₂) and TiN metal gate are deposited by plasma-enhanced atomic-layer deposition in the same step. Following, W is sputtered and planarized by CMP. Next, we deposit a second oxide layer (ILD0'). Finally, standard M1 metallization is performed, opening via on source, drain and gate. Figure 1(c) displays a high-resolution cross-sectional scanning-transmission electron microscope image for a finalized device with L_G = 60 nm. A zoomed-in view on the spacers/channel/RSD region is shown in Fig. 1(d).

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After forming the SiN_x sidewall spacers, we use a digital etching (DE) process to selectively remove parts of the InGaAs channel, as schematized in Fig. 2(a) (inset).^21,22) In order to maintain low access resistance, the target undercut thickness must be matched with the spacer thickness, to result in an accurate alignment of the junction position underneath the gate region. The DE is performed in two steps: 8 min oxidation in a UV–Ozone chamber and etching in HCl:H₂O (1:10). By measuring the channel thickness with atomic force microscopy (AFM), we determine the etching rate of 1 nm/cycle as shown in Fig. 2(a). Similar etch rates were observed for InP DE in another work.²³⁾ The stable etch rate achieved with this method is due to the approximately saturated oxidation of the InGaAs surface, following Lukeš' rate law.²⁴⁾ The diluted HCl subsequently completely etches the formed native oxide but is selective to the semiconductor itself. AFM measurements performed on the larger contacts area [visible in Fig. 2(d)] show significant improvement of InGaAs RMS surface roughness from 0.9 to 0.3 nm [Fig. 2(a)]. SEM pictures of the gated fins before and after the RSD steps are displayed in Figs. 2(b)–2(d).

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Figure 3(a) shows the transfer characteristic of an L_G = 20 nm device with W_FIN = 15 nm. This device shows I_ON = 350 μA μm⁻¹ (I_OFF = 100 nA μm⁻¹ and V_DD = 0.5 V), drain-induced barrier-lowering DIBL = 30 mV/V and inverse subthreshold slopes in the linear and saturation regions, SS_LIN = 74 and SS_SAT = 78 mV/decade, respectively. The reported I_ON is among the highest for Si CMOS-compatible III–V FETs. The gate leakage (not shown) is lower than 1 × 10⁻¹⁰ A μm⁻¹. We achieve a peak transconductance value of about 1.5 mS μm⁻¹. In comparison to our previous work,²⁵⁾ based on devices featuring no spacers, we lower the off-current by approximately 3 orders of magnitude, resulting in a subthreshold slope improvement near the off-current target and thus an overall increase in I_ON. Detailed analysis of the influence of the spacers on the off-state performance²⁶⁾ as well as noise characterization²⁷⁾ was reported elsewhere. Figure 3(b) displays the output characteristic for the same device, showing healthy transistor characteristics with low output conductance. The on-resistance for this device is 300 Ω μm. Excellent performance is also achieved in ultra-scaled devices. As, shown in Fig. 3(c), we report I_ON = 300 μA μm⁻¹ (I_OFF = 100 nA μm⁻¹ and V_DD = 0.5 V) for a device with L_G = 13 nm and W_FIN = 25 nm. As displayed in the benchmarking plot [Fig. 3(d)], this value represents the highest reported on-current for ultra-scaled CMOS-compatible III–V MOSFETs integrated on silicon.^{20,25,26,28–30)}

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In Fig. 4(a), on-resistance versus gate length for InGaAs FinFETs with W_FIN = 40 nm is shown. We extrapolate an access resistance of about 220 Ω μm. To assess the effectiveness of the implemented process modules we evaluate the access resistance for samples with different spacer thickness (0 nm, 4 nm and 10 nm) with S/D extensions matching the spacer thickness, as shown in Fig. 4(b). R_access increases from 200 to 220 Ω μm, for devices without spacers to devices with 10 nm spacers, showing that a relatively low R_access can be maintained by matching spacer thickness with SD extension length. Devices with different extension lengths (8, 9 and 10 nm) at fixed spacer thickness (10 nm) are also shown in Fig. 4(c). A mismatch of 2 nm between spacer thickness and SD extension length results in a 200 Ω μm increase in R_access, (approximately 100 Ω μm per nm of mismatch) demonstrating a strong need for a highly controllable SD extension formation process.

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In summary, III–V on silicon MOSFETs are susceptible to large OFF-state leakage currents through the floating body effect and PBE. In this work we explored the use of spacers to reduce the PBE. We demonstrated high-performance InGaAs FinFETs integrated on silicon using carefully designed RSD extensions. At L_G = 13 nm we achieve an on-current of 300 μA μm⁻¹ (I_OFF = 100 nA μm⁻¹ and V_DD = 0.5 V), among the highest reported values for ultra-scaled Si CMOS-compatible III–V FETs. We showed that R_access increased by ∼100 Ω μm per nanometer of mismatch between the spacer thickness and SD extension length, as well as that relatively low R_access can be maintained with effective matching between spacers and extensions. This highlights the need for a highly controllable SD extension formation process for high-performance III–V FETs.

Acknowledgments