Investigation of degradation under arbitrary bias conditions in HfO₂ based nanosheet nFETs by 3D kinetic Monte-Carlo method

Time-dependent reliability and variability, such as bias temperature instability (BTI), hot carrier injection (HCI), threaten significantly the safe operating window and lifetime of the advanced transistors with ultra-scaled dimensions.^1–4) The devices in different application scenarios may undergo a wide range of V_g/V_d bias combinations, especially in analog circuits.^5,6) Therefore, the limited set of bias combinations in the measurements or separate simulations of BTI and HCI induced degradation might lead to an insufficient lifetime prediction for the normal operating devices.^7,8) Moreover, the quantitative contribution of interface states and bulk traps to the degradation and variability under different bias combinations are difficult to distinguish from measurements.^9,10) Multiple reliability issues co-interacting strongly with each other during circuit operation are associated with the multi-trap behaviors in the gate dielectrics.^11–17) Hence, the physics-based trap behaviors simulation is essential for comprehending degradation and tracing the corresponding variability stressed by arbitrary V_g/V_d bias combinations.

In this work, the 3D kinetic Monte-Carlo (KMC) simulator including multi-trap microscopic physical mechanisms in a unified system is developed to capture degradation and variability over the full bias space. The developed simulator is verified by experimental results under different stress modes. Utilizing the simulator, the degradation induced by multiple traps under three stress modes are compared. The mapping of threshold voltage degradation (ΔV_th) in nanosheet (NS) nFETs with HfO₂ gate dielectric is also performed. The extended works compared to the content in Ref. 18 include the detailed descriptions of the reliability modeling, the difference of the temperature dependent degradation between BTI and off-state stress (OSS), as well as the mapping of the interface state contribution to the total degradation. Furthermore, the statistical average impact of a single defect on the ΔV_th is identified from the simulation results.

Fully-coupled physical mechanisms for multiple traps are illustrated in Fig. 1. The traps simulated in this work are interface states between the channel and interfacial layer (IL) together with the bulk traps located in the IL, high-k layer (HL) and the IL/HL interface. The defect behaviors in gate dielectrics simulated by the 3D KMC method can be categorized as follows: the charge trapping/detrapping, the generation/recombination of interface/bulk traps and trap interaction. The multi-physical processes are dependent on the electrical field, carrier energy and temperature. The detailed equations used in the 3D KMC simulator are listed in Table I. The trapping and detrapping probabilities obey the nonradiative multi-phonon theory, which can be calculated as Eqs. (1)–(3).^19–21) The generation and recombination of bulk traps follow the chemical reaction model using Eqs. (4) and (5).^22,23) The breakage and passivation of Si-H bonds are regarded as the generation and recombination of interface states, which are described with the truncated harmonic oscillator model according to Eqs. (6)–(11).^24–26) The occurrence of each event is determined by the probabilities during every time step. The integrated simulation flowchart for the evaluation of degradation under arbitrary bias conditions is shown in Fig. 2. For a given device structure and the stress condition, the input of 3D-electric field, potential, carrier density and energy distribution can be obtained from the device simulator. The pre-existing oxide traps are distributed randomly in the gate dielectric on the basis of the initial defect density. Besides, the values of model parameters mainly depending on the atomic nature of defects are set in reasonable ranges according to the theoretical calculations and experimental findings.^27–30) The final output results such as threshold voltage shift and its variation are the statistics of charged traps over time. Figure 3 shows the simulation of PBTI effect under different V_g biases, exhibiting excellent agreement with experiments.³¹⁾ And the simulation of HCI degradation in HfO₂ based nFinFETs under V_g/V_d 2.0 V/2.0 V bias also fits well with measured data.³²⁾ Therefore, the simulator is capable of evaluating reliability under different degradation modes in the unified framework.

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Table I.  Modeling equations for reliability prediction over the full bias space.

Probabilities for trap behaviors in the gate dielectrics
${P}_{c}={\delta }_{nc}{v}_{n}n\exp \left(-\tfrac{{u}_{c}-\lambda {({F/F}_{0})}^{\rho }}{{k}_{B}T}\right)$	(1)
${P}_{e}={\delta }_{ne}{v}_{n}{N}_{c}\exp \left(-\tfrac{{u}_{e}+\lambda {({F/F}_{0})}^{\rho }}{{k}_{B}T}\right)$	(2)
${P}_{ij}={T}_{ij}{f}_{c}\exp \left(-\tfrac{{\varepsilon }_{ij}}{{k}_{B}T}\right)$	(3)
${P}_{g}={f}_{g}\exp \left(-\tfrac{{E}_{a}-\gamma F}{{k}_{B}T}\right)$	(4)
${P}_{r}={f}_{r}\exp \left(-\tfrac{{E}_{r}}{{k}_{B}T}\right)$	(5)
${P}_{AB,n}=\displaystyle \int f({\rm{E}})g\left({\rm{E}}\right){\sigma }_{0}{\left(E-{E}_{b}+{E}_{i}\right)}^{p}v(E)dE$	(6)
${P}_{MVE}=\displaystyle \int f({\rm{E}})g({\rm{E}}){\sigma }_{0}(E-\hslash \omega )v(E)dE$	(7)
${P}_{u}={P}_{MVE}+{f}_{e}\exp \left(-\tfrac{\hslash \omega }{{k}_{B}T}\right),{P}_{d}={P}_{MVE}+{f}_{e}$	(8)
${P}_{ig,n}={P}_{AB,n}+{f}_{e}\exp \left(-\tfrac{{E}_{b}-{E}_{i}}{{k}_{B}T}\right)$	(9)
${P}_{ig}=\displaystyle \frac{1}{k}\displaystyle \sum _{n}{P}_{ig,n}{\left(\tfrac{{P}_{u}}{{P}_{d}}\right)}^{n},k=\displaystyle \sum _{n}{\left(\tfrac{{P}_{u}}{{P}_{d}}\right)}^{n}$	(10)
${P}_{{\rm{i}}r}={f}_{e}\exp \left(-\tfrac{{E}_{ir}}{{k}_{B}T}\right)$	(11)

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The three-layer stacked NS nFET with 12 nm gate length is simulated in this work, as shown in Fig. 4. In addition, 0.4 nm thickness SiO₂ and 3.6 nm thickness HfO₂ are applied to the gate-stacks. The initial defect densities in IL, HL and the IL/channel interface are about 10¹⁸ cm⁻³, 5 × 10¹⁸ cm⁻³, and 10¹¹ cm⁻², respectively. The following investigation of reliability degradation in the NS nFET under different V_g/V_d bias combinations is carried out on 200 samples using a set of model parameters listed in Table II.

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Table II.  Model parameters used in the 3D-KMC simulation.

Para.	HL	Para.	HL	IL
Ea0	2.55 eV	uc0	0.77 eV	0.6 eV
Er0	1.1 eV	ue0	0.47  eV	0.55 eV
σEa	0.36 eV	σc	0.16 eV	0.2 eV
σEr	0.2 eV	σe	0.1 eV	0.1 eV
γ	0.85 nm	ρ	1.5	1
uc,e	N(uc0,e0, σc,e)	λ	0.05 eV	0.04 eV
Ea,r	N(Ea0,r0, σEa,Er)	F0	102 V cm−1	102 V cm−1
Interface	$\hslash$ω	p	Eb	fe
Para. value	0.075 eV	11	1.5 eV	0.1 ps−1

The time evolution of trap distributions in the gate dielectric of the NS nFET under the HCI mode is illustrated in Fig. 5. It can be seen that both charged interface states and bulk traps are involved in the degradation. Furthermore, the more charged interface states are generated than bulk traps and mostly located near the drain side due to the larger bond-dissociation probability. Figures 6(a) and 6(b) show the statistical average number of interface states and bulk traps over time under three typical degradation modes, respectively. It can be noted that the number of interface states is maximum in HCI mode (V_g/V_d 1.5 V/1.5V) while bulk traps contribute the most in the degradation induced by BTI stress (V_g/V_d 1.5V/0V). Further statistics of charged traps in Fig. 6(c) show that ΔV_th induced by HCI and OSS (V_g/V_d 0 V/1.5 V) are severer than BTI mode even though more bulk traps are generated under BTI stress. Cumulative distributions of ΔV_th after 100 s BTI, HCI and OSS are plotted in Fig. 7(a) and the variations of ΔV_th are shown in Fig. 7(b). The results indicate that the maximum ΔV_th variation appears in HCI mode, and BTI degradation exhibits the smallest ΔV_th variation. It also should be noted that the ΔV_th variability depends on the dimensional parameters of NS structure. The larger ΔV_th variation can be observed in the NS FETs with the reduced gate width or thickness of NS due to the decreased device gate area.³³⁾ Particularly, the gate oxide along the width direction plays a dominant role in the reliability of NS FETs with thin thickness because of the higher average oxide electric field and the larger trapping area.

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To comprehend the reasons behind the degradation difference under varying bias combinations, the statistical average impact of a single charged trap on the threshold voltage (η) is extracted from simulation results. The parameter η acts as an indicator of the variability and also provides the crucial link between statistical modeling and measurements in the deeply scaled technologies.³⁴⁾ It can be observed in Fig. 8(a) that the peak value of η reaches 4.5 mV under the most serious HCI case (i.e. V_g = V_d = 1.5 V) followed by the OSS mode, whereas η for the BTI mode remains below ∼1.0 mV. A clear increase of η can be seen in the zone where V_d is above ∼0.5 mV due to the increased generation of interface states. What's more, η increases slightly when V_g moves to 1.5 V for the pure BTI condition (V_d = 0 V). The mapping of the interface state contribution also can be obtained from the 3D KMC simulations, as shown in Fig. 8(b). Here, the ratio of interface state induced degradation to the total statistical average degradation ζ_it is expressed as follows

$$\begin{eqnarray*}&&{\zeta }_{{\rm{it}}}=\displaystyle \frac{{\rm{\Delta }}{V}_{{\rm{it}}}}{{\rm{\Delta }}{V}_{{\rm{th}}}}=\displaystyle \frac{{\rm{\Delta }}{V}_{{\rm{it}}}}{{\rm{\Delta }}{V}_{{\rm{it}}}+{\rm{\Delta }}{V}_{{\rm{ot}}}},\end{eqnarray*}$$

where ΔV_it and ΔV_ot are two components in the ΔV_th induced by interface states and bulk traps, respectively. It can be found that the mean contribution of charged interface states to the total ΔV_th is up to ∼83% and occurs at V_g = V_d = 1.5 V condition. However, ζ_it is under 20% for the regimes of weak V_d and pure BTI due to the more bulk traps generated away from the channel/IL interface. Also indicated in Fig. 8, the ζ_it map shows that the bias condition of the peak is identical to that of η over the full bias space, and the trend of ζ_it is similar to η above the pinch-off region (V_g − V_th = V_d). Thus, the charged trap locations have the dominant effect on η. Moreover, the larger η indicates that the majority of charged traps are generated near the channel/IL interface. The mappings of ΔV_th of NS nFETs after 100 s stress under different temperatures are presented in Figs. 9(a) and 9(b), respectively. The simulated results show that the highest ΔV_th is induced by HCI stress for both the temperatures of 300 and 398 K because of the dominant interface state contribution. The worst-case degradations in the ΔV_th mappings are equal to 22 mV and 142 mV, respectively. However, high temperature leads to a visible degradation increase under BTI stress compared to that for OSS mode, indicating that ΔV_th caused by BTI is severer than that induced by OSS mode at 398 K. The phenomena can be attributed to the different temperature dependence of degradation mechanisms and respective trap components.

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The 3D KMC simulator featuring a unified system of multi-trap behaviors in the gate dielectrics is developed for investigating reliability and variability of the device under arbitrary bias conditions. The reliability degradation together with variation in the three-layer stacked NS nFETs are simulated. The time evolution and respective contribution of stress-induced interface states and bulk traps under three typical degradation modes are presented. Moreover, the mapping of statistical average degradation and the single defect impact on the ΔV_th are shown. The results indicate that ΔV_th and its variation induced by HCI are serious than BTI and OSS due to the fact that the interface states play a dominant role.

This work is supported by National High-tech R&D Program (863Program) 2015AA016501 and NSFC 61674008, 61421005.