High mobility (>30 cm² V⁻¹ s⁻¹) and low source/drain parasitic resistance In–Zn–O BEOL transistor with ultralow <10−20 A μm⁻¹ off-state leakage current

Figure 3 shows the mobility characteristics of the fabricated InZnO FET and InGaZnO FET with an EOT of 39 nm. Each mobility was extracted by the split C−V method using FETs with an L/W of 100 μm/100 μm, where L, W is the channel length and the channel width, respectively. As shown in Fig. 3(a), the mobility of the InZnO FET was 33 cm² V⁻¹ s⁻¹ at the surface carrier concentration (N_s) of 10¹³ cm⁻², which is about twice as high as that of a typical InGaZnO FET. Figure 3(b) shows the indium (In) composition ratio dependence of the mobility of the InGaZnO FET at an N_s of 8 × 10¹² cm⁻². An increase of the In composition ratio is effective to improve the mobility of the InGaZnO FET.^25,26) It was found that compared at the same In composition ratio of 0.56, the InZnO FET showed a higher mobility than the InGaZnO FET. This suggests that Ga acts as a carrier scattering source in InGaZnO.^26,27)

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Next, in order to compare S/D parasitic resistance between the InZnO FET and InGaZnO FET, we performed an R_on−L plot with FETs of different channel lengths. Figure 4(a) shows the R_on−L plot with the gate overdrive voltages from 4 V to 16 V. The value of parasitic resistance at each gate overdrive voltage was estimated from the vertical intersection point in the R_on−L plot. As shown in Fig. 4(a), the S/D parasitic resistance decreased as the gate voltage increased. This gate voltage dependence of parasitic resistance can be explained by the potential modulation of the oxide semiconductor at the S/D contact by the gate voltage due to the gate−S/D overlapped structure.²⁸⁾ As illustrated in Fig. 4(b), the Schottky barrier becomes narrower as the gate voltage increases, which results in the increase of tunneling in addition to thermionic field emission. Figure 5 shows a comparison of gate overdrive voltage dependence of S/D parasitic resistance between the InZnO FET and InGaZnO FET. It was found that the S/D parasitic resistance of the InZnO FET was reduced to 3.6 kΩ μm at a gate overdrive voltage of 16 V, which was about 75% smaller than that of the InGaZnO FET.

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In order to investigate the origin of the S/D parasitic resistance reduction by the InZnO FET, the Schottky barrier height (SBH) was extracted. Assuming that the S/D parasitic resistance at the small gate overdrive voltage is mainly dominated by thermionic field emission at the S/D contact as shown in Fig. 4(b), we fitted the S/D parasitic resistance behavior at the small gate overdrive voltage region (V_g−V_th < 1 V) with the following extended equation of the thermionic emission model:²⁹⁾

$$\begin{eqnarray}&&{R}_{{\rm{p}}{\rm{a}}{\rm{r}}{\rm{a}}}=\displaystyle \frac{k}{qA\ast T}\exp \left(-\displaystyle \frac{q\left({\varnothing }_{{\rm{B}}}-\alpha {V}_{{\rm{g}}}\right)}{kT}\right)\end{eqnarray} \tag{ 3 }$$

where q, k, T and ϕ_B are the electronic charge, Boltzmann's constant, temperature and SBH, respectively. We introduced the gate bias voltage modulation factor α in this model in order to represent the gate voltage dependence of the S/D parasitic resistance by thermionic field emission and used ∼0.1 as α and 41 A cm⁻² K⁻² as Richardson's constant (A^*).³⁰⁾ As shown in Fig. 6, the SBH of the InZnO FET was estimated to be 0.37 eV, while that of the InGaZnO FET was 0.46 eV. The SBH of InZnO was found to be smaller by 0.09 eV than that of InGaZnO. This indicates that the reduction of S/D parasitic resistance by the InZnO channel results from a lowering of the conduction band minimum (E_c).

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Since the InZnO FET achieved a lower parasitic resistance in addition to a higher mobility than the InGaZnO FET, as shown in Fig. 3 and Fig. 5, the InZnO FET can be expected to show a higher I_on by proper channel length scaling. Figure 7 shows the I_on improvement with channel length scaling. The solid circles and squares are experimental data, and the dashed lines were calculated from each extracted mobility and parasitic resistance using Eqs. (1) and (2). The InZnO FET can be expected to have an I_on three times higher at the channel length of 10 nm than the InGaZnO FET.

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Figure 8(a) shows a cross-sectional TEM image of the fabricated InZnO FET with thin EOT. The EOT was estimated to be 6.2 nm by C−V measurement as shown in Fig. 8(b). Figure 8(c) shows typical I_d−V_g and I_g−V_g characteristics of the InZnO FET with an EOT of 6.2 nm and L/W of 1 μm/1.4 μm. The InZnO FET showed normally-off characteristics and off-state gate leakage current was not observed in the conventional DC measurement since the detection limit was about 0.1 pA.

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Figure 9(a) shows a comparison of I_g−V_g characteristics in the on-state between the InZnO FET and InGaZnO FET with an L/W of 10 μm/4.4 μm. Compared with the InGaZnO FET, the I_g−V_g curve of the InZnO FET shifted positively by 0.2 V and the on-state gate leakage current was found to be suppressed by the InZnO channel. Figure 9(b) shows a Fowler−Nordheim plot of the obtained data. The on-state gate leakage current characteristics were confirmed to agree well with the Fowler−Nordheim tunneling model. This indicates that the on-state gate leakage current in the InZnO FET and InGaZnO FET with an EOT of 6.2 nm is dominated by the tunneling electron injection from the conduction band of the oxide semiconductor channel to the conduction band of the SiO₂ gate insulator. The conduction band offset between the oxide semiconductor channel and the SiO₂ gate insulator was estimated using the following equations of Fowler−Nordheim tunneling current (J_FN):³¹⁾

$$\begin{eqnarray}&&{J}_{{\rm{F}}{\rm{N}}}=A\displaystyle \frac{{{E}_{{\rm{o}}{\rm{x}}}}^{2}}{{\varnothing }_{{\rm{o}}{\rm{x}}}}\exp \left(-\displaystyle \frac{B{{\varnothing }_{{\rm{o}}{\rm{x}}}}^{3/2}}{{E}_{{\rm{o}}{\rm{x}}}}\right)\end{eqnarray} \tag{ 4 }$$

$$\begin{eqnarray}&&B=\displaystyle \frac{4\sqrt{2{m}^{* }q}}{3h}\end{eqnarray} \tag{ 5 }$$

where A, E_ox, ϕ_ox, m^*, q and h are a constant, the oxide electric field, the band offset, the effective mass, the electronic charge and Plank's constant, respectively. Assuming that the effective mass (m^*) is 0.34,³²⁾ the conduction band offsets between the oxide semiconductor channel and the SiO₂ gate insulator were estimated to be 1.58 eV and 1.45 eV for the InZnO/SiO₂ and InGaZnO/SiO₂ interface by using the following equation, respectively. The conduction band offset of InZnO/SiO₂ was found to be 0.13 eV larger than that of InGaZnO/SiO₂.

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Figure 10 shows a comparison of the extracted band diagram of InGaZnO and InZnO. Here, the bandgap energy was estimated using reflection electron energy loss spectroscopy. As shown in Fig. 5 and Fig. 9, the InZnO FET showed a reduction of S/D parasitic resistance and suppression of on-state gate leakage current. The difference of the extracted SBH values of InZnO and InGaZnO at the S/D contact was 0.1 eV, which is consistent with the difference in the extracted band offset values between the oxide semiconductor channel and SiO₂ gate insulator. These results suggest that the advantages of the reduction of parasitic resistance and on-state gate leakage current in InZnO both originated from a lowering of E_c by the InZnO channel compared with the InGaZnO channel.

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Figure 11 shows an evaluation method of ultralow off-state leakage current characteristics.³³⁾ As shown in Fig. 11(a), we fabricated a simple circuit with the device under test (DUT), a source follower amplifier and a capacitor. The DUT and the amplifier FET of the source follower consisted of InZnO FET or InGaZnO FET, and a capacitor was monolithically fabricated on Si substrate, while an external constant current source was used as a load in the source follower amplifier. A thick SiO₂ film with a thickness of 150 nm was used as an interlayer in the capacitor so that leakage current through the capacitor was negligible. Figure 11(b) shows a timing chart for evaluating the ultralow off-state leakage current characteristics. After a signal voltage (V_sig) of 1.2 V was written to the capacitor (drain of DUT), the gate voltage of DUT (V_gate) was changed to be low-level (V_g) and then V_sig was changed to be 0 V so that the potential difference between the S/D electrodes of the DUT occurred. The time dependence of the source follower amplifier's output voltage (V_detect) was monitored and the time dependence of the floating node voltage (V_FN) could be estimated by using the input−output characteristics of the source follower amplifier. Assuming that the voltage drop of the floating node is caused by leakage current via the DUT, the off-state leakage current (I_leak) can be estimated by using the following equation:

$$\begin{eqnarray}&&{I}_{{\rm{l}}{\rm{e}}{\rm{a}}{\rm{k}}}={C}_{{\rm{F}}{\rm{N}}}\times {\rm{\Delta }}{V}_{{\rm{F}}{\rm{N}}}\,/{\rm{\Delta }}t\,\end{eqnarray} \tag{ 6 }$$

where the capacitance (C_FN) of the floating node was 20 fF and each measurement time was 1000 s. This measurement was repeated with different V_g values in the off-state to obtain a gate voltage dependence of the ultralow off-state leakage current.

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Figure 12(a) shows the time dependences of V_FN at V_g from 0 to −0.4 V. V_FN at each time was calculated from the measured V_detect by using the input−output characteristics of the source follower amplifier measured in advance. In this region, it was observed that the falling speed of V_FN decreased as V_g was set more negatively, and V_FN no longer decreased at V_g of −0.4 V. Moreover, as shown in the time dependences of V_FN at V_g of 0 V and −0.2 V in Fig. 12(a), V_FN dropped to 0 V at constant speed. This means that the magnitude of the leakage current observed in this region does not depend on the potential difference between the source and drain of the DUT. Since the subthreshold leakage current of FETs is determined by electron diffusion with thermal energy, not by the potential difference between the source and drain, the constant leakage current observed in Fig. 12(a) is consistent with the characteristics of the subthreshold leakage current. Figure 12(b) shows the transfer characteristics with the extracted leakage current values using Eq. (6). The extracted ultralow off-state leakage current values showed almost the same trend as the subthreshold characteristics obtained by conventional DC measurements. It was also confirmed that the subthreshold characteristics were maintained below 10⁻²⁰ A μm⁻¹, which is a detection limit of this method.

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Figure 13(a) shows the time dependences of V_FN at V_g less than −2 V. In this region, as V_g decreases negatively, V_FN drops dramatically. Unlike the constant leakage current observed in Fig. 12(a), the leakage current showed time dependence and the time derivatives were decreased as the drain voltage of the DUT was reduced due to the leakage current from the floating node. This behavior of V_FN dropping is consistent with the characteristics of gate leakage current between the drain and gate of the DUT. Figure 13(b) shows the transfer characteristics with the extracted leakage current values. Since the gate leakage current was reduced as the drain voltage of the DUT was decreased, the initial time derivative of V_FN was used to estimate a leakage current value at each gate voltage. It was confirmed that gate leakage current over 10⁻²⁰ A μm⁻¹ was not observed in the range of ∣V_g∣ < 1.5 V even at a thin EOT of 6.2 nm.

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Finally we compared ultralow off-state leakage current characteristics between InZnO FET and InGaZnO FET extracted from the above evaluation method (Fig. 14). Ultralow off-state leakage current values of the InZnO FET and InGaZnO FET agreed well with the trends of the subthreshold characteristics of the InZnO FET and InGaZnO FET by conventional DC measurements, respectively. The subthreshold slope (S.S.) values maintained below 10⁻²⁰ A μm⁻¹ were 66 mV dec⁻¹ and 74 mV dec⁻¹ for the InZnO FET and InGaZnO FET, respectively. It was found that off-state gate leakage current characteristics were comparable between the InZnO and InGaZnO FET. The InZnO FET with an EOT of 6.2 nm exhibited ultralow off-state leakage current characteristics (<10⁻²⁰ A μm⁻¹) as well as the InGaZnO FET in the range of ∣V_g∣ < 1.5 V.

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