Imaginary impedance due to hopping phenomena and evaluation of dopant ionization time in cryogenic metal-oxide-semiconductor devices on highly doped substrate

MOS capacitors fabricated on substrates with doping concentrations as high as 1018 cm−3 were characterized at 4.2 K. The highly doped substrate exhibited an intrinsic imaginary component of impedance at 4.2 K. The imaginary component is attributed to the time delay induced by hopping phenomena, leading to a decrease in the gate capacitance. Furthermore, we investigated the time constant associated with dopant ionization under depletion conditions and determined it to be 0.35 μs. An equivalent circuit model of the highly doped substrate at 4.2 K is also shown.

ryogenic CMOS (cryo-CMOS) devices play a crucial role in integrated electronics for quantum computers. 1,2)While three-dimensional transistors are often favored for cryogenic applications 3,4) such as logic circuits and analog-to-digital converters (ADC), bulk-scaled cryogenic CMOS devices [5][6][7] remain significant for analog applications such as low-noise amplifiers, digital-to-analog converters (DAC), oscillators and mixers, owing to their reduced parasitic capacitance and scalable drain current to the channel width.To satisfy the necessary speeds and gains required for quantum computing applications, it is imperative to utilize scaled bulk CMOS devices at the 65 nm technology generation and beyond.In these scaled bulk CMOS devices, the doping concentration (N D ) within the well/substrate should be on the order of 10 18 cm −3 .8,9) Furthermore, to broaden the application of cryo-CMOS across various domains, a profound understanding of the cryogenic characteristics of fundamental elements in large-scale integrated circuits (LSI), such as capacitance-voltage (C-V ) characteristics and pn junction characteristics, is indispensable.
][13] However, there remains a dearth of literature on MOS capacitor characteristics, especially in cases of high N D .Although CMOS devices operating at 77 K for supercomputing applications were studied in the late 1980s, the N D levels were typically as low as 10 16 cm −3 , [14][15][16][17][18] significantly lower than those utilized in high-speed bulk-scaled CMOS devices. I fact, at N D of greater than 5 × 10 17 cm −3 , the dopant levels become shallower and wider than those of isolated dopants, 19) thereby exerting a notable influence on the characteristics of cryo-CMOS devices.Consequently, it is imperative to study and model MOS capacitors fabricated on a well/substrate with N D as high as 10 18 cm −3 at cryogenic temperatures.
This paper presents the characterization and modeling of MOS capacitors fabricated on substrates with N D ≈ 10 18 cm −3 at 4.2 K, demonstrating that at cryogenic temperatures, carrier freeze-out not only elevates the substrate resistance but also triggers the emergence of the imaginary component of impedance due to the inherent delay in response associated with the hopping phenomenon.Furthermore, a method for evaluating the delay due to dopant ionization was proposed, and the ionization delay was evaluated.These delays stemming from the highly doped substrate/well are important to accurately understand cryo-CMOS operations because they influence the transient characteristics of transistors, such as the overshoot of drain current, 20) and affect the timing of substrate-bias-induced threshold voltage modulation schemes, which find extensive application in bulk CMOS circuits.
A 6-inch antimony-doped CZ (Czochralski) n-type Si (100) substrate with a resistivity of 0.01-0.02Ω•cm was thermally oxidized in a dry oxygen atmosphere to form a SiO 2 gate oxide layer.Al was then deposited and patterned on the SiO 2 surface as a gate electrode.Then, Cr and Au were deposited as backside electrodes after removing the backside SiO 2 .The substrate was annealed at 450 °C under a forming gas atmosphere.The gate area was 60 μm × 70 μm.The capacitance versus voltage (C-V ) characteristics were measured using a Keysight LCR meter E4980A in the double sweep mode, where MOS capacitors were first biased in strong accumulation.The Lakeshore CPX probe station was used for low-temperature characterization.
First, the MOS capacitance was measured in parallel mode (C m ) as a function of the gate voltage (V g ) at RT, and the characteristics are shown in Fig. 1(a).The gate oxide thickness and the substrate doping concentration were determined to be 30.7 nm and 2.0 × 10 18 cm −3 , respectively.At 300 K, the C m -V g curves in Fig. 1(a) show no frequency dispersion, whereas at 4.2 K the C m -V g curves in Fig. 1(b) show strong frequency dispersion.
The decrease in cryogenic C m at higher frequencies, as shown in Fig. 1(b), is considered to result from the high substrate resistance due to dopant freeze-out.Thus, the substrate resistance (R s ) was obtained in strong accumulation with V g = 15 V by where G m is the measured conductance and ω is the angular frequency for the C-V measurements. 21)The dip around V g = 0 V corresponds to the flat-band voltage observed at cryogenic temperatures. 22,23)Using the equivalent circuit as shown in Fig. 1(c), the gate capacitance corrected with R s (C _ Rs g corr ) was obtained, and its V g dependence is plotted in Fig. 1(d).In spite of the R s correction, C _ Rs g corr still decreases at the highest frequency of 100 kHz even in the accumulation.Since interface states do not generate frequency dispersion in the accumulation, the C _ Rs g corr decrease is likely due to capacitance originating from the substrate, meaning that the equivalent circuit of a substrate cannot be expressed by simple resistance but must be expressed by impedance, including complex components.
To extract the substrate impedance Z s (ω), the MOS capacitor was biased in a strong accumulation with V g = 15 V as shown in Fig. 2(a), and Z s (ω) was obtained by subtracting the oxide capacitance C ox from the measured accumulation impedance Z acc (ω) as The gate capacitance with Z s (ω) correction C _ Z g corr s was obtained using the equivalent circuit shown in Fig. 2(b).Figure 2 , demonstrating no frequency dispersion in accumulation.The decrease of capacitance in depletion at the highest frequency of 100 kHz is discussed later.To investigate the factors determining Z s , the Nyquist plot of Z s is shown in Fig. 2(d), illustrating the contribution of the two phenomena with different time constants (τ).The experimental data were fitted with the equivalent circuit model shown in Fig. 2(e), demonstrating that the longer τ phenomenon is represented by the resistance R 0 and imaginary impedance ( ( ) ) w j T 1 0.82 0 , where j is the imaginary unit and T 0 is the proportional constant in units of F•s −0.18 .The imaginary impedance is similar to that of a constant-phase element (CPE) whose impedance is proportional to ( ) w - j p , where 0 < p < 1. CPE is widely used in the field of electrochemistry.A standard capacitance whose impedance is proportional to ( ) w - j 1 cannot reproduce experimental longer-τ data.Other fitting parameters in Fig. 2(e) are R 1 , R c , and C c .R c and C c correspond to the shorter-τ phenomenon.
Here, we discuss the origin of the longer τ phenomenon first.Pollak et al. studied the impedance of heavily doped ntype Si at low temperature 24) and found that when the carrier transport is dominated by hopping phenomena, the conductivity should have an AC term proportional to ω 0.8 , which is independent of doping concentrations.][26][27][28] In the cryo-MOS capacitor, the conductance of the longer-τ phenomenon can be expressed by 051001-2 © 2024 The Author(s).Equation (3) shows that the conductance of the longer τ phenomenon has an AC term proportional to ω 0.82 , which is consistent with the conductivity behavior owing to hopping transport (∝ω 0.8 ), 24) which strongly suggests that the longer τ phenomenon is due to hopping transport through an impurity band.At 10 K, the decrease of gate capacitance in accumulation cannot be observed even at 100 kHz, meaning that the decrease of the gate capacitance in accumulation shows strong temperature dependence and can be observed only at cryogenic temperature.This observation is consistent with the model that the decrease in gate capacitance is due to hopping phenomenon, which can be observed only at cryogenic temperatures.Figure 2(f) shows the equivalent circuit transformed from that in Fig. 2(e), where R dc , C ac , and T ac are expressed as Here, G 0 ≡ 1/R 0 .The derivation is provided in supplementary information.R dc is the low-frequency-limit resistance contributed by ( 1) electrons emitted from the dopants to the conduction band and (2) DC electron transport via hopping phenomena.R ac and ( ) w j T 0.82 ac correspond to frequencydependent AC conductance contributed by the polarization caused by hopping processes. 24)he shorter time constant τ observed is attributed to the Schottky contact formed on the backside of the substrate.Note that this contact exhibited Ohmic behavior at 300 K; however, at 4.2 K, it transitions to a Schottky contact owing to significantly suppressed thermionic and thermionic-field emissions.The time constant τ of the Schottky contact is modeled by considering the contact resistance R c and capacitance C c , which are estimated to yield a value of 0.35 μs from the Nyquist plot.The extracted C c of 0.22 nF agrees with the numerically estimated value of 0.25 nF (see supplementary information).
So far, we have discussed the substrate impedance extracted under the accumulation condition.To understand the cryogenic C-V curves, we also need to discuss C-V characteristics in depletion.Figure 2(c) shows that under the depletion and around the flat-band conditions, C _ Z g corr s decreases at the highest frequency of 100 kHz.We consider that this decrease results from a delay owing to the ionization of the freeze-out dopants.The delay of dopant ionization τ i is modeled by the ionization resistance R i and capacitance C i , as shown in Fig. 3(a).Using the equivalent circuit shown in Fig. 3(a), the frequency-dependent depletion layer capacitance, C d (ω) normalized by its static value C d0 is obtained as where τ dep ≡ R i (C i + C d0 ) and A ≡ C d0 /(C i + C d0 ).Furthremore, experimental C d (ω) were obtained by the equation: . The symbols in Fig. 3(b) shows experimental C d (ω)/C d0 as a function of frequency for various gate voltages.By fitting experimental data to Eq. ( 4) as indicated by the dashed lines in Fig. 3(b), τ dep and A were obtained.From τ dep and A, we can obtain τ i using the equation: τ i = (1 − A)τ dep .Figure 3(c) shows the time constant of the dopant ionization, illustrating that τ i is almost independent of the gate voltage and is approximately 0.35 μs.This time constant is comparable to that observed in bulk 65 nm MOSFETs with a similar substrate doping concentration, 20) demonstrating the validity of the present extraction method for ionization time of freeze-out dopants.As ionization occurs at the edge of the depletion layer as shown in Fig. 3(d), where electric field is very weak, it is reasonable that the ionization time does not depend on the gate voltage.
Finally, we should mention the dielectric relaxation time τ DR given by ρε, where ρ and ε are the resistivity and dielectric constant of the substrate, respectively.τ DR is modeled by the dielectric relaxation resistance R DR and capacitance C DR between the electrodes.In MOS devices with N D as high as 10 15 cm −3 at 77 K, τ originating from the well is dominated by τ DR , 29,30) because of the extremely high substrate resistivity.Whereas, in this study, R DR is 6.4 kΩ and C DR , which is the capacitance between backside electrode and depletion edge (or accumulation layer) is roughly calculated to be 8.6 fF, leading to τ DR of 54 ps.Therefore, τ DR is unimportant for C-V evaluation in present highly doped case.However, this may need to be considered for high-speed applications.
Figure 4 shows the equivalent circuit of cryogenic MOS capacitor, which includes the delay in dopant ionization, delay in hopping phenomena, and non-ohmic metal-semiconductor contact.
In this study, MOS capacitors fabricated on n-type substrate with dopant concentrations as high as 10 18 cm −3 were characterized at 4.2 K.The substrate has an imaginary component of impedance proportional to ( ) w - j 0.8 , owing to the hopping phenomenon.The DC conductance of the substrate is considered to consist of carrier transport in the conduction and impurity bands.Owing to the freeze-out of dopants, an Ohmic contact at 300 K becomes a Schottky 051001-3 © 2024 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd contact at 4.2 K, depending on the dopant concentrations.The hopping phenomenon is the main cause of the reduction in the accumulation-mode gate capacitance after subtracting the substrate resistance.We developed a method to characterize the dopant ionization time.The time constant of the dopant ionization was in the order of sub-μs.An equivalent circuit of MOS capacitors at temperatures is provided, which will be useful for designing bulk CMOS circuits with substrate biasing and to reproduce the transient characteristics of MOS devices.051001-4 © 2024 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd

Fig. 1 .Fig. 2 .
Fig. 1.Capacitance measured in parallel mode (C m ) versus gate voltage (V g ) characteristics of n-type MOS capacitors with doping concentration of 2.0 × 10 18 cm −3 at 300 K (a) and 4.2 K (b).(c) Equivalent circuit including substrate resistance R s .(d) Gate capacitance with R s correction (C _ R g corr s) as a function of V g .

Fig. 3 .
Fig. 3. (a) Equivalent circuit model for dopant ionization analysis in depletion.(b) Depletion capacitance C d (ω) normalized by its static value C d0 as a function of frequency at various gate voltages.(c) Dopant ionization time τ i as a function of gate voltage.(d) Schematic showing the ionization of freeze-out dopants.

Fig. 4 .
Fig. 4. Equivalent circuit of capacitor fabricated on heavily doped substrate at cryogenic temperatures.The equivalent circuit of the substrate impedance Z s (ω) shown within the red dashed line, consists of three parts: DC component contributed by the conduction band and impurity band transport, the AC component contributed by the polarization by hopping processes, and the Schottky contact.