Fabrication of free-standing GaN substrates using electrochemically formed porous separation layers

We have developed a pore-assisted separation (PAS) method for the fabrication of free-standing GaN substrates, where bulk GaN crystals were separated from seed GaN templates at electrochemically formed porous layers. The pore size was controlled by the electrochemical process conditions and must be greater than 100 nm to realize separation within whole wafers. A 2 inch free-standing GaN substrate having a low dislocation density of ∼2.7 × 106 cm−2 was realized by growth of an 800 μm thick GaN layer on the porous GaN template. A 3 inch free-standing GaN substrate was also fabricated by the PAS method, indicating its good scalability.

We have developed a pore-assisted separation (PAS) method for the fabrication of free-standing GaN substrates, where bulk GaN crystals were separated from seed GaN templates at electrochemically formed porous layers.The pore size was controlled by the electrochemical process conditions and must be greater than 100 nm to realize separation within whole wafers.A 2 inch free-standing GaN substrate having a low dislocation density of ∼2.7 × 10 6 cm −2 was realized by growth of an 800 μm thick GaN layer on the porous GaN template.A 3 inch free-standing GaN substrate was also fabricated by the PAS method, indicating its good scalability.© 2024 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd I mproving the power conversion efficiency of electric devices is one of the key challenges for solving global warming problems.][6][7] To fabricate the free-standing GaN substrates, various methods based on hydride vapor phase epitaxy (HVPE), [8][9][10][11] an ammonothermal method [12][13][14] and a Na-flux method 15,16) have been developed.Our group has also developed an HVPE-based void-assisted separation (VAS) method for fabricating free-standing GaN substrates, [8][9][10] where we separated a thick HVPE-grown GaN crystal from a seed GaN template at the void formed on its surface. Becaus the growth rate of HVPE is extremely high (>100 μm h −1 ) and the VAS process is highly stable, the productivity of the VAS process is superior to that of other methods.These benefits have also enabled the growth of GaN ingots as long as 6 mm, 10) leading to the realization of high-quality GaN substrates with a low dislocation density in the order of 10 5 cm −2 or less. As a rsult, the VAS-based 2 and 4 inch GaN substrates are commercially available and have been widely used in optical and electrical device applications.However, if the GaN substrate size is further scaled beyond 4 inches (100 mm) using the VAS method, process nonuniformities of void formation might become severe.The ease with which GaN bulk crystal is separated from the voided template depends on the size and density of the voids as well as the growth conditions of bulk GaN crystals.8) The voids were formed by annealing a Ti-coated GaN template at ∼1000 °C, and its annealing conditions were found to determine the size and density of the voids. 8) Beuse the realization of a uniform temperature distribution at such high temperatures would become difficult with increasing wafer size, fabricating uniform voids across a wafer having a diameter greater than 100 mm by annealing would be inherently difficult.The realization of growth conditions of a growth temperature, gas partial pressure and gas flow rate for large bulk GaN crystals that are sufficiently uniform to enable complete separation within a whole wafer might also be challenging.In addition to such a technical difficulty, the VAS method has another drawback in that it requires a hightemperature process twice, which can reduce the throughput of the total process and increase the fabrication cost.
From these viewpoints, an alternative separation method for GaN substrates that does not involve a high-temperature process for void formation is preferable.][19][20][21][22][23][24][25][26] In fact, researchers have successfully fabricated a free-standing GaN substrate by growing a thick GaN crystal on a GaN template having electrochemically formed pillars or holes on its top surface. 17,18,21)In these methods, complete filling of the pillar and hole structures is difficult even by growth of a thick GaN layer due to their high aspect ratios.Residual voids at the bulk/template interface enable separation of the bulk crystals from the templates.However, because the size and density of residual voids should depend on the growth conditions of the bulk GaN, the application of these methods to the fabrication of a large-sized wafer might also encounter difficulties of growth uniformity and wafer separation.With an electrochemical process, the formation of embedded pores inside a GaN crystal without the aid of regrowth is also possible, as reported in the literature, [22][23][24] where a GaN/ porous GaN distributed Bragg reflector having a flat surface was realized. Athough the pores reported in these previous studies are too small (several tens of nanometers) to survive during long-term GaN bulk regrowth at ∼1000 °C, the electrochemical process appears to be suitable for the costeffective fabrication of large free-standing GaN substrates because the embedded porous structure having a flat surface is formed before thick bulk GaN growth without a hightemperature process.
In the present study, we developed a pore-assisted separation (PAS) method for the fabrication of free-standing GaN substrates.The pores were formed by an electrochemical process inside the n + -GaN layers on a sapphire substrate so that the original flat GaN surface was maintained.Control of the pore size for pores larger than 100 nm is possible under electrochemical conditions.On this "porous GaN template," thick GaN layers were grown by HVPE.When the pore size was greater than 100 nm, thick GaN crystals were successfully separated from the GaN templates.The resultant 800 μm thick 2 inch GaN free-standing substrate exhibited a low dislocation density of 2.7 × 10 6 cm −2 .The fabrication of a 3 inch free-standing GaN substrate was also demonstrated.
The process flow of the PAS method is schematically illustrated in Fig. 1.GaN templates on sapphire substrates were first prepared either by metal−organic vapor phase epitaxy (MOVPE) or HVPE.The GaN templates comprised, from bottom to top, an undoped base GaN layer, an n + to-beetched layer, and an n − cover layer.The thickness and the carrier concentration of the undoped base GaN layers were approximately 1 μm or thicker and approximately in the lower half of the 10 18 cm −3 range or lower.The n + to-beetched layers were approximately 1-3 μm and approximately in the upper half of the 10 18 cm −3 range or higher.The n − cover layers were approximately 100-200 nm and approximately in the lower half of the 10 18 cm −3 range or lower.Subsequently, porous GaN templates were prepared by porosification of the GaN templates using an electrochemical etching process.Pores were then formed only within the n + -layer by an electrochemical process conducted at room temperature, where the GaN template and a Pt electrode were connected as positive and negative electrodes, respectively, and a voltage between 10 and 20 V was applied between them.The positive electrode was directly connected to then − cover layer of the GaN template.An oxalic acid solution was used as an electrolyte.Next, thick GaN layers were regrown on the porous GaN templates.On these porous GaN templates, 200 and 800 μm thick GaN bulk crystals were grown by the HVPE method at atmospheric pressure and at ∼1000 °C.Finally, the GaN layers were separated from the sapphire substrates by stress that could be applied during cooling after the HVPE growth caused by the difference in the thermal expansion coefficients of GaN and sapphire, and GaN substrates were completed.The surface morphology of the porous GaN templates was investigated using atomic force microscopy (AFM), and the pore size was evaluated by cross-sectional scanning electron microscopy (SEM).The dislocation densities of bulk GaN crystals were evaluated by cathodoluminescence (CL) measurements conducted at room temperature.
Figure 2 shows photographs of 2 inch GaN templates (a) before and (b) after porosification at 20 V. Figures 2(c) and 2(d) show the surface AFM images in a scan area of 5 × 5 μm 2 of another GaN template and a porous GaN template porosified at 20 V.Although the as-grown GaN template before porosification showed a mirror-like surface with high transparency [Fig.2(a)], the porous GaN template appeared translucent, with the mirror surface kept as it was [Fig.2(b)], indicating the successful formation of a porous structure inside the GaN layer.A gray circle observed near the orientation flat of the porous template was the contact area of the positive electrode, where porosification did not occur.This part was porosified by an additional electrochemical etching process, and a whole wafer can be separated.As evident in the AFM images, the present porosification process had little effect on the surface morphology.The rms values of the surface roughness were 0.36 and 0.45 nm for the original template and the porous template, respectively.An atomically flat surface was confirmed in the porous GaN templates.
Cross-sectional SEM images of porous GaN templates prepared at various voltages using MOVPE and HVPE GaN templates are shown in Figs.3(a)-3(e).Figures 3(a)-3(c) correspond to porous GaN templates porosified at 10, 15 and 20 V using MOVPE GaN templates, and Figs.3(d) and 3(e) correspond to porous GaN templates porosified at 15 and 20 V using HVPE GaN templates.These figures clearly show that pores were successfully formed inside the GaN crystals while the original flat surface was maintained.There was no significant difference in MOVPE and HVPE GaN templates for fabrication of the porous GaN templates.The formation of pores only inside the crystals without etching of the top n − -layer is noteworthy.This phenomenon can be explained as follows.Etching of GaN crystals occurred only when they were oxidized by hole injection through Zener and/or avalanche breakdown. 25,26)If the applied voltage is insufficient to induce breakdown for the n − -layer itself but sufficiently high to induce breakdown for dislocation cores, only dislocation cores will be etched and will form pipes that connect the surface to the n + -layer. 23)After the electrolyte reaches the n + -layer through the etched dislocation core, Zener and/or avalanche breakdown occurs in the n + -layer and pores are formed in it.The size (height and width) of pores formed at high voltages is greater than that of pores formed at low voltages irrespective of the growth method of the GaN template.The height and width values were typically estimated from the largest pores except the extraordinarily large ones.The uniformity of the pore size was confirmed both in the center and in the edge of the wafer by SEM observation.In addition, uniformity of white color of the porous GaN template shown in Fig. 2(b) also indicates that the pores were formed with good uniformity in the whole wafer.The dependence on the applied voltage in other GaN templates is also plotted in Figs.3(f) and 3(g).The definitions  of the pore height and width are depicted as insets in the figures.Here, pore formation started at a certain threshold voltage of 5-6 V. Above this threshold voltage, the height and width increased almost linearly with increasing applied voltage.Although the pore height and width were ∼50 nm when the applied voltage was 10 V, they both exceeded 100 nm when the applied voltage was greater than 15 V.These phenomena were commonly observed in porous GaN templates formed from MOVPE and HVPE GaN templates, and there was no significant difference in the electrochemical etching process.Thick GaN layers were regrown on the porous GaN templates and were separated from the sapphire substrates.Figure 4(a) shows a photograph of an 800 μm thick GaN substrate separated from a porous GaN template having large (>100 nm) pores.Growth on the large porous structure having pores larger than 100 nm resulted in full separation of GaN bulk crystals from the underlying GaN on sapphire, where the sapphire substrate was completely removed.In contrast, the porous GaN template with small-sized pores resulted in the porous GaN template breaking as well as the sapphire substrate and without separation of the GaN layer.Gray regions in Fig. 4(a) correspond to regions with residual melted Ga on the backside.At this initial stage of development, we were not concerned with suppressing attachment of the GaN wafer to the wafer tray during deposition of the thick GaN layer.Attachment of some parts of the GaN layer to the reactor compartment can generate stress in the substrate, which can lead to crack formation on the surface of the GaN crystal. 27)However, success in nearly full-area separation of a GaN crystal from the GaN template indicated that the PAS method is promising for fabricating large free-standing GaN substrates.The threading dislocation density (TDD) was observed using CL for the free-standing GaN substrates fabricated by the PAS method.As shown in Figs.4(b) and 4(c), free-standing GaN substrates having thicknesses of 200 and 800 μm exhibited TDDs of ∼1.4 × 10 7 cm −2 and ∼2.7 × 10 6 cm −2 , respectively.The relationship between the HVPE-grown GaN layer thickness and the TDD values of the free-standing GaN substrates prepared by the PAS method is summarized in Fig. 4(d), together with the relationship for substrates prepared by the conventional VAS method. 10)As evident in Fig. 4(d), reduction of the TDD in the PAS method decreased in inverse proportion to the GaN layer thickness.This tendency is the same as that observed for the VAS method 8,10) and is well described by the standard theory of TDD reduction. 28)o evaluate the scalability of the PAS method to larger wafers, we applied the PAS method to a 3 inch GaN template.As a result, a nearly 3 inch free-standing GaN  substrates prepared by the PAS method, together with the corresponding relationship for the conventional VAS method. 10)Closed circles and open squares represent data for the free-standing GaN substrates fabricated by the PAS method and those fabricated by the VAS method, respectively.

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© 2024 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd substrate was obtained as shown in Fig. 5, although cracks caused by crystal fixing at irregular portions remained.We were not concerned about suppressing the attachments, and the cracks can be suppressed by improvement of the wafer tray designed to prevent attachments.
In conclusion, the PAS method has been developed for fabricating free-standing GaN substrates.Pores were formed electrochemically inside the GaN layer of a GaN template without a high-temperature annealing process.An adequate pore size is critical for separating the GaN substrate, and it can be controlled via manipulation of the electrochemical etching conditions.When the pores were larger than 100 nm, waferscale separation became possible.The fabricated free-standing GaN substrate exhibited good crystal quality, with a TDD value of ∼2.7 × 10 6 cm −2 .The scalability of the PAS method was confirmed for wafers as large as 3 inches.Therefore, we expect that the proposed method will open a path to realizing larger free-standing GaN substrates with good productivity.

Fig. 1 . 2 ©
Fig. 1.Process flow of the PAS method: (a) GaN template, (b) porosification of the GaN template by electrochemical etching at room temperature, (c) regrowth of a thick GaN layer on the porous GaN templates by HVPE and (d) separation of a free-standing GaN substrate from the porous GaN template during cooling after HVPE growth.055502-2

Fig. 4 .
Fig. 4. (a) Photograph of an 800 μm thick GaN layer grown on a porous GaN template.Plan-view CL images of (b) 200 and (c) 800 μm thick GaN grown on porous GaN templates prepared at 20 V. (d) Relationship between the HVPE-grown GaN layer thickness and the TDD values for the free-standing GaNsubstrates prepared by the PAS method, together with the corresponding relationship for the conventional VAS method.10)Closed circles and open squares represent data for the free-standing GaN substrates fabricated by the PAS method and those fabricated by the VAS method, respectively.