Density functional theory study on effect of NO annealing for SiC(0001) surface with atomic-scale steps

Density functional theory calculations for the electronic structures of the 4H-SiC(0001)/SiO$_2$ interface with atomic-scale steps are carried out to investigate the effect of NO annealing. The characteristic behavior of the conduction band edge states of SiC is strongly affected over a wide area of the interface by the Coulomb interaction of the O atoms in the SiO$_2$ region as well as the step structure of the interface, resulting in the discontinuity of the inversion layers at the step edges under the gate bias. The spatially discontinued band only allows the very limited conduction paths in the inversion layer, leading to the significantly decreased mobile carrier density. It is found that the Coulomb interaction of the O atoms is screened and the inversion layers become continuous when the nitrided layers are inserted at the interface by NO annealing. This result is in good agreement with experimental findings that the improvement of the performance of SiC metal-oxide-semiconductor field-effect-transistors by NO annealing is attributed to an increase in the mobile electron density rather than an increase in the mobility of electrons in the inversion layer.

SiC is a technologically important material for future power electronic devices with high breakdown field, high carrier velocity, and thermally oxidized SiO 2 layers, making it ideal for metaloxide-semiconductor field-effect transistors (MOSFETs).2][3][4] However, the high channel resistance of SiC-MOSFETs limits their performance. 5,6This high resistance is expected to be attributed to the low field-effect mobility in SiC-MOSFETs, which is much lower than the ideal electron mobility (∼ 1000 cm 2 V −1 s −1 ). 72][13] Hatakeyama et al. reported that the Hall mobility is not increased by NO annealing; on the other hand, the mobile carrier density increases and the increase in field-effect mobility is due to the increase in mobile carrier density. 14It is also reported that the inserted N atoms become a source of interface defects 15 and/or cause negative bias instability. 16Although a lot of efforts have been made thus far, the microscopic information of such an increase in field-effect mobility is not fully clear.
The behavior of the conduction band edge (CBE) states of a SiC bulk is similar to that of free electrons, which are the so-called "floating states," 17 and sensitive to the local atomic structure at the interface. 18In practical devices, off-oriented 4H-SiC(0001) surfaces by 4 degree are widely used and thus intrinsically possesses atomic-scale step and terrace structures even for the atomically flat surfaces. 19Furthermore, it has been reported that thermal oxidation causes atomic-scale roughness even on the oriented 4H-SiC(0001) surfaces, 20 suggesting that atomic steps also exist on the terrace at the SiO 2 /SiC interface.Atomic-scale steps affect the behaviors of the electrons of the floating states as well as the electronic structures of the interface over a wide area of the interface.In this paper, we compare the local densities of states (LDOSs) of the SiC(0001)/SiO 2 interface with steps before and after NO annealing using first-principles calculations based on the density functional theory (DFT). 21It is found that the CBE states are affected by the Coulomb interaction of the O atoms in the SiO 2 region, which results in the discontinuity of the inversion layers at the step edge under the gate bias.The discontinuities of the inversion layers markedly prevent the carriers from conducting from the source to the drain.After annealing, the inserted nitrided layers screen the Coulomb interaction and the density of the spatial discontinuities of the inversion layer decreases.These results suggest that the nitrided layers inserted by NO annealing make the inversion layers continuous by screening the Coulomb interaction of the O atoms in the SiO 2 regions so that the penetration of carriers is enhanced.
We perform the first-principles calculation for the electronic structures of 4H-SiC(0001)/SiO 2 interfaces with steps before and after NO annealing.As an example, we show the computational models where the trench structure models are employed to imitate the step model as shown in Fig. 1.Since most of SiO 2 in the SiC(0001)/SiO 2 interface is amorphous as shown by a scanning transmission electron microscopy (STEM) image, 22 it is not straightforward to characterize the interface atomic structure.Here, we assume the atomic structures that can exist locally at the SiC(0001)/SiO 2 interface and employ the interface atomic structures proposed in our previous study on the basis of STEM images. 22Our model contains a crystalline substrate with seven SiC bilayers (17.5 Å thick) connected without any coordination defects to a crystalline SiO 2 region with a thickness of 8.2 Å for the upper terrace.In a 4H-SiC bulk, SiC bilayers are stacked on the quasi-cubic (k) and hexagonal (h) sites alternatively along the [0001] direction.For the SiO 2 side, the computational models where the 4H-SiC(0001) bilayer faces the one-hold or three-hold structure of SiO 2 are proposed in our previous study. 22The interface model, where the atoms in the k site of the 4H-SiC(0001) bilayer face the one-hold SiO 2 structure, is referred to as the k1 model.The other interface models are also similarly named the k3, h1, and h3 models.
For the interfaces with steps, when the upper terrace of the 4H-SiC(0001) bilayer is at the h site, the lower terrace is always at the k site.In addition, when the SiO 2 layer at the upper terrace has the three-hold structure, that at the lower terrace has the one-hold structure.The dangling bonds at the step edges are removed by replacing C atoms with N atoms.The interface model with steps, in which the k1 and h3 interfaces are the upper and lower terraces, respectively, is named the k1/h3 model.The other interface models with steps are similarly referred to the k3/h1, h1/k3, and h3/k1 models.
The RSPACE code, [23][24][25] which uses the real-space finite-difference approach 26,27 for the DFT, 21 is employed.The periodic boundary condition is imposed on all the directions.The supercell size for the interface with steps is 5.33 × 36.96× 40.44 Å 3 and a vacuum gap of 14.1 Å thickness separates the slabs.The back side is flattened at the atomic level and the dangling bonds at the top surface of the SiO 2 layer and the bottom surface of the SiC substrate are terminated by H atoms.
Integration over the Brillouin zone is performed using a 6 × 1 × 1 k-point grid including Γ point.
The grid spacing in real space is taken to be 0.18 × 0.19 × 0.18 Å 3 .The exchange-correlation functional is treated within the local density approximation. 28The projector-augmented wave method 29 is adopted to describe the electron-ion interaction.We implement structural optimization until all  The LDOS is calculated as where ǫ i,k is the eigenvalue of the wavefunction Ψ i,k with indexes i and k denoting the eigenstate and the k-point, respectively, z is the coordinate of the plane where the LDOS is plotted, and is the normalization factor with α as the smearing factor and N k as the number of k-points in the Brillouin zone.Here, α is set to 16.4 eV −2 .
Table I shows the topmost interfacial SiC bilayer where the CBE states appear.As reported in our previous papers, 18,22 the CBE states are absent at the topmost SiC bilayer when the first interfacial SiC bilayer of 4H-SiC(0001)/SiO 2 is the k site.On the other hand, when the first Step (before annealing) k1/h3 2 k3/h1 4 h1/k3 3 h3/k1 3 Step (after annealing) k1/h3 4 k3/h1 4 h1/k3 5 h3/k1 5 interfacial bilayer is the h site, the CBE states are absent at the first and second interfacial bilayers in the h1 model, whereas they lie at the first interfacial bilayer in the h3 model. 18Matsushita et al. reported that the behavior of the electrons in the CBE states is similar to that of free electrons, which are called the floating states.4H-SiC bulks consist of tetrahedrons surrounded by Si atoms and those by C atoms.The electrostatic potential in the Si tetrahedrons is lower than that in the C tetrahedrons because of the difference in electron negativity between the Si and C atoms.The Si and C tetrahedrons spatially overlap at the k site, whereas they are separated at the h site, resulting in the formation of the floating states in the Si tetrahedrons at the h site. 17Since O atoms bridge the Si atoms of the first interfacial bilayer in the h1 model, the electron negativity of the O atoms increases the Coulomb potential at the first interfacial bilayer, resulting in the increase in the energy of the floating states. 22The CBE states do not appear at the second interfacial bilayer because the second interfacial bilayer is the k site in the h1 model; the topmost SiC bilayer where the CBE states appear is the third bilayer.
We show in Fig. 1 the computational models for the interface with steps.Since the atomic structures of the k and h sites appear the same when they are seen from the [1 100] direction, only the k1/h3 and k3/h1 models are illustrated.Figure 2 shows the LDOS of the upper terrace of  I.In the k1/h3 (h1/k3) model [Fig.2(a) (Fig. 2(c))], the topmost interfacial SiC bilayer at the upper terrace is the same as that in the k1 (h1) model.Interestingly, the CBE states are absent at the second and third (the first) interfacial SiC bilayers in the k3/h1 (h3/k1) model [Fig.2(b) (Fig. 2(d))], whereas they appear at the flat interface.Owing to the finite size effect along the direction parallel to the interface at the step edge, the energy of the floating states increases and the states do not lie at the CBE.
The SiO 2 /SiC(0001) structure is usually fabricated on an off-oriented substrate by 4 degrees and the atomic-scale single steps of the SiC substrate at the interface are observed by STEM.When the gate bias is applied, inversion layers are formed by the CBE states at the interface.Since SiO 2 at thermally oxide SiC-MOS is usually amorphous, one-hold and three-hold structures coexist at a terrace and several types of step appear at the interface.The inversion layers formed by the CBE states are not continuous at the step edges in the h1/k3 model.The electrons trapped at the discontinuous inversion layers are immobile, as shown in Fig. 4(a), resulting in the low mobile carrier density at the interface. 13In addition, since the behavior of the CBE states is sensitively affected by the interface atomic structure, the Hall mobility of SiC-MOS is low. 30Therefore, the channel resistance, which is the inverse of the product of the Hall mobility and the mobile carrier density, increases.Next, the electronic structure of the interface with steps after NO annealing is investigated.
The computational models for the interfaces with steps after NO annealing are shown in Fig. 3 which four C atoms adjacent to a Si vacancy are replaced by N atoms.The structures have been proposed in our previous paper, 31 and the areal N atom density of 1.2 × 10 −15 atoms/cm 2 corresponds to that observed in experiments. 32,33We have also reported that the insertion of the nitrided layers is an exothermic reaction and the nitrided layers are preferentially formed immidiately below the SiO 2 region. 34We plot in Fig. 5  tical MOS interface.It is intuitive that the density of these discontinuities is low in the oriented (0001) interfaces.Thus, the investigation of oriented (0001) interfaces without NO annealing is in progress.
We have investigated the effect of NO annealing on the electronic structures of the 4H-SiC(0001)/SiO 2 interfaces with steps by the DFT calculations.In the experiments, the mobile carrier density of SiC-MOSs is increased by NO annealing, whereas the increase in Hall mobility is negligible.Our results indicate that the CBE states are absent below the upper terrace in some models before NO annealing owing to the finite-size effect and the Coulomb interaction of the O atom in the SiO 2 region, resulting in the discontinuities of the inversion layers under the gate bias.
The discontinuities seriously prevent the carriers from penetrating along the channel direction and decrease the mobile carrier density.On the other hand, when the nitrided layers are inserted between the SiC substrate and the SiO 2 region by NO annealing, the Coulomb interaction of the O atom is screened and the density of discontinuities in the inversion layers are reduced.Since the spatial deviation of the behavior of the CBE states due to the disorder of the atomic structure at the interface cannot be eliminated completely, the Hall mobility remains low.However, the channel resistance, which is the inverse of the product of the Hall mobility and the mobile carrier density, is reduced.Since the density of the atomic-scale steps, which is the source of the discontinuities of the inversion layers, is low in the oriented (0001) interfaces, these results will also aid future work in determining the channel resistance of SiC-MOSFETs using the oriented (0001) substrates without NO annealing.

AUTHORS' CONTRIBUTIONS
M.U. and N.F.contributed equally to this work.
the force components decrease to below 0.05 eV/Å, whereas the atomic coordinates of the SiC bilayer in the bottom layer and the H atoms terminating C dangling bonds are fixed during the structural optimization.

FIG. 2 .
FIG. 2. LDOSs of interface with steps before annealing for (a) k1/h3, (b) k3/h1, (c) h1/k3, and (d) h3/k1 models.For clarity, structural models are provided on the top of each distribution.Zero energy is chosen as the Fermi level.Each contour represents twice or half the density of the adjacent contours, and the lowest contour is 6.94 × 10 −4 electrons/spin/eV/Å.LDOSs in the shaded area in Fig. 1 are calculated.Atomic structures are illustrated as a visual aid and the numbers written on the right-hand-side of the atomic structures are the indices of the atomic layers counted from the upper terrace.

FIG. 4 .
FIG. 4. Schematic of electron conduction at interfaces (a) before and (b) after annealing.The gray shaded areas indicate the inversion layers.The red and pink areas are the spatial distributions of the floating states below and above the Fermi level, respectively.

FIG. 5 .
FIG. 5. LDOSs of interface with steps after annealing for (a) k1/h3, (b) k3/h1, (c) h1/k3, and (d) h3/k1 models.Zero energy is chosen as the Fermi level.Each contour represents twice or half the density of the adjacent contours, and the lowest contour is 6.94 × 10 −4 electrons/spin/eV/Å.LDOSs in the shaded area in Fig. 3 are calculated.The meanings of the other symbols are the same as those in Fig. 2.

TABLE I .
Position of topmost interfacial SiC bilayer where CBE states lie.