Separate evaluation of interface and oxide hole traps in SiO2/GaN MOS structures with below- and above-gap light excitation

Understanding the traps in metal-oxide-semiconductor (MOS) structures is crucial in the fabrication of MOS transistors with high performance and reliability. In this study, we evaluated the hole traps in SiO2/GaN MOS structures through photo-assisted capacitance-voltage measurements. Below- and above-gap light was used to distinguish between the contributions of fast interface and slow oxide hole traps. While annealing in oxygen is effective in reducing the oxide hole traps, a high density of hole traps exceeding 1012 cm−2eV−1 remains at the interface. Although these traps are donor-type and thus hidden in n-type MOS structures, they could impair the switching performance of GaN MOS transistors.


G
][6][7] HEMTs exhibit extremely high mobility due to the high density of two-dimensional electron gas induced at the AlGaN/GaN heterointerface by spontaneous and piezoelectric polarization without doping.Despite superior on-state performance of AlGaN/GaN HEMTs, their normally-on nature presents a vital challenge in achieving fail-safe operation with low power consumption.10][11] In MOS devices, the selection of dielectrics is particularly important so as to prevent gate leakage current and ensure good gate controllability.Among the dielectrics investigated so far in GaN MOS devices, e.g.silicon dioxide (SiO 2 ), [12][13][14][15] aluminum oxide (Al 2 O 3 ), [16][17][18] and aluminum silicate (AlSiO), 19,20) SiO 2 is the most reliable due to its wide bandgap and extremely high thermal stability.In previous studies, interface engineering has been conducted to obtain high-quality SiO 2 /GaN MOS interfaces.While electron traps in the SiO 2 /GaN structure can be reduced to 10 10 cm −2 eV −1 by forming a GaO x layer at the interface, 14,15,21) hole traps still remain an issue.Although the hole traps might originate from the formation of the GaO x layer, 22) this model is still under debate. These ole traps could impair the switching performance and threshold voltage stability of MOS devices and thus have to be eliminated. While ow hole trap density has recently been demonstrated for SiO 2 /GaN samples with very high magnesium doping concentration (10 18 -10 19 cm −3 ), 22,23) the mechanism of defect passivation remains unclear.To gain better control over the hole traps in SiO 2 /GaN structures, having insight into their origin is crucial.For this purpose, detailed experiments to clarify their location, density, and energy levels are necessary.
An effective method to evaluate deep traps in MOS structures is the photo-assisted capacitance-voltage (C-V ) method.By relying on light excitation, one may detect traps with extremely long emission time constants in the absence of light.][26] An earlier study indicated that a low average interface state density (D it ) of 7 × 10 10 cm −2 eV −1 can be achieved within the entire bandgap of GaN through postmetallization annealing (PMA) of Al 2 O 3 /GaN structures at 800 °C in nitrogen (N 2 ) gas. 24) However, at this temperature condition, grain boundaries form in the Al 2 O 3 layer due to its partial crystallization, leading to a high gate leakage current. 17)With a reduced PMA temperature of 300 °C, D it values as low as 7 × 10 10 cm −2 eV −1 were successfully achieved for energies less than 1.2 eV from the conduction band edge (E C ), while higher D it values of (2-4) ×10 12 cm −2 eV −1 were detected near the valence band edge (E V ). 25)Despite these important findings in Al 2 O 3 /GaN structures, reports on SiO 2 /GaN structures remain limited.To gain insight into the hole traps in SiO 2 /GaN systems, systematic photo-assisted C-V measurements should be conducted on a set of samples processed under various conditions.In this study, we evaluated the hole traps in SiO 2 /GaN structures using photo-assisted C-V measurements.In particular, we used below-and above-gap light to separately evaluate the contributions of fast interface and slow oxide traps.We also discuss the possible impact of these traps on the performance/reliability of GaN MOSFETs.
The flow of sample preparation and measurements is shown in Fig. 1.We used n-type GaN epilayers (donor density: 2 × 10 16 cm −3 ) grown on freestanding GaN(0001) substrates.After wet cleaning the samples with acetone and 50%-hydrofluoric acid, a field SiO 2 layer with a thickness of about 1.2 μm was deposited using plasma-enhanced chemical vapor deposition (PECVD) in a tetraethyl orthosilicate (TEOS) and oxygen (O 2 ) gas mixture.The substrate temperature during the deposition process was 400 °C.Then, the field SiO 2 was patterned by lithography and hydrofluoric acid (HF) etching.After that, a SiO 2 gate dielectric layer with a thickness of about 50 nm was deposited, using either PECVD or sputtering of a SiO 2 target in pure argon gas.While an interfacial GaO x layer with a thickness of a few nm is ultimately formed during the PECVD deposition of SiO 2 , 21) only a few monolayers of GaO x are formed for sputter deposition. 27)Subsequently, post-deposition annealing (PDA) in O 2 was performed within the temperature range of 400 °C-800 °C.After that, an indium tin oxide (ITO) gate electrode was deposited via sputtering and patterned through lithography and etching using a mixed acid.Aluminum (Al) back contacts were then formed through vacuum evaporation to fabricate the GaN MOS capacitors, and finally PMA in N 2 was conducted at 300 °C.Hereafter, the samples are labeled on the basis of the combination of the deposition method and PDA condition; e.g.PECVD-O 2 800 and Sputter-O 2 400.As the light source for the photo-assisted C-V measurements, we used a xenon lamp (MAX-303, Asahi Spectra) with a 340-890-nm bandpass filter.The bandwidth of the bandpass filters were about 10 nm, enabling monochromic light illumination.The light was directly illuminated onto the SiO 2 /GaN interface through the transparent ITO electrode as described in the schematic picture shown in Fig. 1.
We start with the fast trap evaluation using below-gap light illumination (hν < 3.39 eV). Figure 2(a) describes the measurement flow.First, C-V characteristics within a voltage range of −20 -+10 V were acquired two times in the dark.Next, after a voltage sweep from accumulation to depletion, a below-gap light was illuminated onto the MOS interface for a specified duration, whilst keeping the depletion bias to excite the electrons from the ingap states to the conduction band.Here, the excited electrons would promptly vacate the interface due to the depletion bias, without recombining with the holes left at the traps.This enables us to evaluate the contribution of deep ingap states, which normally have extremely long emission time constants in the dark.The bias hold time was set to 5 s longer than the illumination time, and the light is switched on and off during the bias hold.After that, the voltage was swept back from depletion to accumulation.The rate of forward and reverse voltage sweeps was about 0.5 Vs −1 .This measurement procedure was repeated several times changing the conditions to evaluate the hole traps.Figure 2(b) shows the typical measurement results for sample PECVD-O 2 800, with a fixed illumination time of 5 s.First, the characteristic obtained in the dark (second sweep) showed minimal hysteresis, as well as a small flatband voltage shift with respective to the ideal position.This result suggests that the density of interface defects is low.This is likely to be due to the formation of the GaO x layer at the MOS interface during the PECVD deposition of SiO 2 and the post annealing treatment.In contrast, a bump in the characteristic is clearly observed after the light illumination, which thereby increases the C-V hysteresis.The hysteresis gets even larger as the energy of the light source increases, which is due to the excitation of electrons from deeper interface states.Note that the bump is observed exclusively in the forward (depletion to accumulation) characteristic and not in the reverse (accumulation to depletion) one.The reverse characteristics overlap each other quite well independent of light illumination, and their

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© 2023 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd flatband positions are close to ideal as mentioned earlier.This suggests that the traps causing the bump/hysteresis after below-gap light illumination are related to donor-type interface defects with fast recombination.In this manner, it is possible to detect the fast interface hole traps using belowgap light excitation.
We then aimed to estimate the density and energy levels of deep traps.For this purpose, it was necessary to determine an illumination time long enough to excite the trapped electrons at a given photon energy.Figure 3(a) shows the hysteresis of sample PECVD-O 2 800 as a function of illumination time.When the photon energy was 1.72 eV or less, the amount of hysteresis saturated after an illumination time of 2 h.In contrast, when the photon energy was increased to 1.88 eV, the saturation behavior was not observed even within an illumination time of 3 h.Therefore, in this study, we evaluated the trap distribution by illuminating the light within the energy range of 1.39-1.72eV for 2 h.From the wellconverged hysteresis values obtained under these conditions, we derived the energy distribution of D it using the following formula: 25,28) where C ox , ΔV hν1 (ΔV hν2 ), and e are the oxide capacitance per unit area, the hysteresis value obtained with illumination of light with an energy of hν 1 (hν 2 ), and the elementary charge, respectively.Here, the trap energy level with respective to the valence band edge (E − E V ) was estimated by where E G is the bandgap of GaN (= 3.39 eV).According to a previous study, the GaO x interlayer is minimized to a few monolayers by sputter deposition of SiO 2 , and its growth is suppressed up to an O 2 -PDA temperature of 600 °C. 27)While the suppression of the GaO x layer is clearly effective in preventing the positive fixed charge generation caused by annealing in a forming gas ambient, 27,29,30) we now clarify that a high density of hole traps still remains at the MOS interface [Fig.3(b)].Although these hole traps are normally hidden in n-type MOS structures because of negligible hole concentrations, they are likely to impair the switching performance of GaN MOSFETs and thus need to be reduced.
We then evaluate the slow traps using above-gap light (hν = 3.65 eV). Figure 4(a) describes the measurement flow.After acquiring the C-V characteristics two times in the dark, the above-gap light was illuminated while applying a negative gate voltage stress corresponding to an oxide field of −4 MVcm −1 .This above-gap light penetrates the ITO electrode and generates electron-hole pairs directly at the MOS interface, and the generated holes are injected into the oxide in accordance with the strong negative bias.This time, the above-gap light was illuminated for slightly longer than the bias hold time to clearly define the hole injection stress time.The stress was applied for 1-1000 s, and C-V characteristics were repeatedly measured afterward to observe the hole injection behavior.The voltage sweep rate was again about 0.5 Vs −1 .Note that once the stress voltage was determined from the initial characteristic, we kept the stress voltage constant, rather than the stress oxide field, for the rest of the measurements.Next, we estimated the density of oxide traps on the basis of the drift in the flatband voltage due to the stress.Figure 5 shows the estimated trap charge density as a function of stress time for samples PECVD-O 2 800, Sputter-O 2 400, Sputter-O 2 600, and Sputter-O 2 800.In the sputter-deposited sample with a low O 2 -PDA temperature (400 °C), a charge injection into the oxide occurred even with a very short stress time (∼1 s).However, the charge injection was clearly suppressed when the PDA temperature was increased, which indicates a reduction in the oxide hole trap density.In particular, after O 2 -PDA at 800 °C, improved characteristics were obtained regardless of deposition methods (PECVD/sputter).In the PECVD-deposited SiO 2 film, extrinsic defects involving carbon atoms may be present, likely due to the usage of TEOS gas.As for the sputter-deposited SiO 2 film, a high density of oxygen vacancies may be present.O 2 -PDA is effective in eliminating these oxide traps and in improving the threshold stability and long-term reliability of MOS devices.
As can be seen in the aforementioned results, we would like to emphasize the importance of distinguishing between the fast and slow traps in GaN MOS structures.These traps have completely different natures and have different impacts on device performance/reliability.The fast hole traps are donor-like and are in the neutral charge state when the Fermi level is located above the trap level.Thus, to visualize these traps using n-type MOS structures, one should rely on light excitation.However, caution must be taken because the trapped holes immediately recombine as soon as free electrons are induced at the MOS interface [Fig.2(b)].Recombination might occur even when one simply switches off the gate bias when the flatband position is near 0 V.This is why we illuminated light while applying depletion bias and swept the voltage from depletion to accumulation to detect these traps.Although the traps are not observable in n-type MOS structures, this does not mean that they do not have an impact on the n-channel MOSFETs.In the off-state of inversion-type n-channel MOSFETs, holes exist at the MOS interface and would be captured into these traps.Nevertheless, as soon as the device is turned on, the traps are immediately neutralized because trapped holes recombine with electrons accumulated at the MOS channel.In this sense, they should have a limited impact on threshold voltage stability.However, they could impair the AC switching performance of MOSFETs because the traps would contribute as parasitic capacitance when switching the on/off states at a high frequency.In contrast, the slow hole traps have different impacts.Incidentally, relatively high-stress conditions are needed to fill these traps with holes.However, once the holes are captured in these traps, they do not easily recombine with the electrons accumulated at the MOS interface [Fig.4(b)].Therefore, they have a direct effect on the threshold voltage of the MOSFETs.It is important to distinguish the fast/slow traps and find a solution to simultaneously reduce these traps.
In summary, we separately evaluate the contributions of fast and slow hole traps in SiO 2 /GaN MOS structures using below-and above-gap light illumination.We found that a high density of interface hole traps exist regardless of the deposition methods of SiO 2 (PECVD/sputter) and the temperature conditions of O 2 -PDA.While these traps are donortype and thus are normally hidden in n-type MOS structures, they are likely to impair the switching performance of GaN MOSFETs and thus should be eliminated.In contrast, the slow oxide traps can be suppressed by conducting O 2 -PDA at high-temperature conditions (800 °C).Thus, PDA is effective in improving the threshold stability and long-term reliability of GaN MOSFETs.

Fig. 2 .
Fig. 2. (a) Flow of below-gap photo-assisted C-V measurements to evaluate the fast interface hole traps.(b) Exemplary C-V characteristics of a GaN MOS structure (sample: PECVD-O 2 800).The probe frequency was 1 MHz.
Figure 3(b) shows the evaluated D it distributions of the samples PECVD-O 2 800, Sputter-O 2 400, Sputter-O 2 600, and Sputter-O 2 800.Note that each plot in the figure represents the averaged value acquired from three pads/capacitors.Error bars represent standard deviation from the average.As a result, D it values increased toward the valence band edge regardless of the sample conditions.A high density of D it exceeding 10 12 cm −2 eV −1 was detected at about E − E V = 1.75 eV for all the samples; the sample Sputter-O 2 400 exhibited particularly high D it values.

Figure 4 (Fig. 3 . 3 ©
Fig. 3. (a) C-V hysteresis after below-gap light illumination (1.39-1.88eV) as a function of illumination time for a GaN MOS structure (sample: PECVD-O 2 800).The hysteresis values obtained without light illumination are also shown as plots at 0 h.(b) D it distributions of GaN MOS structures evaluated by below-gap photo-assisted C-V measurements.The averaged results of three pads/capacitors are shown.Error bars represent standard deviation from the average.011003-3

Fig. 4 .
Fig. 4. (a) Flow of above-gap photo-assisted C-V measurements to evaluate the slow oxide hole traps.(b) Exemplary C-V characteristics of a GaN MOS structure (sample: PECVD-O 2 800).The probe frequency was 1 MHz.Enlarged view is also shown in the inset.

Fig. 5 . 4 ©
Fig. 5. Density of injected holes in the oxide in GaN MOS structures as a function of stress time.011003-4