Demonstration of avalanche capability in 800 V vertical GaN-on-silicon diodes

High-quality pseudo-vertical p–n diodes using a GaN-on-silicon heterostructure are reported. An optimized fabrication process including a beveled deep mesa as edge termination and reduced ohmic contact resistances enabled high on-state current density and low on-resistance. A uniform breakdown voltage was observed at 830 V. The positive temperature dependence of the breakdown voltage clearly indicates the avalanche capability, reflecting both the high material and processing quality of the vertical p–n diodes. The Baliga figure of merit, around 2 GW cm−2, which is favorably comparable to the state-of-the-art, combined with avalanche capability paves the way for fully vertical GaN-on-Silicon power devices.

][3][4][5] In addition to its physical properties that exceed the limitations of silicon, GaN technology is cost-effective when grown on silicon (Si).While lateral GaN HEMTs have demonstrated high performances up to 900 V voltage operation, several challenges still plague the widespread use of this technology, including: (1) Electron trapping caused by complex hetero-epitaxy and surface states.(2) Destructive breakdown (in contrast to avalanche), resulting from the peak electric field at the vicinity of the gate terminal.(3) Relatively large device size due to the substantial gateto-drain distance required to increase the breakdown voltage.On the other hand, vertical GaN architectures offer the potential to overcome these limitations. 6,7)[10][11][12][13][14][15][16] The device breakdown voltage scales with the drift layer thickness, allowing small device dimensions.[19][20] Nevertheless, for widespread market adoption, a cost-effective substrate such as silicon would be preferred.][23][24][25][26][27] However, the avalanche breakdown capability has not yet been proved, even though it is a crucial feature required for power electronic devices.Indeed, avalanche capability ensures a non-destructive behavior close to the breakdown region and thus enhances the device robustness, and reliability of the overall system.Sidewall parasitic leakage current through the mesa, high dislocation density within the GaN drift layer, and point defects are some of the issues that lead to destructive and non-uniform breakdown, which is a significant barrier to achieving avalanche capability in GaN-on-silicon based power devices. 7)n this letter, pseudo-vertical GaN-on Si p-n diodes with a drift layer thickness of 4.5 μm, are discussed.Uniform breakdown with avalanche capability around 800 V, and low on-resistance (R on ) is achieved, reflecting the high material quality.
The heterostructure was grown by metalorganic CVD on 6 inch silicon substrate.A schematic cross-sectional diagram of a vertical GaN-on-Si p-n diode is shown in Fig. 1(a).The growth process began with a proprietary buffer layer stack, followed by a 800 nm thick n+ GaN Si-doped layer (5 × 10 18 cm −3 ), a 4.5 μm thick n-type (Si-doped) drift layer (3 × 10 16 cm −3 ) and a 700 nm thick p-type GaN Mg-doped layer (5 × 10 19 cm −3 with 3 × 10 17 cm −3 hole concentration).Capacitance-voltage (C-V ) measurements were performed on the diodes in order to confirm the net ionized doping concentration in the drift region, which was found to be ∼9 × 10 15 cm −3 .Additionally, SIMS analysis was carried out with identical growth conditions to verify the epitaxial doping of the various species [Fig.1(b)].The fabrication process started with the deposition of thick SiO 2 layer by plasma-enhanced CVD, which is patterned by reactive-ion etching plasma.This layer serves as a hard mask for the mesa etching.To reach the n+ layer, deep mesa etching were performed (about 5.2 μm) using an optimized Cl 2 /Ar based inductively coupled plasma recipe.The developed recipe reduced the sidewall leakage current and produced a beveled etching for edge termination. 28)The angle appears in Fig. 2, which was obtained with a focused ion beam by etching a vertical cross section using platinum metal as etching mask (white region in Fig. 2).The angle of the sidewalls was estimated to be around 75°.The resulting angle is used to spread the electric field at the edge of the device over a distance that is larger than the drift region thickness.This technique results in a gradient of the electrostatic potential and thus helps to manage the electric field around the anode electrode.The n+ layer was then contacted with the deposition and patterning of Ti/Al/Ni/Au metal stack by evaporation using a standard lift-off process.Subsequently, a Pd/Ni/Au stack was deposited using evaporation on top of the p-GaN layer.Both n-type and p-type contacts were optimized to achieve low ohmic contact resistances using 500 °C annealing for 10 min.The corresponding contact resistances are around 5 × 10 −6 Ω.cm 2 and 10 −4 Ω.cm 2 for n-type and p-type contacts, respectively.Forward characteristics of 30 μm anode diameter vertical diodes, with 70 μm as top mesa diameter, were evaluated using DC measurements from 0 to 20 V as a function of temperature.
The device delivered a high current density (J) with low differential on-state resistance (R on < 0.35 mΩ.cm 2 ) and a threshold voltage (V th ) of 4.5 V [Figs.3(a) and (b)].The V th value can be reduced by further optimizing the p-type ohmic contacts.The on-state resistance value was extracted ( V V J D D ( )) in the linear region at 12 V, where the slope is constant and normalized according to the anode area.Two distinct regimes can be observed: 1) between V th and 12 V, the current spreads towards the epitaxial layers and the slope of R on decreases before stabilizing.When reaching 12 V, a saturation of the forward current and a degradation of R on are observed.This is attributed to the pseudo-vertical architecture, where the current crowds at the edge of the n+ layer, limiting the current spreading under high bias due to thermal dissipation issues.From TCAD simulations [see Fig. 4(a)] using Silvaco Atlas software, the current crowding contribution can be estimated to be about 40% of R on value.Indeed, the current of the pseudo vertical structure flows vertically from the edge of the anode area towards the N+ layer where the charge transport changes direction, generating a crowding effect that degrades the specific on-resistance.This results also in a critical length of the current spreading [Fig.4(a)] above which the R on becomes dependent on the anode diameter.In turn, the size of the contact should be smaller than the critical length.This issue is specific to the pseudo-vertical architecture and does not occur in a fully vertical structure [Fig.4(b)]. 7,23)][26][27] For a more in-depth analysis of the on-state behavior of the diodes, I(V ) measurements were conducted at various temperatures [Fig.3(a)].Elevated temperatures slightly decrease V th and enhance the current spreading due to increased thermal diffusion of carriers and narrowing of the bandgap.However, in the second regime (beyond 12 V), the degradation of R on is more pronounced at high temperature [Fig.3(b)], confirming the thermal dissipation challenges associated to the pseudo-vertical design.Increasing the thickness of the n+ layer can reduce the thermal dissipation issue, but the additional resistance corresponding to the crowding effect will persist.
Typical reverse characteristics of the vertical GaN-on-Si p-n diodes are shown in Fig. 5.The diodes exhibit a high blocking capability (BV) above 800 V, resulting in a high electric field at the p-n junction of 2.3 MV cm −1 .This translates to an average electric field across the drift layer close to 2 MV cm −1 .Moreover, a uniform breakdown voltage across the sample  The Japan Society of Applied Physics by IOP Publishing Ltd was observed with similar values as a function of the anode sizes (up to 200 μm as diameter).Further improvement of the edge termination process should allow withstanding even higher critical field.Low leakage current density is observed to be below 10 −1 A cm −12 all the way to the device breakdown.This is a strong indicator of the good material quality as well as the reduction of sidewall parasitic leakage current achieved through the optimized mesa etching step.Additionally, it provides solid evidence of low electrically active dislocations within the structure (although this has not yet been assessed).Figure 5 shows the temperature dependence from RT up to 100 °C of leakage current for reverse biased p-n diodes.It can be pointed out that the diode survived many voltage sweeps up to 800 V suggesting avalanche capability.This assumption is confirmed with the temperature dependence of the reverse J-V characteristics.Under high reverse bias, charge carriers flow through a specific path with high energy, enabling the accumulation of additional charge carriers.This corresponds to the so-called impact ionization, which enables for the avalanche capability. 29,30)As the temperature increases, phonon scattering delays the onset of impact ionization.To achieve the same kinetic energy level at higher temperature, a higher voltage is thus required.Therefore, the increased breakdown voltage with increasing temperature is a strong indication of the avalanche capability in the devices.A clear avalanche breakdown signature is observed [Fig.5(b)], as the blocking voltage increases with temperature due to higher phonon scattering, which delays the onset of impact ionization.The demonstration of avalanche capability in 800 V-class p-n diodes represents a key feature that highlights the potential vertical GaN-on-silicon heterostructures for power electronics.Figure 6 illustrates the benchmark of R ON ,sp versus BV for vertical GaN-on-Si diodes.The corresponding Baliga FOM (BV 2 /R ON ) around 2 GW cm −2 is therefore favorably comparable to the state-of-the-art.
To conclude, we investigated the potential of vertical GaN-on-Si p-n diodes.With a drift thickness of 4.5 μm, the pseudo-vertical GaN-on-Si diodes exhibited high current spreading with low on-state resistance.Furthermore, we demonstrated a high blocking voltage at 800 V with avalanche   016503-3 © 2023 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd capability, resulting in a state-of-the-art BFOM of approximately 2 GW cm −2 .The demonstrated avalanche breakdown capability through temperature measurements is a strong indicator of the material and processing quality.This is attributed to an optimized deep mesa etching yielding low leakage current through the sidewalls, and low electrically active dislocations.These results pave the way for medium voltage vertical GaN-on-Si based power devices.It can be pointed out that the limitations related to the pseudo-vertical architecture in terms of current crowding effect can be overcome with the use of a fully vertical structure that can be realized by means of local substrate removal. 5)ig. 6.[23][24][25][26][27]

Fig. 3 .
Fig. 3. (a) Forward current measurements and (b) Differential on-state resistance measurements at various temperatures.

Fig. 4 .
Fig. 4. Distribution of the current density extracted from Silvaco TCAD in on-state conditions for a pseudo-vertical diode (a) and a fully vertical diode (b).

Fig. 5 .
Fig. 5. (a) Temperature dependence of pseudo vertical GaN-on-silicon p-n diode reverse characteristics (b) Zoom of the breakdown region.