Design and exploration of vertically stacked complementary tunneling field-effect transistors

The purpose of this letter is to study the design and explore vertically stacked complementary tunneling field-effect transistors (CTFETs) using CFET technology for emerging technology nodes. As a prior work, the CTFET’s device-level simulations are implemented and deliberated in strict compliance with the experimental settings. This work comprises the study of physical and DC analyses by scaling the p- to n-CTFET separation (D pn ), being a significant factor in CFET/CTFET design for its process difficulty. By utilizing the 50% benefit in footprint, the work is further extended to CTFET static random access memory implementation and characterization with hold/read noise margin analysis.


S
][3] The CFET design is most challenging because it consists of a bridge of both p-and n-type transistors together on a single plane (vertically).Hence, it is named as 3D vertically stacked CFET with single or multiple channels in the bridge of p-and n-type FETs.Researchers have identified that the CFET design has the benefit of reducing the footprint (FP) by ≈50% compared with its counterparts (conventional complementary metal oxide semiconductor (CMOS) designs). 4)Hence, this design is endorsed for sub-3 nm technology nodes and beyond (Angstrom (A 0 ) nodes). 5,6)The benefit of the FP is most advantageous for digital circuit designs, e.g.inverters, static random-access memory (SRAM), and so on.Having said that, tunneling field-effect transistors (TFETs) have shown promise for digital circuit designs due to their energyefficient performance in the low-bias operated regime (V DD ).This is with the result of its <60 mV/dec subthreshold swing (SS) operation, though there are several works on the benchmarking of TFET circuits for digital applications (e.g.inverters, SRAM, and so on), which are restricted to conventional CMOS designs. 7)In addition, TFET is a more promising choice for sub-3 nm down to A 0 nodes (as stated earlier).Therefore, the use of CFET technology for TFET design is an important consideration to design, study, and explore.
Sequential and monolithic are the two CFET technologies that have been identified and demonstrated. 8)The benefits of monolithic CFET are its cost-effectiveness and precise process control due to the low p-to n-FET separation or isolation, i.e. vertically (D pn ).Meanwhile, sequential CFET has the benefit of flexibility in design but a higher cost and process restrictions due to the large D pn .In common, it is identified that the increased D pn makes large parasitic effect (resistance (R) and capacitance (C)), thereby affecting the gain. 8)Hence, it is important to control the size of D pn for a better CFET design.In other words, the D pn reduction creates a reduction in the vertical pitch if the volume of the device is a concern (see supplementary file).Therefore, this letter will address the significance of CFET technology for TFETs as complementary TFET (CTFET) while utilizing the benefit (≈50%) in FP, followed by the study of D pn with physical, DC, and circuit (SRAM) analyses.
The proposed design of CTFET is depicted in Fig. 1 with its key specifications and material settings.Here, multibridged channels with 3-and 2-in numbers for p-(bottom) and n-CTFETs (top), respectively, are considered with Si/ SiGe semiconductor options.The parameter specifications of the proposed structure are tabulated in Table I.To model such a structure, 9) well-calibrated simulation settings meeting the experimental conditions are essential. 10,11)The simulations are calibrated using the experimental design with similar material options (Si and SiGe), and the results are depicted in Fig. 1(c).To do so, the band-to-band and trapassisted tunneling (BTBT and TAT), hydrodynamic (temperature), density gradient (quantum correction), and so on are the key models used during calibrations.The BTBT occurs along the source-channel junction, i.e.SiGe/Si, therefore the generation and recombination terms (A gen and B gen ), tunneling mass of the electron and hole (m c and m v ), and so on are used and depicted in Fig. 1(d). 9)Here, we use indirect path-dependent settings because Si and SiGe are of indirect bandgap nature.[14][15][16][17] The design of the proposed CTFET is equipped with conventional tunneling options (point-tunneling) similar to the experimental work. 10)Hence, the working principle of the CTFET is based on source (S)-channel (Ch) tunneling in both p-and n-CTFET devices as electron and hole BTBT due to the point-electric field (E).The detailed working principles of the device can be better understood from the energy band diagram of both p-and n-CTFET devices, respectively, as depicted in Fig. 2(a).Here, the carrier BTBT (electron and hole) during on-state conditions can be identified from S-Ch and vice versa for p-and n-CTFETs, respectively.The tunneling length can be identified as <5 nm to have sufficient BTBT in both p-and n-CTFETs under the specified biasing conditions.In proportion to BTBT, the drive current (I DS ) characteristics with respect to the gate bias (V GS ) are depicted in Fig. 2(b), at drain bias (V DS = |0.35|V).The use of V DS = |0.35|V is referring to sub-3 nm technology nodes with estimated power supply (V DD ) ⩽ 0.7 V 18) (circuit perspective: V DS ≈ V DD /2).The prediction of the ambipolar current (I amb ) in addition to the I DS is crucial for circuit analyses. 7)Hence, the I amb at V GS > 0 V and V GS < 0 V for p-and n-CTFETs is extracted and shown in Fig. 2(b).The magnitude of I amb is effectively controlled through reduced drain doping compared with the experimental characteristics that are seen in Fig. 1(c) (the reasons are detailed in the supplementary file).
As stated earlier, the analysis of D pn is crucial for sequential CFET/CTFET design options to reduce the parasitics. 6,8,14,19)Here, the significance of D pn is investigated with physical and DC behavior in n-and p-CTFETs at suitable biasing conditions (see Fig. 3).The D pn is scaled from 20 nm down to 5 nm, and its behavior is analyzed at both p-and n-CTFETs while they are adjacent to S-drain (D) isolation or D pn along the x-cut as depicted in Fig. 3.The two major analyses are the impact on p-while n-CTFET is ON and the impact on n-while p-CTFET is ON.Under this study, the electron and hole current density variations are displayed in Figs.3(a) and 3(b), respectively.The observations are that the adjacent p-TFET is affected in terms of the electron density when n-TFET is ON, especially at low D pn (= 5 nm).Similarly, the adjacent n-TFET is affected in terms    ) is affected marginally.The effect happening in p-is within the off-state current limits of n-CTFET and vice versa.As added evidence, the average contributions of SRH, TAT, and current density (or BTBT) at varied D pn in the entire device are extracted and depicted in Fig. 3(e).In summary, the D pn significance is marginally higher at D pn < 5 nm.Furthermore, the magnitude of I DS variation for the scaled D pn is also seen as marginal [see Fig. 3(e)].Hence, the unaltered tunneling principle for the scaled D pn of CTFET helps to advance scaling with a better off-state performance.Distinct operating conditions of CTFET are required to assess various digital circuit designs (e.g.inverter, SRAM, and so on).Hence, the I DS -V DS characteristics of both the pand n-CTFETs are extracted at distinct V GS (0 to |0.5| V), and are depicted in Fig. 4. Due to the unipolar behavior of the TFET, the conduction happens only in one direction, i.e.V DS < 0 V [see Fig. 4(a)] and V DS > 0 V [see Fig. 4(b)] in p-and n-CTFETs, respectively.This uni-directional characteristic behavior is referred to as the forward mode of operation.Under this operation, both results are identified as impressive even at very low V DS (⩽0.35 V).Meanwhile, the reverse mode of operation, i.e.V DS > 0 V [see Fig. 4(b)] and V DS < 0 V [see Fig. 4(d)] for p-and n-CTFETs, respectively, suffer from the anticipated conduction mechanism.The achieved current in reverse mode is an exponential decay (negative in magnitude) with poor saturation points.This mechanism influences applications where bi-directional conduction is needed; for example, unipolar operation of the inverter is benefited with the CTFET, whereas the sixtransistor (6T) SRAM circuit, in which n-type transistors act as access transistors (ATs) that need bi-directional conduction capability, will suffer from poor drivability of p-and n-CTFET (during reverse mode).
Use of the CTFET design is further extended to analyze the 6T-and 7T-SRAM performance, as shown in Fig. 5. Here, pull-up and pull-down networks of inverters (CTFET 1 and CTFET 2 ) conduct through uni-directional current flow, whereas the ATs (n-TFET 1 and n-TFET 2 ) require bi-directional current flow [see Fig. 5(a)].As stated earlier, the difficulties during bi-directional current flow of 6T inwardand outward-facing (IF and OF) TFETs will come into the picture, which are well addressed in the literature. 20)Here, the 6T-IF-CTFET-SRAM [Fig.5(a)] followed by the 7T-OF-CTFET-SRAM [Fig.5(d)] are demonstrated and compared.A well-defined layout demonstration is shown in Fig. 5(b), which signifies the benefited layout FP of CTFET-SRAM by 50% compared to conventional TFET-SRAM.It is worth highlighting that the cross-coupled connection is an advanced feature that can be formulated as CTFET 1 coupled to n-TFET 1 and CTFET 2 to n-TFET 2 [see Fig. 5(b)], respectively, that also benefits in achieving a 50% lower FP (4xFP compared to conventional CMOS-TFET).The procedure followed for the extraction of hold and read noise margins (NMs) is briefly stated here.To estimate the complete hold ability of SRAM, the bit lines (BL and BL bar ) are set to V DD and the word line (WL) to 0 V, by which the SRAM can deliver 145 mV of hold NM, while losing a pre-charged potential (ΔV), as indicated in Fig. 5(c).Furthermore, the read NM is measured by pre-charging the BLs to V DD and setting the WL as high (V DD ).This setting measures a read NM of ≈141 mV.We identify that the CTFET has performed better (read NM = 141 mV) than in our recent work (read NM = 78 mV), i.e. experimentally demonstrated 3D vertically stacked 6T-CFET-SRAM at similar V DD (=0.5 V). 21) In addition, the 7T-OF-CTFET-SRAM is also demonstrated and its characteristics are compared [see Figs.5(d)-5(f)].The external n-TFET is required [see Fig. 5(d)] to process both read and write lines (RBL, RWL).The 7T-SRAM's read NM is slightly improved by the external transistors, because the additional transistor has a current drivability while reading [see Fig. 5(f)].
As stated earlier, the significance of parasitic effects that arises due to the large D pn is elaborated here as future scope for the work.The contact, spreading, and source and drain extension resistances are the major parasitic resistive factors that affect the I ds -V gs performance in CTFET/CFET devices.The increase of parasitic resistance reduces the I on of the device due to its cumulative contribution from source to drain. 22)In addition, the RF performance of the circuit is adversely affected by other parasitic resistive factors originating from the multiple stacked channels, metal tracks, and so on. 5,23,24)However, the amount of metal tracks required by the CFET/CTFET technology is lower than that for conventional CMOS technology (because of the smaller area); therefore, the RF performance loss will be lower. 19)he parasitic effect is mainly due to metal interconnect layers (dependency on thickness, width, and lengths), via from the buried power rail, and the additional capacitance due to the D pn increment. 25)In addition, as a capacitive note, the magnitude of the Miller capacitance (gate-to-drain coupling capacitance from both p-and n-devices) is more beneficial than the conventional TFET because of the vertical stacking of p-and n-devices.Further investigation is needed. 26,27)In summary, the existing works identify that the parasitic RC component loss is slightly lower in CFET devices compared with that in conventional structures. 26,27)he benchmark of CTFET-with CFET-SRAM is listed in Table II, 8) in which the device type, channel, and key specifications, followed by the characteristic's behavior are listed.The benefits in FP, minimum SS (SS min ), NM, and onoff ratio (I on /I off ) are identified.It clarifies that the CTFET-SRAM has the potential to deliver an acceptable performance while considering all the process variability conditions.As a prior demonstration, CFET technology utilization for TFETs is restricted to conventional or point-tunneling rather advanced-tunneling approaches i. [28][29][30][31] In conclusion, the proposal for the design and exploration of CTFETs utilizing CFET technology for emerging technology nodes has been successfully delivered. T physical analyses and DC characteristic behavior have been discussed while highlighting the ability of CTFET under strict process conditions.The choice of the low D pn requirement for CTFET performance as one of the key parameters is studied and observed with an acceptable performance of up to D pn ≈5 nm.Furthermore, this

Fig. 1 .
Fig. 1.(a) A vertically stacked multi-channel CTFET with n-on top of a p-type device, and (b) its specifications.(c) Model calibrations with respect to experimental work of Si/SiGe-based TFET.(d) Derived model parameters during the calibrations, i.e.BTBT generation factors (A gen and B gen ), m t * as quantum-corrected, and TAT with spatial distribution at Si/SiGe and fixed charge at Si/SiO 2 interfaces, respectively.

Fig. 3 .
Fig. 3. D pn significance (scaled from 20 nm down to 5 nm) in terms of (a) electron (e) and (b) hole (h) current density, followed by (c) e-TAT and (d) h-TAT including SRH, as contour plot (along x-cut) while n-CTFET is ON and p-CTFET is OFF, and vice versa.(e) Average contributions of aforementioned factors, i.e. (b)-(d).(f) I DS -V GS characteristics of p-and n-CTFET devices, respectively.

Fig. 5 .
Fig. 5. (a) Circuit model, (b) layout demonstration, and (c) extracted NM (hold and read) of 6T-IF-CTFET-SRAM.Replacement of cascaded inverters with CTFETs and cross-coupled logic are the reasons for the reduction of FP by 50% compared with the conventional device.Similarly, the (d) circuit model; extracted (e) read NM (compared with 6 T) and (f) current-voltage shifts across the external transistor node (Q bar ) of 7T-OF-CTFET-SRAM, respectively.

Table I .
Device design and material specifications.