Improvement of AlSiO/GaN interface by a novel post deposition annealing using ultra high pressure

In this study, a novel post-deposition annealing (PDA) technique employing ultra-high pressure was demonstrated for the first time. A 40 nm thick AlSiO gate insulator was deposited using atomic layer deposition (ALD) on n-type gallium nitride (GaN) epitaxial layers grown on free-standing GaN substrates. These PDA techniques were performed at 600 °C in a nitrogen ambient under 400 MPa, with normal pressure conditions used as the references. The annealing duration varied within the range of 10, 30, 60, and 120 min. For normal pressure annealing, the flat-band voltage of capacitance-voltage curves exhibited a shift towards the positive bias direction as the annealing time increased. Conversely, for the 400 MPa annealing, the flat-band voltage approached the ideal curve as the annealing time extended. For 400 MPa and 120 min, low interface state density of ∼5 × 1011 cm−2 eV−1 or less at E c −0.20 eV was obtained. These results suggest that post-deposition annealing under ultra-high pressure could be a viable method for improving the interfacial characteristics of AlSiO/GaN.


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allium nitride (GaN) holds great promise as a material for next-generation high-power devices due to its high breakdown electrical field strength of 2.8-3.5 MV cm −1 1,2) and high electron mobility. 3)Recent advancements in vertical GaN power devices, enabled by high-quality free-standing GaN substrates 4) and innovative processes like ion implantation using ultra-high pressure annealing (UHPA), 5,6) have been remarkable.However, power devices demand specific characteristics, such as a normally-off operation and high threshold voltage, for fail-tosafe operation.Although metal-oxide-semiconductor (MOS) devices have been employed for these purposes, the properties of the interface and the gate insulator in GaN devices remain inferior to those of silicon (Si) and silicon carbide (SiC) counterparts.
So far, several kinds of gate insulator materials for GaN devices have been extensively investigated, including silicon dioxide (SiO 2 ), [7][8][9][10][11][12][13][14][15] aluminum oxide (Al 2 O 3 ), [16][17][18] aluminum oxynitride (AlON), 19) aluminum silicate (AlSiO), [20][21][22][23] silicon nitride (SiN), [24][25][26] and others.[27][28][29][30] Among these, AlSiO has recently emerged as a promising gate insulator candidate due to less micro-crystallization during post-deposition annealing (PDA) and high permittivity of ∼7.An AlSiO layer is formed through alternating deposition of Al 2 O 3 and SiO 2 using atomic layer deposition (ALD) at low temperatures (∼250 °C) followed by PDA at temperatures typically higher than the deposition temperature (ranging from 950 °C-1050 °C).20,21) However, it is well-known that PDA at high temperatures leads to the formation of GaO x at the interface and Ga diffusion from GaN into the insulator, resulting in the degradation of gate insulator properties and device characteristics. 31) Hence,we focused on the effect of ultra-high pressure at relatively low temperatures on the insulator and the interface characteristics, rather than high-temperature annealing. Annealng under ultrahigh pressure aims to densify the gate insulator and suppress the formation of interfacial reaction layers, such as GaO x , by reducing the migration of atoms within the layers through lattice distance shrinkage under ultra-high pressure.
In this study, we investigated the effects of PDA at 600 °C under ultra-high pressure.We observed that the capacitancevoltage (C-V) characteristics for the PDA using ultra-high pressure approached the ideal curve with annealing time.This novel PDA technique shows promise as an effective method for enhancing the characteristics of the gate insulators in GaN devices.
Figure 1 depicts the MOS capacitors used in our study, fabricated on 8 μm thick Si-doped n-type GaN layers with a Si concentration of 2.5 × 10 16 cm −3 , grown on free-standing n + type GaN (0001) substrates using metal-organic vapor phase epitaxy (MOVPE).After cleaning the surface with sulfuric and hydrochloric acid solutions, followed by diluted hydrofluoric acid (HF), a 40 nm thick AlSiO (with a ratio of SiO 2 : 21%) was deposited by atomic layer deposition (ALD) at 250 °C.Subsequently, PDA was performed in nitrogen ambient under 400 MPa and normal pressure (0.1 MPa) as references, at 600 °C for 10, 30, 60, 120 min, as shown in Table I.The temperature was raised at a rate of approximately 10 °C min −1 for both ultra-high pressure and normal pressure conditions.Finally, gate electrodes comprising 200 nm thick Al were formed through resistance heating evaporation, and backside electrodes, consisting of Ti/Al/ Ni, were formed by electron-beam evaporation.
Figure 2 shows C-V characteristics of the MOS capacitors at 100 kHz at the sweep rate of 160 ms V −1 at the room temperature for 400 MPa and 0.1 MPa conditions.The curves were obtained in a clockwise direction to reveal the hysteresis.The ideal calculated curves were plotted on the graphs, assuming an electron affinity in GaN of 4.1 eV.It is evident from the figure that a significant difference exists between the 400 MPa and 0.1 MPa conditions.The C-V curve for 400 MPa and 120 min closely approaches the ideal curves, while the curve for 0.1 MPa and 120 min is far from ideal curves.Figure 3 shows the dependence of flat-band voltage (V FB ) and hysteresis (ΔV ) on the PDA time.We observed that the C-V curves for the 400 MPa condition approached the ideal curves as annealing time increased, while the flat-band voltage shifted in the opposite direction compared to the 0.1 MPa condition.This suggests that PDA under ultra-high pressure prevents the shift in flat-band voltage, attributable to fixed charges within the AlSiO layer.Some origins of the fixed charge, such as the defects in the AlSiO or the interfacial reaction layer, might be reduced by ultra-high pressure.
Figure 4 shows the interface state density (D it ) as a function of the energy in the range below E c .D it values were calculated using the Terman method, which analyses the response of the gap states to the DC bias change using the high-frequency AC small signal that the gap states cannot respond to.We found that D it decreased with the annealing time for 400 MPa and that the value at E c −0.2 eV was ∼5 × 10 11 cm −2 eV −1 or less for 400 MPa and 120 min.There was some error in our Terman method for 400 MPa and 120 min, since the measured curve is so close to the ideal one.This indicates an improvement in the AlSiO/GaN

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© 2023 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd interface due to ultra-high pressure annealing for extended periods.The hysteresis was mainly due to the trapping and the detrapping to these interface states, where the gate voltage was swept from 10 V to −10 V and from −10 V to 10 V. We assumed that the electrons were captured when the gate voltage started, and the electrons were emitted in the negative region of the gate voltage.
In Fig. 2, we can see the variation in the maximum capacitance (C max ) for 400 MPa and 0.1 MPa.In general, C max is determined by the insulator thickness and the permittivity.In Fig. 5, we showed the dependence of C max on the PDA time.Although C max for 0.1 MPa decreases with the annealing time, C max for 400 MPa increases.There are possibilities that the densification of the AlSiO or the increase of the permittivity of the AlSiO might be changed during ultra-high pressure, although the variation in the insulator thickness from sample to sample is included.We will clarify them using some analysis.
Figure 6 shows the current density and the electric field (J-E) characteristics.The breakdown electric field strength of the AlSiO for 400 MPa and 0.1 MPa is in the range of 9-10 MV cm −1 , which is comparable to that of SiO 2 . 14)We found that no degradation was observed due to ultra-high pressure annealing.
In this work, we demonstrated that the novel PDA technique using ultra-high pressure.For 400 MPa, the flatband voltage approached the ideal curve as the annealing time extended, unlike the normal pressure 0.1 MPa.Especially, for 400 MPa and 120 min, low interface state density at E c −0.2 eV of ∼5 × 10 11 cm −2 eV −1 or less was obtained.The annealing technique is an effective method for improving the characteristics of AlSiO/GaN interfaces.016502-4 © 2023 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd

Fig. 3 .
Fig. 3. Dependence of (a) the flat-band voltage V FB and (b) the hysteresis ΔV on the PDA time.

Fig. 5 .Fig. 4 .
Fig. 5. Dependence of the maximum capacitance C max on the PDA time.Fig.6. J-E curves obtained using the MOS capacitors of the diameter of 200∼500 μm for 400 MPa and 0.1 MPa.