Exploring thermally stable metal-oxide/SiO2 stack for metal oxide semiconductor memory and demonstration of pulse controlled linear response

We fabricated Al2O3/SiO2 stack structures with atomically thin Ti oxide layers at the interfaces using atomic layer deposition and investigated the capacitance–voltage (C–V) hysteresis of the metal-oxide-semiconductor (MOS) capacitors. We studied the effect of post-deposition annealing in the temperature range of 150 °C−500 °C on the C–V hysteresis and found that the Al2O3/SiO2-based stacks are thermally stable compared to ZrO2/SiO2- and HfO2/SiO2-based stacks. Using Al2O3/SiO2-based stacks, we investigated the impact of oxide layer thickness and gate electrode materials and studied pulse-induced current changes in MOS field-effect transistors.

T he metal-oxide-semiconductor (MOS) non-volatile memory has a long history. In the 1990s, erasable programmable read-only memory was widely used in computer systems to store system configurations, and recently, NAND flash memory has become commercially successful as a data-storage device. 1,2) Furthermore, intense research-and-development efforts are focused on improving flash memory performance, e.g. endurance and write/erase speed, and one of the promising candidates for improved flash memory is the ferroelectric field effect transistor. 3,4) In particular, HfO 2 -based ferroelectrics have been widely researched owing to their excellent compatibility with current complementary-MOS (CMOS) technology. [5][6][7][8][9] In the meantime, neuromorphic applications of such emerging memory devices are a recent hot topic. [10][11][12] Pulse-controlled changes in the conductance of memory devices have been applied to emulate the synaptic-weight update in a deep neural network (DNN) in a manner that is expected to enable energy-efficient machine learning. Even in neuromorphic applications, CMOS compatibility is a key criterion, and the materials and processes that meet that criterion are limited in a similar way to those for storage-memory applications.
Fabricating the gate-oxide stack is a key technology in the development of MOS-type memory. In consideration of the usefulness of state-of-the-art 3D device platforms such as 3D NAND flash memory and fin-type FETs, atomic-layer deposition (ALD) is the most advantageous in terms of film uniformity, and amorphous oxides are preferred to polycrystalline oxides. That is, amorphous oxides formed by ALD are preferred over polycrystalline oxides like ferroelectric HfO 2 for advanced memory devices. Recently, interface dipole modulation (IDM) memory based on an amorphous HfO 2 /SiO 2 stack incorporating an atomically thin TiO 2 has been reported as one candidate for memories close to the above conditions. 13) An electric-field-induced structural change is considered to occur around an interfacial TiO 2 to change the potential profile around the HfO 2 /SiO 2 interface. A multi-layered HfO 2 /SiO 2 structure was integrated into the gate stack to enhance the memory window because a single IDM effect is not so large (about 0.3 V). The first report of IDM memory utilized an HfO 2 /SiO 2 -based stack deposited by electron-beam (EB) evaporation method, 13) and then a similar memory operation was confirmed from those formed by the ALD method. 14) However, it was pointed out that the memory operation disappears when the IDM stack received the thermal processes, e.g. PDA at 350°C. 14) In a typical gate dielectric formation process using ALD, PDA is usually performed at temperatures above 400°C to improve dielectric properties, so exploring more tolerant IDM structures is crucial. Thus, in this study, we explore other oxide combinations to achieve a thermally stable IDM stack. The IDM mechanism requires contact of oxides with different dielectric constants, so we explore high dielectric constant oxides while leaving low dielectric SiO 2 . Considering the material affinity to the Si MOS device and mass-production compatible ALD process, ZrO 2 and Al 2 O 3 are potential oxides. In particular, Al 2 O 3 has a higher crystallization temperature than HfO 2 and ZrO 2 , making it a potential candidate. [15][16][17][18] Moreover, the multi-layered structure of the IDM memory is expected to be advantageous for analog operation in neuromorphic applications, because larger amounts of switchable dipoles can be integrated into the gate stack compared to the conventional ferroelectric memory with a single oxide layer.
The IDM MOS structure fabricated in this study is shown in Fig. 1(a). The gate-oxide stack was fabricated on a p-type Si(100) substrate covered with 3-10 nm thick layer of thermally grown SiO 2 . The Al 2 O 3 , SiO 2 , and TiO 2 layers were deposited by ALD at 200°C with trimethylaluminium, tris-dimethylamino silane, and titanium tetraisopropoxide precursors, respectively. The TiO 2 modulation layer was deposited in four cycles (about 0.16 nm). 14) The layers are stacked in a structure where a TiO 2 layer is always inserted between the Al 2 O 3 and SiO 2 layers, as shown in Fig. 1(a). The thickness of the upper-surface Al 2 O 3 layer was fixed at 3.5 nm, and the inner Al 2 O 3 and SiO 2 layers have the same thickness (t int ). From the C-V measurements of the MOS capacitors, the dielectric constants of the Al 2 O 3 and SiO 2 layers after PDA at 450°C were estimated to be 7.4 and 3.6, respectively. For comparison, ZrO 2 /SiO 2 and HfO 2 /SiO2-IDM stacks were fabricated by ALD. 14) In that fabrication, the ZrO 2 and HfO 2 layers were deposited with tetrakis-ethylmethylamino zirconium and tetrakis-ethylmethylamino hafnium precursors, respectively, and the other oxides were deposited with the same precursors as used for the Al 2 O 3 /SiO2-IDM structure. Here, we refer to the multi-layered oxide deposited by ALD is referred to as an IDM stack as shown in Fig. 1(a). The fabricated gate-oxide stack was subjected to PDA at substrate temperature (T PDA ) of 150°C−500°C in an atmospheric oxygen/argon mixture (21% O 2 ) for 30 min. As gate electrodes, aluminum and iridium were deposited by resistanceheating deposition and EB evaporation, respectively. In these cases, the electrodes with a diameter of 200 μm were fabricated using the stencil mask method. Also as gate electrodes, titanium-nitride and tungsten electrodes with an area of 100 × 100 μm 2 were fabricated using sputtering deposition and lithography. X-ray photoelectron spectroscopy (XPS) and transmission electron microscopy (TEM) were used to examine the structure of the prepared samples. For the TEM observations, an electron acceleration energy of 200 keV was selected because high-energy electrons often damage the oxides. To investigate the pulse-induced conductance change, n-channel Si FETs with titanium-nitride gate electrodes were fabricated by the gate-last process. 13) For the IDM FET (L g = 1 μm, W = 100 μm), pulse voltage was applied to the gate and drain current was measured with the source and substrate electrodes grounded at V ds = 50 mV.
The measured high-frequency capacitance-voltage (C-V ) curves of 6-IDM and 12-IDM MOS capacitors with t int = 2 nm and annealed at T PDA = 500°C are shown in Fig. 1(b). Here, "6-IDM" and "12-IDM" mean that six and twelve TiO 2 modulation layers, respectively, are included in the IDM stack. The C-V curves exhibit clockwise hysteresis likely induced by the IDM effect. In general, MOS capacitors fabricated on p-type Si substrates exhibit weak counterclockwise C-V hysteresis due to hole trapping in the gate oxide. The observed clockwise hysteresis is widened with an increasing number of TiO 2 modulation layers. As one of the characteristics of IDM, this TiO 2 -layer-number dependence suggests that potential modulations occurring at the Al 2 O 3 /SiO 2 interfaces are superimposed through the IDM stack. 13) It is therefore concluded that IDM occurs in the fabricated ALD-Al 2 O 3 /SiO 2 stacks similarly to the way it occurs in conventional HfO 2 /SiO 2 -based stacks.
The flat-band voltage difference (ΔV fb ) estimated from the measured C-V hysteresis curves is shown as a function of PDA temperature in Fig. 1(c). Positive and negative ΔV fb values mean clockwise and counterclockwise hysteresis, respectively. Namely, negative ΔV fb indicates loss of IDM. As for the Al 2 O 3 /SiO 2 stack t int = 2 nm, IDM can be obtained across the whole temperature range. Note that other Al 2 O 3 /SiO 2 stacks with various t int prepared in this work exhibited IDM even when subjected to 500°C PDA (not shown). The ZrO 2 /SiO 2 -based IDM stacks with t int = 2 nm also exhibited IDM characteristics, but their ΔV fb decreased with increasing PDA temperature, and IDM was lost above 250°C. As for the HfO 2 /SiO 2 -based IDM stacks with t int = 2 nm, the upper limit of PDA temperature is 350°C. 14) From the above comparison of ΔV fb , it is concluded that the Al 2 O 3 /SiO 2 based stack has a higher temperature of IDM losses compared to the ZrO 2 /SiO 2 -and HfO 2 /SiO 2 -based stacks. As previously reported, the origin of IDM loss by PDA was supposed to be the effect of residual impurities in the ALD HfO 2 layer. 14) In particular, it was suggested that the hydrogen and carbon in HfO 2 desorb during the annealing process to form oxygen vacancies in a manner that subtracts oxygen from the TiO 2 modulation layer. As long as the oxide layer is deposited by the decomposition of the metalorganic precursor, such impurities cannot be completely eliminated. 19,20) It is therefore reasonable to suppose that the Al 2 O 3 layers deposited in this study also contain such impurities, albeit at different concentrations. In addition, according to the Gibbs-free-energy difference, it is reasonable to suppose that the vacancies in Al 2 O 3 react with the oxygen in TiO 2 . However, the formation energy of oxygen vacancies in Al 2 O 3 is higher than that in ZrO 2 and HfO 2 . [21][22][23] We speculate that the supply of oxygen vacancies to TiO 2 is low, because the vacancy migration is accompanied by the formation of adjacent vacancies. Moreover, the formation energy of oxygen vacancies in ZrO 2 was estimated to be slightly smaller than that in HfO 2 , which is consistent with the experimental result presented in Fig. 1(c), where the PDA temperature at which +ΔV fb disappears for ZrO 2 /SiO 2 -based stack is slightly lower than that for HfO 2 /SiO 2 -based stack. 24,25) Another cause of IDM loss is atomic-scale structural change at the ZrO 2 /SiO 2 and HfO 2 /SiO 2 interfaces. The crystallization temperatures of HfO 2 and ZrO 2 are reported to be less than 600°C, 17,18) which is obviously lower than that of Al 2 O 3 (around 900°C). 15,16) Atomic-scale structural changes at the oxide/oxide interface probably proceed at a lower temperature than the crystallization temperatures, so The Japan Society of Applied Physics by IOP Publishing Ltd the ZrO 2 /SiO 2 and HfO 2 /SiO 2 interfaces potentially structurally change at lower temperatures than the IDM loss temperature of the Al 2 O 3 /SiO 2 interface. Moreover, the crystallization temperature of ZrO 2 is slightly lower than that of HfO 2 , which explains the difference between ZrO 2 /SiO 2 -and HfO 2 /SiO 2 -based stacks shown in Fig. 1(c). 26 Thinning the gate-oxide stack is expected to be effective in lowering the operation voltage of the MOS-type memory; however, in relation to the IDM stack, it has not been investigated in detail so far. Accordingly, in this study, Al 2 O 3 /SiO 2 -based IDM MOS stacks with various t int and subjected to annealing at T PDA = 450°C were investigated. In this investigation, ΔV fb induced by both positive and negative bias stresses was obtained by light-illuminated C-V measurement. 13,27) The inset in Fig. 2(a) shows the measured C-V hysteresis curves in the sweep-voltage range of ±4 V for an 8-IDM MOS capacitor with t int = 0.5 nm and an Al-gate electrode. Note that C-V hysteresis occurs at a lower voltage than that of the above-mentioned samples with t int = 2.0 nm. ΔV fb of 8-IDM stacks with various t int is plotted as a function of the applied electric field in Fig. 2(a). For the samples with t int = 1.0 nm, measured ΔV fb of different IDM stacks with bottom SiO 2 layers of 5, 7, and 10 nm is plotted. These plots show that ΔV fb increases from 2 MV cm −1 and saturates around 6 MV cm −1 . These three sets of data are found to be nearly identical in a manner that suggests that the electric field dominates the behavior of measured ΔV fb rather than the applied voltage. 13,27) On the contrary, as t int becomes thinner, the maximum ΔV fb in the saturation region becomes smaller. In the case of ideal IDM behavior, the modulation width is expected to be independent of oxide thickness, 13) but the results presented in Fig. 2(a) obviously differ from that expectation.
Maximum modulation voltage per TiO 2 layer (V IDM ) for 6-IDM, 8-IDM, and 10-IDM stacks with different gate metals shown in Fig. 2(b) reveals obvious dependence on oxide thickness. In the range of t int greater than 1 nm, maximum modulation is 0.5-0.6 V, which is larger than that (0.3 V) previously reported for HfO 2 /SiO 2 -based IDM structures. 13,27) On the contrary, it decreases significantly when t int becomes smaller than 1 nm. Accordingly, the physical origin of this thickness-dependent change of IDM was investigated by XPS with monochromatized Al Kα radiation. The observed Ti 2p, Si 2p, and Al 2p photoelectron spectra of IDM samples with t int = 1.0 nm (I) and t int = 0.5 nm (II) are shown in Fig. 3(a) and exhibit no obvious differences. These photoelectron spectra reveal that the sub-oxide components of titanium oxide, silicon oxide, and aluminum oxide are sufficiently small. It was previously reported that IDM loss in the HfO 2 /SiO 2 -based IDM structure correlates with the Ti 3+ component. 14,27) In fact, as shown by  PDA show a weak Ti 3+ component. We, therefore, consider that chemical bonding is not the major origin of the observed thickness dependence. TEM images of an Al 2 O 3 /SiO 2 -based IDM MOS stack with t int = 2 nm, t int = 1 nm and t int = 0.5 nm shown in Figs. 3(b)-3(d) show a layered Al 2 O 3 /SiO 2 structure. Note that the TiO 2 layer is indistinguishable due to resolution and contrast issues. On the contrary, the TEM image of the sample with t int = 0.5 nm shows an unclear layered structure with a partially unclear Al 2 O 3 /SiO 2 interface. The structural change at the Al 2 O 3 /SiO 2 interface is thus thought to lead to the reduction of IDM. Next, the relationship between IDM and interface structures is described in consideration of previously proposed mechanisms of electric-field-induced modulation. 13) As for the previous HfO 2 /SiO 2 -based IDM structure, it was proposed that (i) the bonding state around the titanium atoms at the interface is changed by the electric field and (ii) atomic-scale displacements of the positively charged titanium atoms and the negatively charged oxygen atoms lead to changes in the potential profile around the HfO 2 /SiO 2 interface. 28,29) In general, atomistic fluctuations occur at the interfaces with amorphous oxides, as reported in the case of HfO 2 /SiO 2 -based IDM structures. 13,27) Even at such a fluctuated interface, IDM occurs because changes in the distributions of oxygen and titanium atoms can induce effective potential differences. However, at a more disordered interface, the positional distributions of oxygen and titanium atoms overlap. In addition, it should be noted that the directions of electric-field-induced atom displacement are dispersed at such a disordered interface. The structural change is thus likely to hamper IDM. We, therefore, propose that maintaining interface flatness is a key factor in improving IDM in thin Al 2 O 3 /SiO 2 -IDM structures.
The experimental results shown in Fig. 2(b) demonstrate that all samples with various gate metals are in line with the same V IDM versus t int trend; namely, the gate metals do not have a significant effect on IDM characteristics. The gate metals used in this work were deposited by various methods, and the work functions are diverse, e.g. the work functions of iridium and aluminum differ by more than 1 eV. In general, compared to the other deposition methods, sputtering induces more defects in the oxides. Depending on the metal/oxide material system, contact of the metal with the oxide sometimes produces defects in the oxide. Namely, the fabricated gate stacks probably have various combinations of trap level and metal work function. It has been noted that carrier transfer between the gate metal and the oxide traps potentially induces IDM-like C-V hysteresis. 13) According to that defect-induced model, the hysteresis characteristics are predicted to depend on the defect levels and metal work function as well as defect density. The above results for various gate-metal samples suggest that the defect-induced model is not suitable for explaining the observed hysteresis characteristics.
The operation of an IDM FET in which an Al 2 O 3 /SiO 2 -based 8-IDM stack with t int = 0.8 nm and annealed at T PDA = 450°C was incorporated as a gate stack is described hereafter. The drain current−gate voltage (I d -V g ) curves shown in Fig. 4(a) show that the hysteresis width increases with widening sweep-voltage range. This result roughly agrees with that of the IDM MOS capacitor prepared under the same conditions and measured by light-illuminated C-V measurement. The channel conductance of this IDM FET was measured at a gate voltage of 1 V after applying a pulse voltage (V pulse ) with a pulse width of 100 μs. Cyclic measurements of conductance change at V pulse = ±9.6 V are shown in Fig. 4(b). They indicate that repetitive conductance modulation, i.e. pulse-controlled synaptic potentiation and depression, is possible. However, both the potentiation and depression characteristics shown in Fig. 4(c) show asymmetric nonlinear responses. From these curves, the nonlinear parameters for the potentiation and depression were estimated to be 2.7 and 5.7, respectively, by using previously proposed fitting equations. 30,31) It has been reported that a linear response is advantageous for synaptic-weight update in DNN learning, and linear characteristics can lead to high classification accuracy. 32,33) To reduce the nonlinear characteristics of the IDM FET, we applied variable voltage pulses, as shown in Fig. 4(d), where V pulse was changed linearly in the range from 7.8 to 9.6 V. According to the figure, the nonlinear parameters for both potentiation and depression are improved to 0.1 and 1.1, respectively. We believe that the IDM FET with variable voltage pulses is promising for synapse-weight-multiplier hardware for DNN systems.
In summary, we demonstrated higher temperatures of the IDM loss for Al 2 O 3 /SiO 2 -based stacks in the PDA process, compared with those for ZrO 2 /SiO 2 -and HfO 2 /SiO 2 -based stacks. We also demonstrated that thinning the Al 2 O 3 and SiO 2 layers reduces IDM, likely due to structural change of the Al 2 O 3 /SiO 2 interface. Moreover, we demonstrated hysteresis of the I d -V g curves of an Al 2 O 3 /SiO 2 -based IDM FET, and we proposed that variable voltage pulses can enable linear synaptic-weight updates of an IDM FET.
Acknowledgments Part of the device fabrication was conducted at the AIST Nano-Processing Facility (AIST-NPF).