Reconfiguration of nondestructively readable superconductor memory by direct injection of magnetic flux to storage loop

In this study, we demonstrate a novel method for the reconfiguration of a nondestructively readable memory cell for superconductor integrated circuits. The proposed reconfiguration method involves the direct injection of flux quantum to the storage loop of the memory cell, which has been achieved using interface circuits in previous studies. By applying this method, the footprint of the superconductor memory cell can be reduced by half. We experimentally demonstrate the proof-of-concept of the investigated reconfiguration method. We expect that the memory cell reconfigured using the proposed method will be suitable for building large-scale lookup tables using superconductor circuits.

S uperconductor circuits such as a single-flux-quantum (SFQ) circuits, 1,2) quantum flux parametrons 3) and their modified versions [4][5][6][7][8] have been studied as the next-generation high-speed, low-power integrated circuits. 9) The superconductor digital circuits use tiny magnetic flux, known as a flux quantum in a superconductor, to express the binary logical state. Owing to the small bit energy of the superconductor circuits, the circuit function can be easily reconfigured by applying a control current and magnetic flux. Reconfigurable logic devices based on superconductor circuits have been widely studied. [10][11][12][13][14][15][16] A field-programmable gate array (FPGA) 17) is one of the promising and practical applications of the superconductor reconfigurable logic device. [18][19][20][21][22] A lookup table (LUT) that realizes arbitrary logic functions by reconfiguring its memory cells is the main circuit component of the FPGA. We had previously developed a superconductor memory cell that could be reconfigured by applying external control currents and read out by inputting an SFQ clock. 23,24) For this memory cell, highspeed nondestructive read-out at frequencies beyond 50 GHz was possible through SFQ read-out. However, its reconfiguration speed was less because of the use of external control currents. 23) Nevertheless, this memory cell is suitable for building large-scale FPGAs based on SFQ circuits, because high-speed reconfiguration of the LUT is not required in FPGA applications. We also demonstrated the operation of superconductor LUTs composed of our proposed 4-bit and 64-bit memory cell arrays. 23,24) However, for building a large-scale LUT, in addition to advanced circuit-fabrication process, reduction in the footprint of the memory cell used in the LUT is also necessary. In a previous study, we used a non-destructive read-out flip-flop (NDRO) with interface circuits, called magnetically coupled DC/SFQ converter (MC-DC/SFQ), as the memory cell. The MC-DC/SFQ converter converted the input current to an SFQ pulse 25,26) and the internal state of the memory was reconfigured to "1" by holding the input SFQ in the storage loop. The internal state of "1" could be reset to "0" by releasing the stored SFQ by inputting a reset SFQ pulse produced by the other MC/DC/SFQ. By aligning the memory cell in a twodimensional matrix, a large-scale scalable LUT could be built. However, the use of two MC-DC/SFQs increased the footprint of the memory cell. Because the footprint of the memory cell directly affects the LUT integration level, the circuit structure of the memory cell must be simplified to reduce its footprint, while building large-scale superconductor LUTs.
In this study, we propose a new reconfiguration scheme for nondestructively readable superconductor memory cells used in LUTs. By applying the proposed reconfiguration scheme to a memory cell and eliminating the MC-DC/SFQs, we can simplify the circuit structure of the memory cell. The size of the memory cell designed using the new reconfiguration scheme is approximately half of that in the previous study. We experimentally demonstrate the reconfiguration of the internal state and nondestructive read-out operation of the designed memory cell that employs the proposed reconfiguration method. Figure 1 shows the equivalent circuit of the memory cell studied considered in this study. This memory cell is designed based on the NDRO cell in the CONNECT cell library. 27) The state with no flux quantum stored in the circuit corresponds to the internal state of "0". The state where the flux quantum is stored in the storage loop that comprises inductors L 1 , L 2 , L 3 , L 4 , and L 5 shown in Fig. 1, is "1". The control currents, I x and I y , are magnetically coupled to the storage loop. The application of both I x and I y directly injects the flux quantum to the storage loop, and the internal state transition from "0" to "1" is induced. By inputting an SFQ pulse from the "clk" port, the internal state of "1" is nondestructively read out and output to the "dout" port. In the "1" state, applying I reset induces the switching of J 3 and the stored flux quantum is released. This corresponds to state initialization to "0". Thus, by inputting appropriate control currents, arbitrary reconfiguration of the internal state is possible, whereas the memory cell in the previous study required MC-DC/SFQs to input the SFQ signals to the storage loop to reconfigure the internal state. By employing this new reconfiguration scheme, the MC-DC/SFQs can be eliminated and the circuit structure can be simplified. As the result, the number of Josephson junctions (JJs) comprising the memory cell is reduced by 2.
We confirmed the correct reconfiguration and nondestructive read-out of the memory cell through transient analysis using the analog circuit simulator JSIM 28) with the AIST 10 kA cm -2 Nb high-speed standard process (AIST-HSTP). 29,30) We optimized the circuit parameters of the memory cell to obtain a wide operating margin using the parameter-optimization tool for the SFQ circuit, SCOPE. 31) The circuit parameters described in the caption of Fig. 1 are the optimized ones. We also obtained the circuit-parameter margins to evaluate the robustness of the parameter spread caused by the fabrication process. Figure 2 lists the device-parameter margins of the JJs and the bias voltage (V b ) obtained in the analog circuit simulation. The device that has the smallest margin of 17.2% is J 2 . This margin is larger than the typical criticalcurrent deviation in the AIST 10 kA cm -2 Nb fabrication process. 30) Figure 3 shows the input magnetic flux margins required for the reconfiguration of the internal state of the memory cell from "0" to "1". The area surrounded by the dashed line corresponds to the operating margin. Assuming the operating point of the memory cell is at Φ x = 0.54 Φ 0 and Φ y = 0.58 Φ 0 , where Φ 0 is the flux quantum, as indicated in Fig. 3, the input flux margins are 0.31 Φ 0 < Φ x < 0.77 Φ 0 and 0.25 Φ 0 < Φ y <0.83 Φ 0 . We believe that these input flux margins are wide enough for building a large-scale memory cell array for the LUT.
We designed the memory cell based on the new reconfiguration scheme using the AIST-HSTP. The inductanceextraction tool InductEX 32,33) was used for inductance adjustment. Figure 4 presents a comparison of the mask layouts of the previous memory cell and the one reconfigured using the scheme proposed in this study. Owing to the simplified circuit structure and reduced number of JJs, the footprint of the new memory cell could be reduced to half of that of the previous study. Table I

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According to the circuit simulation, the maximum read-out frequency of the new memory cell is almost the same as that of the previous one. Simulation results also indicate that applying 5 ps width trapezoidal control currents can induce the state transition of the memory cell. This indicates that the designed memory cell has the potential for high-frequency reconfiguration if on-chip high-speed current/voltage drivers [34][35][36][37] are used.
We tested the implemented memory cell using a low-speed function test. The implemented test circuit was measured in liquid helium at 4.2 K. Figure 5 shows an example of the low-speed test result. The internal state of the memory cell was reconfigured to "1" by applying both I x and I y . After applying both I x and I y , the internal state of "1" was read out nondestructively, in synchronization with the "clk" inputs, until I reset was input. The measured normalized DC bias margin was −15% to +10%. Under the designed bias conditions, V b was 2.5 mV and the measured input flux margins were 0.37 Φ 0 < Φ x < 0.74 Φ 0 and 0.35 In summary, we introduced a new reconfiguration method for the internal states of nondestructively readable superconductor memories. By using direct magnetic flux injection to the storage loop in the memory, we could reconfigure the internal state. The new reconfiguration method could simplify the circuit structure and reduce the number of devices comprising the memory. We implemented and tested the memory cell that was designed based on the new reconfiguration method and confirmed proper functioning of the memory cell. We hope that the memory cells proposed in this study will lead to the realization of large-scale superconductor LUTs.  5. Example of the measured oscilloscope view. The clock (clk) signal is input via the DC/SFQ converter, and the SFQ clocks are input at the rising edges of "clk". "dout" is the output voltage of the SFQ/DC converter, which is amplified by 100 using a differential amplifier. Voltage transitions of "dout" correspond to "1" outputs.