Fabrication of low-resonant-frequency inertial MEMS using through-silicon DRIE applied to silicon-on-glass

This paper reports on a fabrication process suitable for ultra-low resonant frequency inertial MEMS sensors. The low resonant frequency is achieved by electrically tunable springs and a heavy mass formed by through-silicon deep reactive-ion etching (DRIE) applied to a silicon-on-glass. A thermal issue of through-silicon DRIE (TSD) stemming from the low-resonant-frequency structure is circumvented by two methods: introducing cooling time between the DRIE steps, and adopting a metal hard mask. A blade dicing method suited for this process is also presented. To monitor the verticality of TSD, a non-destructive taper detection method that utilizes a capacitance–voltage (CV) curve is proposed and verified.


Introduction
Microfabrication technologies have enabled miniaturization and mass-production of inertial sensors and gave birth to the Internet of Things (IoT) applications. 1)MEMS inertial sensors are now being developed for seismic and geophysical applications. 2,3)Inertial sensors in this field require low resonant frequency to attain the high sensitivity. 4)The mechanical resonant frequency is determined by a factor k m / with k and m being the stiffness and the mass, respectively.This suggests the difficulty of attaining the low resonant frequency in the microscale, as the mass inevitably becomes small in this region.To date, several approaches have been adopted to overcome this issue.A method is to make the mass m as heavy as possible even for the small size.Pike et al. have attached a gold weight to the proof mass and succeeded in lowering the resonant frequency from 14 to 6 Hz. 5) Another approach is to lower the stiffness k.Middlemiss et al. have made an ultra-small stiffness by combining positive and negative mechanical springs. 6)The resonant frequency as small as 2.3 Hz was achieved by this approach.This method was further extended by Tang et al. 7) and Zhang et al. 8) Recently, Wu et al. from the same group attained a 0.7 Hz resonant frequency using the quasi-zero stiffness mechanism. 9)Along with this trend, we have previously proposed a method to lower the resonant frequency using negative electrical stiffness. 10)owever, in the manufacturing process, the weak mechanical springs and large mass cause an issue with respect to heat dissipation. 11)Due to insufficient cooling during the throughsilicon DRIE (TSD) process, the topside temperature of the wafer goes up.The high temperature will result in resist burnout during the TSD process.Etching can no longer be done with this burnt resist.Finding a method to prevent this problem is therefore prerequisite for TSD.This is the first aim of this paper.
The second aim of this paper is to provide a dicing method suited for our device.) Unfortunately, this method cannot be applied to our MEMS, since it includes a glass layer to which stealth dicing cannot be applied.We therefore need to employ a blade dicing to our uncapped wafer.11) For this purpose, we have developed an efficient method to protect the movable portion from the cleaning water of the blade dicing.
Tapering of trenches is a common issue during the DRIE process. 16)Minimization of the taper is especially important for high-aspect-ratio TSD as in our device.Various parameters that affect the taper are known by now and the taper can be, in principle, minimized with this knowledge. 17,18)An issue here is the method to monitor the taper.The cross-sectional taper shape monitoring by the scanning electron microscopy (SEM) is a standard method for this purpose.This method, however, is timeconsuming and also destructive.It is also not suited for monitoring the taper distribution within a wafer.In view of this, we developed a non-destructive taper monitoring method suited for wafer-level taper monitoring.

Design
The methodology to attain the ultra-low resonant frequency is explained in our previous work. 10)The essence is that the total spring constant k is formed by a positive mechanical spring k m and an electrically tunable spring k .
e As shown in Fig. 1(a), the spring k e is formed by symmetrical electrodes.Thus, the attractive electrostatic force induces a negative stiffness: k V , where V e is the voltage difference of the electrodes and a is a structure-dependent constant.The resonant frequency of this system is described by . This suggests that f res can be tuned by the voltage V , e as shown in Fig. 1(b).A multi-step tuning method described in our previous paper ensures finetuning of f res even at the low-frequency regime. 10)Our target is to attain f 1 res < Hz.The design parameters of our device are listed in Table I.

MEMS process
The MEMS structure consists of two layers as shown in Fig. 2. The first layer is a partially etched glass substrate of 700 μm thickness.The second layer is a silicon structure layer of 525 μm thickness.TSD is applied to this layer.The minimum gap of trenches is set to 25 μm.The glass layer is employed since it is advantageous in attaining low parasitic capacitances.The recess region in the glass is introduced to avoid touching between the movable structures and the glass substrate.To determine the recess depth, two cases are examined as shown in Fig. 3. Firstly, during the anodic bonding process, a pressure of 50 kPa is applied.As shown in Fig. 3(b) The touching is observed only in the size of 6 mm × 6 mm.If the cavity length is less than 4 mm, 3 μm depth is enough to avoid the touching.We determined the cavity length based on this observation.Secondly, after TSD, the movable parts should not touch the glass under gravity, as shown in Fig. 3(c).According to the simulations, the maximum deformation caused by gravity is 0.689 μm.Therefore, the recess depth is set to 3 μm to ensure sufficient margin.It should be mentioned that the deformation under gravity is larger than that by the pressure, since the silicon is etched by TSD in the former case.
To construct the above structures, a fabrication process composed of three steps is adopted: (a) forming recesses on top of a glass wafer, (b) anodically bonding a silicon wafer to the partially etched glass wafer, and (c) applying TSD to the silicon layer.Detailed fabrication steps are shown in Fig. 4.
The MEMS process starts with a glass wafer used as the substrate.A recess region for movable structures is formed on the glass substrate.Firstly, an etching mask of 500 nm thick   056501-3 © 2024 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd SAMCO's RIE-800iPB is used for this process.The etching gas is SF 6 and the passivation gas is C 4 F 8 .After this, the silicon above the recess region becomes movable.The remaining Al is used as a pad.

Thermal issue and solutions
Thermal problems in the TSD process stem from insufficient heat dissipation of the generated heat.Let us explain this in more detail.The heat capacity is given by C cm, th = where c is the specific heat capacity of the material and m is the mass of the material.The thermal resistance is given by R L A, where L is the heat flow path length of the material, A is the cross-sectional area, and k is the thermal conductivity of the material.The large mass brings about a high heat capacity C th and the folded spring brings about a large thermal resistance R .
th As a result, the thermal time constant, becomes significantly large.The thermal properties of our MEMS are listed in Table II.On the other hand, the glass layer acts as a thermal insulator.As shown in Fig. 5(a), the insulation is enhanced at the glass recess portion which is kept in a vacuum.Thus, the heat cannot be dissipated by the bottom chiller and the topside temperature will rise during the DRIE process.The PR will burn when the temperature goes up higher than the PR's bake temperature of 110 °C.A photo of a wafer with the burnt resist is shown in Fig. 5(b).If the DRIE step is continued, the silicon structure with the burned PR will be damaged.
We circumvent this heat issue by two methods.Firstly, we introduce a cooling time between each DRIE cycle to ensure heat dissipation.As indicated in Fig. 5(c As estimated in Fig. 5(d), the thermal time constant th t becomes significantly large just before the etching penetrates the silicon layer.To minimize the total etching time, the cooling time is varied based on .th t The total etching time is increased from 1.5 to 3.5 h by this.
Using an aluminum (Al) hard mask is also effective in preventing the thermal issue.As the etching proceeds, the resist vanishes and only Al remains.The risk of thermal damage can be reduced by the remaining Al hard mask, since the Al has higher thermal conductivity than PR and high melting temperature.It should also be mentioned that the Al has a sufficiently high selection ratio in the DRIE process.
Using the two methods explained above, we confirmed that TSD can be carried out successfully.The SEM photo is 056501-5 © 2024 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd shown in Fig. 6.A slight taper observed on the side walls is not an issue for the device operation.

Dicing method
A dicing method suitable for this thick silicon-on-glass (SOG) wafer is also developed.Since our device possesses a glass layer, stealth dicing, a wafer-free dicing method for silicon, cannot be employed.Thus, a blade dicing method shown in Fig. 7 is adopted for our uncapped wafer.Firstly, the dicing lines of the silicon layer are just etched in the TSD process.Next, in order to protect the movable structures from the cleaning water and vibration caused by the blade dicing, a thermal release tape REVALPHA TM,20) is pasted to the silicon side before the dicing.The thermal release tape was found to bring less damage than UV tapes, as shown in Fig. 8.Then, a blade dicing is applied to the glass layer.The thermal tape protects the movable part from the cleaning water.This dicing is programmed to stop before it reaches the silicon layer.Finally, the tape is released by heating at 120 °C.We selected the tape type that minimizes the MEMS damage during this release process.The fabricated chip photo is shown in Fig. 7(d).
(  A non-vertical cross-sectional shape of trenches is shown in Fig. 9(a).This kind of taper has an impact on the device's function.For example, it reduces the stroke of the movable components.Usually, a cross-sectional SEM is used to monitor the taper.This method, however, is destructive and cannot obtain taper distribution data over a wafer.In view of this, we developed a non-destructive method based on waferlevel electrical measurements.Let's consider the cross-sectional shape of the trenches as in Fig. 9(b).We assume that the deviation from the ideal vertical sidewall is expressed by a quadratic function: ( ) e ah bh c, 3 where h is the height measured from the top, and a, b and c are constants.The capacitance between the parallel plates can be calculated from the following equation: where 0 e is the vacuum permittivity, l c is the length of the capacitor, d 0 is the initial gap of the electrodes, and h w is the thickness of the silicon layer.When applying voltage difference V a to the parallel plates, the actuators generate an attractive electrostatic force F .
c On the other hand, the mechanical springs generate a repulsive force F. s We assume that the gap in the balanced state is written as d x, 0where x is the displacement of the movable plate.In this state, the capacitance is expressed as The electrostatic force F c that applies to the electrodes can be calculated from the potential energy as On the other hand, there is a mechanical spring force is given by where k is the spring constant.If the actuation voltage V a is lower than the pull-in voltage, the two forces will make a balanced state.This situation is expressed as a zero total force condition This equation determines the gap between the electrode and hence the capacitance.Therefore, if we fit the measured capacitance-voltage (CV) curve with the model described by Eqs. ( 5) and ( 8), we can determine the parameters.More specifically, we regard Eq. 8 as a constraint between x, a, b, c, k and V .
a Then, together with Eq. 5, we determine the parameters so that the model reproduces the measured CV curve.This fitting procedure is done numerically.

C-V curve analysis
We are now in a position to discuss about the taper shape based on the above method.A simplified actuator structure as shown in Fig. 10(a) is used.The key parameters of the test device are listed in Table III.The proof mass is anchored to the glass substrate with four folded springs.When a drive voltage V a is applied to the actuator, the generated force makes a displacement of the proof mass.This results in a change of the actuator capacitance.The CV measurement is carried out with Keysight Technologies B1500 semiconductor parameter analyzer. 21)The measured CV curves for several samples are shown in Fig. 10(b).A plot corresponding to the ideal vertical wall is also shown.To extract the parameters, a nonlinear least-squares solver function "lsqnonlin" in MATLAB is used.The resulting parameters are summarized in Table IV.
The microscope photos of samples are shown in Fig. 11.Sample #1 has capacitors with a larger taper and sample #2 has capacitors with a smaller taper.The mechanical stiffness of sample #2 is much closer to the ideal value.This suggests that the DRIE condition used for sample #2 is more suited for the vertical wall.The relative error of this method is less than 8%.We regard that this error is mainly caused by the fringe capacitance not incorporated   © 2024 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd in the theoretical model.The approach presented here is useful in obtaining a wafer map of the taper distribution.
And since this method is non-destructive, it can be utilized in the test sequence of the device production.

Conclusions
In this paper, a fabrication process suitable for SOG-based low-resonant-frequency inertial MEMS sensors is presented.A thermal issue of TSD stemming from the low-resonantfrequency structure is prevented by enhancing the heat dissipation with two methods: introducing cooling time between the DRIE steps, and adopting a metal hard mask.These methods can be also applied to the fabrication process with a similar thermal issue.A blade dicing method suited for this device is also developed.To monitor the cross-sectional shape of the trench, a non-destructive method using CV data is shown.

Fig. 4 .
Fig. 4. Fabrication process flow: (a) fabrication for a glass wafer, (b) Si wafer is anodically bonded to a partially etched glass wafer, and (c) fabrication for an anodic-bonded wafer.
), the heat on the mass is transferred via three kinds of paths: remaining silicon layer R , T th silicon spring R , S th and glass R .G th In this case, the

Fig. 5 .
Fig. 5. (a) Thermal issue during DRIE, (b) photos of a wafer with burnt resist, (c) heat transfer paths in the vacuum chamber during DRIE, (d) estimated thermal time constant , th t and (e) principle of adding cooling time.

Fig. 10 .
Fig. 10.(a) Structure of the verification device.(b) The capacitancevoltage curve.The capacitance difference is used.Sample #2 is closer to the ideal shape.

Table II .
Detailed thermal properties of our MEMS.
©2024The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd total thermal resistance R th_tot becomes

Table III .
Key dimensions of samples.

Table IV .
Comparison between the measured and calculated value of the gap distance with taper error.
©2024The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd