Growth of CuAlO2 on SiO2 under a layer-by-layer approach conducted by digitally processed DC sputtering and its transistor characteristics

A CuAlO2 (CAO) bottom gate top contact p-type thin film transistor (TFT) is demonstrated. The CAO thin film is synthesized through a digitally processed DC sputtering (DPDS) technique, employing a precise layer-by-layer (LBL) deposition strategy. X-ray diffraction analysis exhibited distinct peaks beyond 600 °C. The CAO film shows a dominant phase along the (004) plane at the elevated temperature of 990 °C. The fabricated CAO p-TFT exhibits field effect mobility of 4.1 cm2 V−1 s−1. In addition, the p-TFT characteristics were observed even in the as-deposited CAO film. The DPDS-assisted LBL approach offers a promising pathway for controlled stacking deposition routes in the growth of CAO thin films, enabling enhanced performance and device integration.


Introduction
Wide-bandgap (>3 eV) metal oxides (MOs) with high mobility as well as reliable optical transparency (>80%) attend to the burgeoning demand for application in large-area electronic and optoelectronic devices.In commercial applications, the prevalence of n-type MOs supersedes that of their p-type counterparts. 1) significant breakthrough in n-type MOs was achieved by Nomura et al. 2) in 2003 with the demonstration of an indiumgallium-zinc-oxide (IGZO) single-crystalline active layer thin film transistor (TFT) having an electron mobility of 80 cm 2 V −1 s −1 and an on/off ratio of 10 6 . 2,3)However, the challenge of fabricating high-performance devices at lower processing temperatures was first addressed in 2004 with the introduction of an amorphous oxide semiconductor TFT utilizing amorphous In-Ga-Zn-O (a-IGZO). 4)Nomura et al. 5) deposited a-IGZO at RT, exhibiting field effect mobility in the saturation region of 8.3 cm 2 V −1 s −1 and in the linear region of 5.6 cm 2 V −1 s −1 . 5)This high-performance n-type TFT justified its potential application in electronic devices.On the other hand, the quest for p-type MOs TFTs having comparable performance to n-type counterparts continues to face formidable challenges. 6)he absence of p-type counterparts can be attributed to the strong confinement of the upper edge of the valence band around the oxide ions. 7)Kawazoe et al. 8) realized that modifying the energy band structure would alleviate such localization behavior.In this regard, the Cu + cation is an intriguing choice due to the highest energy for the d 10 closed shell electrons, which is expected to overlap with the 2p electrons of oxide ions.The tetrahedral coordination of oxide ions mitigates the localization behavior of 2p electrons.However, the direct interaction between d 10 electrons of neighboring Cu + ions reduces the bandgap.CAO has been identified as a potential candidate due to its ability to reduce the dimension of Cu + ions, leading to a consequent enlargement of the bandgap. 8)The current research has chosen CAO due to its p-type nature and potential application as a transparent conductive oxide material. 9)CAO is composed of AlO 6 octahedra spread out, forming a basal layer and alternating stacking layers of O-Cu-O dumbbells structure vertically 10) as shown in Fig. 1.CAO could be synthesized by different routes, i.e. a spin coating method, 11) MBE, 12) and RF magnetron sputtering. 13)Where magnetron cosputtering and reactive sputtering are prevalent methods for fabricating CAO thin films.Hsieh et al. 14) utilized RF sputtering to deposit films on (0001) sapphire substrates from an Al-Cu metallic target, with subsequent annealing at various temperatures in a nitrogen atmosphere.Results indicated amorphous as-deposited films, crystallization of CuO at 600 °C, and formation of crystallized CuAlO 2 at 800 °C with preferred (00l) orientation.Similarly, under RF magnetron sputtering, Yongjian et al. 15) deposited CuAlO on quartz and silicon, revealing amorphous as-deposited films and dominance of the CAO phase after annealing in argon ambiance.The dominance phase increment in the hall mobility, as well as carrier concentration of the film, was ascribed to the improvement in grain boundary and crystallization.YJ Zhang et al. 16) synthesized CuAlO films on Si and quartz substrates via RF magnetron sputtering, observing crystalline transformation from amorphous at 700 °C-900 °C, improving hall mobility due to reduction in the scattering and trapping of carriers.At the same time, further annealing to 1000 °C resulted in reduced mobility due to microcrack formation.Liu et al. 17) deposited CuAlO films using RF reactive magnetron sputtering, noting phase transitions at specific substrate temperatures and emphasizing the dependence of conduction on film crystallinity and phase purity.Ievtushenko et al. 18) investigated the influence of substrate temperature on Cu-Al-O films deposited using reactive ion beam sputtering, revealing increased substrate temperature leading to CuAlO 2 phase formation.Tsuboi et al. 19) successfully prepared CuAlO 2 films using a dc-reactive sputtering method with Ar-diluted oxygen gas, achieving stoichiometric CuAlO 2 films through post-annealing at temperatures exceeding 700 °C in a nitrogen atmosphere.The oxygen molar fraction decreased with post-annealing at temperatures higher than 700 °C, approaching 0.5.
Along with poor film quality, the deficiency of Cu-O-Cu lattice connectivity 21) in the CAO structure is also accountable for the low field effect mobility.Addressing such issues requires a layer-by-layer (LBL) deposition approach that enables the c-direction stacking of CuO and AlO, focusing on the d-spacing of CAO.Recently, digitally processed DC sputtering (DPDS) has been proposed as an atomically precise deposition method. 22,23)This study utilized the DPDS-conducted LBL approach for CAO thin film growth for the first time.
The LBL approach enables precise control of the growth process, leading to ordered CuO, AlO stacking, and formation of long-range structural integrity, which is believed to facilitate carrier transport increase.There is no scattering, and it contributes to the improvement of mobility.
Moreover, the LBL deposition facilitates better control over the growth process, which minimizes the formation of grain boundaries in CAO and also contributes to higher mobility.The DPDS allows the deposition rate to be 0.57 nm/ cycle under the d-spacing of the (002) plane for good CAO crystallinity.In the growth of CAO by DPDS-assisted LBL, non-radical oxidation was prioritized to avoid possible surface damage. 23)In this report, structural analysis and electrical performance of the fabricated CAO p-TFTs have been presented.

Experiment
2.1.Optimization of DPDS conditions for the LBL deposition In this work, deposition was performed by the DPDS system (SHINCRON CO., LTD.P-RAS), which utilizes a digital pattern generator (DPG) for pulsed-DC sputtering.The DPDS system consists of two cathodes attached with a high-voltage switch (HV-SW) for each and one DC power supply.Each cathode is directly driven through HV-SW by the DPG to generate pulsed plasma independently, which allows sputtering of the selected metal target and sputtering pauses. 22)On the other hand, oxygen is supplied by generating a valve open/close pulse in synchronization with the sputtering interruption to achieve saturation adsorption/ oxidation after deposition of the metal atomic layer. 23)he sputtering process employed Cu and Al metal targets with a diameter of 2 inches and Si(100) and SiO 2 /Si as substrates.Each metal target was independently subjected to pulsed-DC plasma generation by DPG in an Ar atmosphere.The process was carried out without substrate heating and at a pressure of 5 Pa with an Ar flow rate of 50 SCCM, and a pulsed oxygen supply of 13 SCCM during sputtering interruption was applied.Consequently, the LBL deposition of CAO can be achieved by DPDS.The repetition of CAO stacking in a unit cell is twice; hence, the deposition was desirable to half the height, i.e. 0.57 nm.In such a context, the deposition rate was set to 0.57 nm/cycle, corresponding to the d-spacing of (002) in CAO. Figure 2(a) shows the programmed process pulse pattern for the LBL deposition procedure of CAO.The fundamental pulse frequency for generating pulsed-DC plasmas on both metal targets was 80 kHz, and the duty ratio was set to 50%.The actual process pulses were synthesized by combining them with the base pulse and each process pulse using AND logic.To obtain a deposition rate of 0.57 nm/cycle, the sputtering time of each metal in one cycle was adjusted to 1.9 s for Cu and 6 s for Al, respectively, discussed with the DC power supply conditions described below.The significant difference in sputtering time can be attributed to the difference in sputtering yield between Cu and Al metals. 24)With a predefined oxygen supply time (t O 2 ) of 1 s and purge time (t purge ) of 3 s, an optimal temporal separation is achieved between the oxidation process and plasma generation.
The DPDS system employs a DC power supply, allowing three operation modes: constant voltage (C v ), constant current (C c ), and constant power (C p ) modes, which can limit the operation voltage, current, and power, respectively.To obtain stable ignitions for frequent plasma generation on each target, the voltage and current limit were set to 350 V by C v mode and 0.25 A by C c mode, respectively.Figure 2(b) shows the voltage and current responses of the DC power supply output along the progress of LBL deposition.A sharp overshooted current (I overshoot ) is noticed at the rising edge of the current pulse, which seems to be due to micro ark at the Al metal target and then limited by C c mode.Well-defined transitions between the metal sputtering and the oxygen supply in sputtering interruption are readily discernible.Basically, the deposition rate should be controlled under C p mode in order to manage the fluctuation of plasma impedance, and the Al sputtering was conducted by C p mode set to 70 W. On the other hand, the Cu sputtering was conducted by C v mode due to the higher plasma impedance, and the average power was about 60 W. Note that the precise response of voltage and current pulses of the plasma was continuously observed during the sputtering process, suggesting that a LBL process was established.Through measurements conducted using an electron probe microanalyzer (EPMA), the DPDS conditions were determined to achieve the LBL process, precisely tailored to the requisite metal composition.
The LBL-deposited CAO films were annealed in air, with temperatures up to 990 °C.This annealing process effectively enhanced the chemical and physical stability of the CAO samples, facilitating the formation of CuO nucleation centers at 600 °C and inducing phase transformations above 600 °C.The crystalline nature of the CAO thin film was assessed using X-ray diffraction (XRD) with CuK α1 radiation.Notably, at 990 °C, a dominant CAO phase was observed, characterized by a highly c-axis orientation verified through rocking curve scanning.

Fabrication of CAO TFTs
The architecture of a TFT encompasses active channels, electrodes, and dielectric layers.In this work, highly oriented CAO for bottom gate top contact TFT configuration was deposited on a SiO 2 /Si substrate under a shadow masking technique to achieve precise patterning.Firstly, a 200 nm SiO 2 layer was meticulously deposited on a p-Si substrate.Subsequently, a precisely positioned shadow mask was employed to facilitate the controlled growth of a (CAO) channel on the SiO 2 /Si substrate.Finally, the source (S) and drain (D) electrodes were deposited atop the CAO/SiO 2 /Si structure using a thermal evaporator.The shadow mask approach deposited Al S/D electrodes on the CAO/SiO 2 /Si structure to establish the desired electrical connections.Then, a back gate electrode was formed on the back side of the substrate.The schematic of the fabrication steps is illustrated in Fig. 3(a).The separation between S/D electrodes is termed channel length (L), while the overlapping distance between the electrodes is termed channel width (W), as shown in Fig. 3(b).The channel dimension of the CAO was investigated by FESEM, where the W and L of CAO channel layers were 0.859 mm and 100 μm, respectively, as shown in Fig. 3(c).The cross-section of the FESEM image of the fabricated CAO p-TFT is demonstrated in Fig. 4, where a 150 nm CAO layer serves as a channel layer and a 200 nm thick SiO 2 is used as the gate dielectric.

Results and discussions
3.1.Crystallinity evaluation of the LBL-deposited CAO XRD was conducted for structural investigation at different annealing temperatures (ranging from 600 °C to 990 °C).XRD patterns, shown in Fig. 5, provide valuable insights into the changes occurring within the film upon annealing.There was no discernible peak for the as-deposited CAO thin film.Annealing was made for qualitative improvement in the grown film. 25,26)At 600 °C, XRD peaks observed at 35.8°F ig. 4. Cross-section of FESEM image obtained from CAO grown on SiO 2 /Si substrate.Comparing the XRD pattern of the CAO film annealed at 990 °C with JCPDS No.00-040-1037, the hexagonal structure of CAO with space group P6 3 /mmc can be confirmed as shown in Fig. 6.However, the diffraction peaks that appear are limited to those c-axis oriented (004) and tilted from the c-axis (101) and (103).Moreover, the peak intensity ratio is changed compared to the powder diffraction, and the (004) diffraction peak becomes stronger.Here, the FWHM of (004), (101), and (103) are 0.0866°, 0.3464°, and 0.5196°, respectively.
Figure 7 shows rocking curves for the diffraction peaks of (004) and (101) to gain insights into the c-axis crystallization of the CAO film annealed at 990 °C.Remarkably, the (004) diffraction rocking curve showed a sharp peak with an FWHM of 0.057°overlapping on a constant background.In contrast, no such peak was detected for the (101) diffraction.The sharp peak on the (004) diffraction rocking curve indicates high orientation to the c-axis of CAO.We have speculated that there are two pathways for forming the CAO crystalline phase: phase transition from the CuO phase and direct formation from the LBL-deposited lattice.The former shows randomly oriented diffraction, such as the (101) diffraction and the constant background of (004) rocking curves.On the other hand, the latter exhibits a fine peak in the (004) rocking curve due to the c-axis-oriented LBL deposition.The smaller FWHM and the formation of the XRD rocking peak indicate the preferred orientation of CAO along the (004) direction.Therefore, the prominent background signal observed in the rocking curve X-ray diffraction indicates the coexistence of randomly and highly oriented crystalline planes at this elevated temperature.

Morphological analysis of the CAO thin films
The surface morphologies of the CAO thin films were examined using scanning electron microscopy (SEM), as illustrated in Fig. 8.The as-deposited CAO thin film exhibited an initial grain size of approximately 40 nm.Subsequent annealing of the samples at 990 °C facilitated the coalescence of smaller grains, forming larger grains with an increased size of about 150 nm.The augmentation in grain size is attributed to thermally activated processes such as grain growth and recrystallization during the annealing  035502-4 © 2024 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd treatment. 28)The reduction in the trapping sites of the grain boundaries is beneficial to the charge transport that helps to improve the mobility of the annealed CAO thin films. 29)

Stoichiometry of the CAO films deposited by DPDS
The confirmation of CuAlO 2 stoichiometry in the CAO films deposited on Si by DPDS was examined through an EPMA, wherein the Cu/Al ratio approached unity, confirming the targeted stoichiometric composition of the films.Furthermore, the utilization of a LBL approach was instrumental in maintaining homogeneity throughout the film thickness.Figure 9(a) illustrates the effectiveness of this method in preserving the desired stoichiometry, affirming the precision achieved through the deposition process.
Concerning the impact of annealing on stoichiometry, EPMA analysis was extended to include samples subjected to varying annealing temperatures.In Fig. 9(b), it is evident that the Cu/Al ratio remained almost the same despite changes in annealing conditions.In addition, there is no significant decrease in the oxygen molar fraction caused by the annealing.This observation suggests that the annealing temperature (600 °C-990 °C) did not adversely affect the stoichiometry of the CAO films.

TFT characteristics
The CAO TFT devices were evaluated using two characteristic curves: transfer (I ds versus V gs ) and output (I ds versus V ds ) curves, following conventional methods.035502-5 © 2024 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd negative bias to V gs , a capacitive injection of holes takes place at the interface of CAO/SiO 2 , subsequently modulating the I ds flowing between the source and drain electrodes.Note that the TFT characteristics are observed in the as-deposited sample, as shown in Fig. 11, despite the amorphous phase of CAO.The transfer curve for each sample is for V ds = −2 V, which is in the linear region of the output curve.The CAO TFT's threshold voltage (V th ) is an important parameter determined by a horizontal axis intercept of a linear extrapolation of the transfer curve. 31,32)V th for the highly oriented and as-deposited CAO TFT were −7.53 V and −9.0 V, respectively.In annealing, the thermal energy facilitates the healing of crystal defects, which minimizes the hole traps at the CAO/SiO 2 interface, 33) consequently reducing the V th in the higher annealing CAO TFT.The transfer characteristics also show an on/off ratio of 3 × 10 4 for the annealed sample and 6 × 10 2 for the as-deposited sample, respectively.The device has a width of 859 μm and a channel length of 100 μm, but there is no surface passivation.Therefore, it was speculated that the relatively high off current was due to the leakage current through the grain boundary and surface in such a wide channel.Moreover, the 200 nm thickness of the SiO 2 gate is enough to prevent gate leakage.The charge transfer to the gate should have actually occurred, but the gate current containing the leakage current could not be measured within the gate drive voltage range of the DC measurements.Therefore, we believe that the gate current does not significantly affect the drain current characteristics.
Due to the long channel length, the gradual channel approximation analysis was used to calculate the field-effect mobility of CAO layers from experimentally obtained TFT characteristics. 30)The field-effect mobility μ FE in the linear region can be estimated using differential transfer conductance ¶ ¶ I V ds gs following Eq.( 1).
where L and W are the length and width of the CAO channel layer, and C i is the areal capacitance of the gate oxide.C i has been estimated to be 1.73 × 10 −8 (F cm −2 ) from the thickness and the relative permittivity (ò r = 3.9) of SiO 2 .
On the other hand, the output curves shown in Figs.10(b) and 11(b) show the saturation of I ds clearly, and the saturated value (I ds sat ) depends on V gs , which are typical transistor characteristics.I ds decreases with V ds and then reaches I ds sat at V ds = V gs −V th .The value of I ds sat increases with V gs due to the channel carrier generation.I ds sat is obtained from the saturation region of the output curve and is expressed by the following Eq.( 2), μ FE depends on the gate voltage V gs because the depth profile of the accumulated carriers changes with the gate voltage.From Eq. ( 2), μ FE in the saturated region is expressed by  Also, the carrier concentration in the channel region exhibits a non-uniform distribution, as it accumulates near the semiconductor-insulator interface when V gs and V ds are applied.Here, the effective conductivity of the CAO channel layer is defined as σ, then I ds sat at V ds = V gs − V th can be expressed as, where t is the CAO thickness.The effective channel conductivity σ was estimated using Eq. ( 4) from the output curves.The extracted TFT properties from the characteristic curves have been tabulated in Table I.
The reported μ FE for the solution-processed CAO TFT after post-annealing is 0.1 21) to 1.36 cm 2 V −1 s −1 . 34)Meanwhile, the CAO TFT synthesized through magnetron sputtering exhibited a field-effect mobility of 0.97 cm 2 V −1 s −1 . 35)The directed formation of CAO via DPDS-assisted LBL deposition offers a unique advantage by creating an orderly atomic arrangement with superior electronic characteristics.The controlled and precise deposition process allows for the formation of a well-structured and defect-minimized CAO lattice.This structured lattice arrangement facilitates the efficient transport of charge carriers within the CAO film, which serves as an excellent foundation for TFTs.The well-structured lattice also seems responsible for transistor characteristics in the as-deposited CAO TFT; even in the amorphous phase, it exhibited mobility of 0.50 cm 2 V −1 s −1 , comparable to the solution processing followed by annealing.We expected the directional crystallization by LBL deposition and following thermal annealing.The LBL creates a wellordered CAO lattice, and the thermal treatment contributes to the further refinement of its crystalline structure and enhances the quality of the CAO film, bringing uniformity to the carrier path and enhancing hole transport. 36)The combined process positively influenced the TFT characteristics of the annealed CAO layer, improving the mobility of 4.1 cm 2 V −1 s −1 .The difference in mobility arising in the linear and in saturation regions is due to a notable contact resistance that a device experiences, contributing significantly to a discernible decrease in the effective V ds . 37)This mobility value is good, but we still believe it is restricted due to the persistence of a fraction of the CAO crystal planes retaining a random orientation.To achieve this coveted complete c-axis orientation of the CAO crystalline planes, further atomically precise control over the annealing conditions should be considered, which is expected to lead to an additional enhancement in mobility.
On the other hand, the conductivity of 0.19 × 10 −2 S cm −1 for the as-deposited and 1.8 × 10 −2 S cm −1 for annealed CAO TFTs at V gs = 20 V is relatively low despite the high mobility; this suggests a low carrier concentration.Due to the CAO/SiO 2 /Si configuration, it is fully depleted, making Hall measurement difficult at V gs = 0. Therefore, the carrier density was estimated from the effective conductivity and found to be on the order of 10 16 cm −3 .On the other hand, CAO films grown using the DC magnetron sputtering technique reveal a higher carrier concentration of 1.5 × 10 17 cm −3 along with a Hall mobility of 13.1 cm 2 V −1 s −1 . 38)No intentional p-type doping was carried out in this work.The origin of holes in Cu 2 O was reported to be the ionized Cu vacancies and ionized interstitial oxygen. 39)In the LBL process, oxidation is performed based on saturated oxygen adsorption, so increasing the ionized interstitial oxygen seems challenging.Improving the LBL process by controlling Cu vacancy and intentional doping is necessary.

Conclusion
CuAlO 2 having a dominance phase along the (004) plane was grown by DPDS under the LBL approach.C-axis oriented CAO thin film was obtained at an annealing temperature of 990 °C by carefully optimizing the deposition rates.The deposition process exhibited a consistent and uniform growth rate of 0.57 nm per cycle, as evidenced by the constant pulse voltage and plasma current profiles.Under such a process, CAO p-TFT was successfully fabricated.For the optimized CAO p-TFT, the threshold voltage of −7.53 V and field effect mobility of 4.1 cm 2 V −1 s −1 was recorded.Moreover, p-TFT properties and field-effect mobility comparable to the annealed CAO reported previously were observed in the as-deposited CAO films.We speculate that DPDS-assisted LBL for the controlled stacking is a good approach in the growth of CAO thin film and in implementing CAO as a channel layer for p-TFTs.

Table I .
Extracted TFT properties of TC and OC characteristics.
©2024The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd