A 4H-SiC p-channel insulated gate bipolar transistor with higher breakdown voltage and superior V F·C res figure of merit

A silicon carbide p-channel insulated gate bipolar transistor (IGBT) with higher breakdown voltage (BV) and low V F·C res figure of merit (FOM) has been simulated, fabricated, and characterized successfully. The proposed IGBT adds two n-type implant regions in the junction FET (JFET) area and increases the gate oxide thickness above the JFET area to reduce the reverse transfer capacitance (C res) and gate oxide electric field (E ox). The proposed structure notably lowers E ox below 3 MV cm−1 while elevating the BV to 16.6 kV. A new FOM of V F·C res is defined to evaluate the trade-off between the on-state and the C res characteristics. The experimental results demonstrate that a lower V F·C res FOM of 0.369 V·pF is achieved from the proposed IGBT with a reduction of 66.4%, compared to the conventional current spreading layer IGBT. Meanwhile, the simulated turn-on and turn-off times of the proposed IGBT are reduced by 29.4% and 20%, respectively.


Introduction
][3] In ultrahigh voltage applications (>10 kV), such as compact energy conversion and power grid systems, SiC insulated gate bipolar transistors (IGBTs) are favored over SiC MOSFETs due to their lower conduction losses in the conductivity-modulated drift layer.[6][7][8][9][10] Compared to n-channel IGBTs, p-channel IGBTs have garnered significant attention from various research groups due to their distinctive advantages.][13][14][15][16] In 2006, the first 5.8 kV 4H-SiC planar p-channel IGBT was reported, featuring a differential on-resistance of 570 mΩ cm 2 at 25 °C and a turn-off time of 750 ns. 17)In 2008, Zhang et al. demonstrated continuous improvement, achieving a breakdown voltage (BV) of 12 kV, with measured turn-on and turn-off times of 40 ns and approximately 2.8 μs, respectively. 18)][21] The dynamic behavior of a 16 kV 4H-SiC n-IGBT was also studied in detail. 22)][25][26][27] The dynamic characteristics are closely related to the capacitance of IGBT.In 2011, Praneet et al. reduced the gate capacitance by 50% while increasing the bipolar gain using a terrace gate IGBT. 28)A terrace gate structure has also been introduced into DMOS+ IGBT technology to improve the trade-off between the gate capacitance and threshold voltage. 29)It is also critical for ultrahigh voltage IGBT to reduce the electric field in the gate oxide to increase the long-term reliability of the device. 30)In 2023, Zhang et al. introduced a SiC-IGBT structure by adding floating P-islands in the n-type junction field-effect transistor (JFET) region to protect the gate oxide, showing a better static-dynamic trade-off. 31)lthough numerous research studies have delved into the static and dynamic characteristics of ultrahigh voltage IGBTs, several outstanding issues persist that must be addressed to enhance the performance of SiC IGBTs.A significant concern revolves around the trade-off between V F and C res .In this paper, a 4H-SiC p-channel IGBT structure with an elevated BV, reduced gate oxide electric field, and improved V F •C res figure of merit (FOM) is proposed and fabricated.The static and dynamic characteristics of the proposed structure are analyzed by numerical simulations and experiments.The simulation was briefly described in the previous study. 32)The results demonstrate the potential for achieving superior switching characteristics and an optimal trade-off property in the proposed structure.

Experimental methods
Figure 1 shows schematic cross-sections of the conventional current spreading layer (CSL) p-IGBT and the proposed p-IGBT structure.For the proposed p-IGBT structure, identical doping profiles and dimensional parameters are used except for the structure of the gate oxide and the JFET region.The fabrication process of the proposed p-IGBT is compatible with the conventional CSL p-IGBT.The epitaxial layers were grown on a 4-inch n-type 4H-SiC substrate.The conventional structure is based on our previous research work, 33) which utilized a 2 × 10 14 cm −3 doped, 100 μm thick p-type drift layer, and a 2.5 μm thick p-type buffer layer with a doping concentration of 1.5 × 10 17 cm −3 for the blocking requirement.In order to improve the on-state characteristics, a 1.5 μm thick p-type CSL with a doping concentration of 1 × 10 16 cm −3 is adopted.The width of the JFET region (L JFET ) is set to 7 μm.The channel length is about 1 μm.The cell pitch is 24 μm.The n-base and p+ emitter are formed by multiple ion implantations of nitrogen and aluminum, respectively.The two n-type implant regions in the JFET area with 2 μm width of the proposed structure are formed together with the n+ contact by multiple ion implantations of nitrogen.All the implants are activated at 1800 °C for 5 min after all implantations have been completed.The gate oxide thickness of the proposed IGBT structure is 60 nm at the channel region and is increased to 0.5 μm at the JFET region, while the gate oxide thickness of the conventional structure remains at 60 nm.The 0.5 μm thick oxide in the JFET region was formed together with the field oxide by plasma-enhanced chemical vapor deposition.The 60 nm gate oxide at the channel region is formed by dry thermal oxidation at 1300 °C and then annealed in nitric oxide (NO).The emitter and collector ohmic contacts are formed by Ti/Al and Ni, respectively.It is worth noting that the two n-type implant regions are short-connected to the emitter.This adds an additional extraction path for the electrons and reduces the turn-off time.During the manufacturing process, the thermal oxidation process was applied to enhance the lifetime.The average minority carrier lifetime before thermal oxidation of the wafer was measured to be 0.67 μs by photoconductance decay measurements (μ-PCD).After thermal oxidation at 1300 °C for 3 h, the average minority carrier lifetime of the wafer was increased to 1.298 μs, as given in Fig. 2.
The 2D simulations are performed using Silvaco TCAD.The physical models for the SiC device are employed, including the bandgap models, mobility models, Shockley-Read-Hall recombination, Auger recombination, carrier-dependent lifetime, and incomplete ionization models.To validate the effectiveness of the models used in our work, the forward current-voltage (I-V ) characteristics from the experimental results based on our fabricated 10 kV p-channel IGBT and the simulation results are compared, as given in Fig. 3. 34) The I-V characteristics of the same p-IGBT structure demonstrate a good fitting effect for the experimental and simulated results.In the simulation, the lifetimes of the electrons and holes are 1.2 μs and 0.1 μs, respectively.The active area is 4.2 × 4.2 mm2 .However, due to the defects of the SiC material, the yields of large-area chips fabricated in both structures are lower compared to small-area ones.In the experiment, a small active area chip was fabricated.Figure 4 shows a photograph of the top view of the fabricated IGBT.The fabricated IGBT has a chip size of 3 mm × 3 mm and an active area of 1 × 1 mm 2 .

Simulation results and discussion
The simulated breakdown characteristics and the off-state gate oxide electric field (E ox ) distributions are shown in Fig. 5.The proposed IGBT demonstrates a higher BV of  16.6 kV, while that of the conventional CSL IGBT is 15.6 kV.The electric field distribution of the two structures along the A-Aʹ cutline shown in Fig. 1 at a collector voltage of -15.6 kV is illustrated in Fig. 6.The electric field at the corners of the n-base/p-drift junction is 2.43 MV cm −1 for the conventional structure and 2.29 MV cm −1 for the proposed structure.The n-type regions connected to the emitter in the JFET area reduce field crowding at the corners of the junction, leading to a higher BV of the proposed IGBT.In addition, the long-term reliability under blocking conditions is very important, and can be evaluated by the E ox along the gate oxide in Fig. 1.As can be seen from the inset in Fig. 5, the maximum E ox is reduced from 4.4 MV cm −1 for the conventional CSL IGBT to 2.9 MV cm −1 for the proposed IGBT with a reduction of approximately 34%.Clearly, the E ox of the proposed IGBT is below 3 MV cm −1 , which is a widely accepted criterion for long-term gate oxide reliability. 35)he results indicate that the adoption of a thicker oxide layer and the introduction of n-type implant regions in the JFET area can effectively reduce the electric field of the oxide layer and corner of the n-base/p-drift junction.
Therefore, the device's long-time reliability is enhanced, and the blocking ability is also improved effectively.
Figure 7 shows the simulated on-state I-V characteristics of the two structures at room temperature.The forward voltage (V F ) drops of the conventional CSL IGBT and the proposed IGBT at an on-state current (I ce ) of −10 A are −5.5 V and −7.8 V, respectively.The V F of the proposed IGBT structure is relatively high due to the slightly lower minority carrier (electron) concentration at the top side.
The electron distributions along the vertical direction of the two structures at an I ce of −10 A are shown in Fig. 8.It is obvious that both IGBTs have extensive minority carriers injected into the drift region, resulting in a conductance modulation effect and a reduction of the on-resistance.However, compared with the conventional CSL IGBT, the electron concentration of the proposed IGBT structure is relatively lower because of the introduction of n-type implant regions connected to the emitter in the JFET area.But the proposed structure reduces the gate oxide electric field, mitigates the field crowding during avalanche breakdown,   For most application requirements, a lower C res is highly desired since it causes the Miller effect, which affects the device dV/dt capability.Figure 9 shows the simulated C res characteristics of the conventional CSL IGBT and the proposed IGBT.The C res of the proposed IGBT structure is much smaller than that of the conventional IGBT.When a collector voltage of −3 kV is applied, the C res of the proposed IGBT is 1 pF while that of the conventional IGBT is 3 pF.
Figure 10 depicts the hole distribution along the vertical direction of the proposed IGBT structure with a varied bias voltage applied between the collector and the emitter.As the bias voltage increases, the holes in the drift region are gradually depleted and the depletion region expands toward the substrate.The holes in the drift region are completely depleted until the bias voltage increases to approximately −2 kV.As is known, the C res is a series connection of the gate oxide capacitance and the depletion capacitance.When the emitter-collector bias voltage is small, C res is mainly related to the oxide capacitance.Compared to the conventional CSL IGBT, the oxide capacitance of the proposed IGBT is smaller due to the adoption of a thicker oxide layer.As the emitter-collector voltage increases, the depletion region extends, and the depletion capacitance gradually becomes smaller.Therefore, the depletion capacitance becomes the dominant part of the C res .Until the drift region is completely depleted, the C res remains as a depletion capacitance.For the same chip active area, the depletion capacitance of the proposed IGBT structure is smaller due to the introduction of n-type implant regions.Therefore, the proposed IGBT structure has a smaller C res capacitance.
The adoption of a thicker oxide layer of 0.5 μm and the introduction of n-type implant regions in the JFET area significantly improve the C res characteristics.To evaluate the trade-off performance, a new FOM of V F •C res is defined in this paper.According to the simulation results, the FOM of the proposed IGBT is only 7.8 V•pF, while that of the conventional IGBT is 16.5 V•pF, indicating a better trade-off between V F and C res being achieved for the proposed IGBT.
The turn-off and turn-on waveforms of the conventional CSL IGBT and the proposed IGBT structure are shown in Fig. 11.The switching behavior is assessed with a clamped inductive load simulation.A load inductance of 5 mH and a gate resistance of 10 Ω are used in the double-pulsed switching circuit.The switching time is defined by the time taken for the collector-emitter voltage to go from 90% to 10%. 24)It can be seen that the turn-on and turn-off time of the proposed IGBT are about 12 ns and 200 ns at −5 kV dc-link voltage while those of the conventional IGBT are about 17 ns and 250 ns.The turn-on and turn-off time of the proposed IGBT reduce by 29.4% and 20%, respectively.Obviously, a better switching time performance can be achieved for the proposed IGBT due to the lower C res .

Experimental results and discussion
Figure 12 shows the experimental breakdown characteristics of the two structures at room temperature.The IGBTs were tested with the gate grounded to the emitter and a high voltage applied to the collector using Agilent B1505A at a wafer-level chip.During the breakdown characteristic measurement, the devices were immersed in Fluorinert liquid to prevent arcing in air.The measured I ce of the proposed IGBT and the conventional CSL   02SP94-4 © 2024 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd IGBT is −6.5 nA and −9.0 nA at V ce of −8 kV, respectively.It can be seen that the leakage current of the two structures is lower than −10 nA at −8 kV without distinct breakdown behavior, and the breakdown characteristics of the proposed structure are slightly better.It should be noted that a higher BV (≥8 kV) is limited owing to the maximum equipment ability.
Figure 13 shows the experimental on-state I-V characteristics of the two structures.It is obvious that the I-V characteristics of the proposed IGBT have been degraded due to the two n-type implant regions in the JFET region.The V F of the conventional CSL IGBT and the proposed IGBT at an I ce of −500 mA are −5.5 V and −8.2 V, respectively.Figure 14 shows the experimental C res characteristics of the two structures.When a collector voltage of −3 kV is applied, the C res of the proposed IGBT is 45 fF while that of the conventional IGBT is 200 fF.
The on-state I-V characteristics and C res characteristics of the experiment are in good agreement with those of the simulation.The FOM of V F •C res of the proposed IGBT is only 0.369 V•pF, while that of the conventional IGBT is 1.1 V•pF.Compared to the conventional IGBT, the FOM of the proposed structure was reduced by 66.4%, indicating a better trade-off being achieved for the proposed IGBT.

Fig. 3 .
Fig.3.Simulated and experimental fitting results of forward I-V characteristics to validate the effectiveness of models.34)

Fig. 5 .
Fig. 5. Simulated breakdown characteristics and E ox curve of the conventional CSL IGBT and the proposed IGBT.

Fig. 9 .
Fig. 9. C res characteristics of the conventional IGBT and the proposed IGBT.

Fig. 10 .
Fig. 10.The hole distribution of the proposed IGBT along the vertical direction.

Fig. 12 .
Fig. 12. Experimental breakdown characteristics of conventional CSL IGBT and the proposed IGBT.

Fig. 13 .
Fig. 13.Experimental on-state I-V characteristics of the conventional CSL IGBT and the proposed IGBT.
In this article, a 4H-SiC p-IGBT structure with a higher BV and superior V F •C res FOM is proposed.The adoption of a thicker oxide layer of 0.5 μm and the introduction of n-type implant regions in the JFET area can greatly improve the main static and dynamic characteristics, including the BV, C res , and switching characteristics.In addition, E ox is effectively reduced to below 3 MV cm −1 , which enhances the reliability of the gate oxide and improves the BV to 16.6 kV by a 7% increase.Compared to the conventional IGBT, the measured C res is only 45 fF at a bias of −3 kV, corresponding to a reduction of 77.5%.Furthermore, a smaller measured FOM of V F •C res with a 66.4% reduction can be achieved owing to the structural advantages.The turn-on and turn-off time of the proposed structure are about 12 ns and 200 ns at −5 kV dc-link voltage, while that of the conventional IGBT are 17 ns and 250 ns.The turn-on and turn-off times of the proposed structure reduce by 29.4% and 20%, respectively, indicating a better switching characteristic of the proposed structure.

Fig. 14 .
Fig. 14.Experimental C res characteristics of the conventional CSL IGBT and the proposed IGBT by experiment.