Oxide-semiconductor channel ferroelectric field-effect transistors for high-density memory applications: 3D NAND operation and the potential impact of in-plane polarization

We have explored the 3D NAND memory operation of oxide-semiconductor (OS) channel ferroelectric FETs (FeFETs) by TCAD simulation with a multi-transistor NAND-string model. Key challenges in 3D NAND memory devices, such as (1) disturbance from pass voltages (V pass), (2) interference from neighboring wordlines, and (3) both the conventional and self-boost program inhibit operation of unselected bitlines, are addressed. For a target device structure, the operation voltages can be optimized to satisfy the requirement of (1)–(3). The stacking possibility of 3D NAND OS FeFETs is also predicted by conducting an extrapolation from the TCAD simulation results. We also studied the potential impact of in-plane polarization in the NAND FeFET string. A comparative study shows that in-plane polarization under the spacer may lead to unexpected characteristics of OS-channel FeFETs in 3D NAND memory operation. This paper will provide insights on the feasibility of 3D NAND FeFETs for high-capacity storage memory.


Introduction
][4][5][6][7][8] Advantages such as their CMOS process compatibility, low power consumption and fast writing speed make HfO 2 -based FeFETs a promising candidate for next-generation non-volatile memory devices. 9,10)To achieve higher integration density for storage-level applications, as well as controlling the variability and fabrication cost, like in the evolution of NAND Flash technology, 11,12) poly-Si channel 3D vertical FeFETs were proposed in 2017. 13)Compared with the conventional NAND Flash memory, FeFETs have a much faster write speed and better endurance when used as storage-level memory.Most importantly, because of the electric field-based switching of FeFETs, the power consumption can be much lower than the charge-based Flash memory.However, the challenges of voltage loss on the interfacial layer, reliability and low channel mobility remain to be solved.
To overcome these challenges, an oxide semiconductor (OS) channel vertical FeFET has been proposed with high mobility and an abrupt oxide-oxide interface between the FE-HfO 2 and the OS channel, as shown in Fig. 1 14) and recently demonstrated. 15,16)Nevertheless, voltage schemes used in a NAND memory array can be much more complicated than a single memory cell, which bring new challenges for NAND-type memory. 17)These challenges are becoming critical with the scaling of memory cells and spacer length, and have been widely studied in the field of NAND Flash. 18,19)To realize array operation of FeFET, memory operation in the NAND-string structure needs to be studied 20) and has not been fully reported yet.Most of the previous research was based on single device measurement or a planar structure, 21,22) and the interplay between memory cells was ignored.Moreover, the special writing characteristics of OS FeFET make the NAND operation more complicated.
To explore the physical reason for the interplay between cells and provide a guideline for device design optimization, the NAND operation of OS FeFETs needs to be investigated based on a device model similar to the target fabricated device structure.In addition, we previously reported the existence of an in-plane polar phase, 23) which may influence the 3D NAND FeFET memory characteristics.
In this paper, we study the 3D NAND memory operation of OS-channel FeFETs with a multi-transistor NAND-string model using TCAD simulation.The operation voltages are optimized to satisfy the requirement from pass voltage disturbance, interference and program inhibit operation.The stacking possibility of NAND OS FeFETs is predicted theoretically by conducting an extrapolation from the TCAD simulation results, from the perspectives of read speed and sensing ability.We also study the impact of inplane polarization under the spacer of 3D NAND FeFETs.This paper is an extended version of the previous conference proceedings, 24) with new exploration of the self-boost program inhibit operation and the prediction of stacking possibility.

Simulation methods
The ferroelectric model used in this paper has been presented in our previous work. 25)The static ferroelectric polarizationvoltage (P-V ) loop is described by the Miller model.To reproduce the minor loops of ferroelectric switching, the turning point method is used in this model.The ferroelectric model of HZO was fitted with experimental data in our past work. 26)We previously reported the memory device operation of a single 3D structure OS FeFET using TCAD simulation. 27)The single device model is extended to a series-connected five-transistor model, which consists of three FeFETs and two selectors (Ground select line and string select line, hereinafter called "GSL" and "SSL").As shown in Fig. 2, 3D vertical-channel FeFETs have a macaroni structure with SiO 2 filler inside.Amorphous In-Ga-Zn-O (IGZO) is chosen as the channel material, with ideal material properties.The bandgap of IGZO is 3.2 eV.The devices are junctionless transistors, and the source and drain are ohmic contacts.The high-field saturation model is applied to describe the carrier mobility.The target device parameters in this study are summarized in Table I.We focus on the device characteristics of T2, which is the central cell of the string, while operation voltages are applied to T1 and T3 in different operation modes.In this study, only the static ferroelectric property is considered for simplicity and, thus, DC voltages are used in the simulation.We define the erase (ERS) operation by applying positive voltage on a wordline (WL) to realize a low V th as the ERS state, and program (PRG) operation by applying negative voltage on the WL to realize high V th as the PRG state.Note that this definition is opposite from the conventional definition in FeFETs. 28)n the write operation, first, 5 V is applied to the WL to initialize all cells to the same ERS state with low V th , corresponding to the block erase in NAND Flash.Then, −5 V is applied to the WL of a target WL to write the cell to PRG state with high V th .The write operation is executed in the order of T1, T2 and then T3, from the ground line to the bitline (BL).A BL voltage of 0.3 V is used as the drain voltage for the read operation unless otherwise mentioned.The sensing margin is evaluated by the memory window (MW) and current ratio.The MW is defined as the V th difference between the ERS state and the PRG state when the drain current is 100 nA, while the current ratio is defined as the ERS state current to the PRG state current when the gate voltage of T2 is 0 V.Only out-of-plane polarization is considered unless otherwise mentioned.In this study, we only consider 1 bit memory operation per cell, while it can be extended to multi-bit operation.

Disturbance from pass voltage
A certain positive pass voltage (V pass ) is necessary for driving the unselected cells during the write or read operation in NAND memory array, regardless of the states of the written memory cells.A negative voltage is used to write the cells into the PRG state by flipping the polarization in this device.Thus, a positive V pass may disturb the PRG state.The waveform used for the disturbance study is shown in Fig. 3(a).A selected cell is programmed by −5 V and returns to V pass , then the PRG state after disturbance is read out. Figure 3(b) shows the simulated I d -V g curves at different V pass from 0.8 V to 1.5 V.The PRG state I d -V g curves are shifted to the left after the disturbance.This is because the polarization of the written PRG state is partially flipped by applying a positive V pass .After writing PRG, a specific amount of positive charge is obtained at the target cell.When a positive V pass is applied to the written cell, the PRG polarization charge at the written cell follows the P-V loop.As V pass becomes larger, the positive polarization charge decreases firstly, and is finally flipped to a negative charge when V pass is large enough.It results in V pass disturbance and left-shifting of the PRG state I d -V g curves.
In the next step, the current ratio and read current are extracted in the worst sensing case, in which neighboring cells T1 and T3 are written into PRG (high V th ) state.As shown in Fig. 4, V pass has an optimal range for a good sensing margin.A smaller V pass can suppress the pass voltage disturbance, leading to a lower string current when T2 is in the PRG state.A larger V pass is necessary to increase the conductivity of unselected cells and prevent a significant decrease of the string current, which leads to a higher string current when T2 is in the ERS state.A larger V pass can also increase the read current of the string, which is important from the read speed perspective.Therefore, to take the balance, 1.0 V can be chosen as the V pass of the target structure for a high sensing margin (target ratio > 10k) as well as a good read speed.

Interference from neighboring WLs
The characteristics of a target cell can be interfered by the writing progress of neighboring cells, especially when the gate length (L g ) and spacer length (L s ) are scaled   dimensionally.In this part, the characteristics of T2 are discussed as a victim cell after writing T3.The waveform used for interference simulation is shown in Fig. 5(a).After initialization by the block erase operation, all memory cells are written to the PRG (high V th ) state one by one, then T2 is read out.Notice that the target cell T2 returns to V pass before the reading.Not only the interference, but also the disturbance from V pass is included in the readout characteristics.As shown in Fig. 5(b), the PRG state I d -V g curve of T2 is shifted after writing T3 by the interference.
To give more details on the interference from neighboring WLs, the polarization charge distribution before and after writing T3 is extracted and compared in Fig. 6(a).The asymmetric polarization distribution on the source and drain side of T2 indicates that the shift of the I d -V g curve is not only due to the disturbance from V pass , but also the interference from the writing operation of T3.The polarization of T2 near T3 is flipped by writing T3 to the PRG state, which is because of the electrostatic coupling between the WLs of T2 and T3.Because of the floating body, the electric potential difference between the WL of T3 and the channel is smaller than the potential difference between the WLs of T2 and T3 when T3 is being programmed, and the horizontal electric field between T2 and T3 is not negligible.It results in a strong coupling field between the WLs of T2 and T3, which is the reason for the mentioned interference.Fig. 4. PRG/ERS current ratio and read current versus V pass .A large ratio can be obtained in a certain range, while a larger V pass is desired for higher read current.
(a) (b) (a) As the writing process of T3 is believed to be the origin of interference, the V th shift of T2 and MW at different write voltages in T3 are shown in Fig. 6(b).Although the interference can be suppressed by using a weaker write voltage, a stronger write voltage is still desired for a larger MW, even though the interference is taken into consideration.Therefore, −5 V can be chosen as the PRG voltage.

Program inhibit mode of unselected BLs
In the NAND array, an unselected string must be prevented from being written by using inhibit mode, and program disturbance may be introduced to unselected cells.The conventional inhibition method in NAND memory is to propagate a high potential (low potential in this work) to the selected WL to decrease the potential difference between the gate and channel.The waveform used for the conventional inhibit mode is shown in Fig. 7(a).GSL is closed and a low channel potential is achieved by applying a negative bias on the BL of the unselected string, while V pass is applied to unselected WLs.The potential distribution in the unselected string in the inhibit mode is extracted in Fig. 7(b).The low potential is successfully propagated to T2 on the selected WL (page).Figure 7(c) shows the I d -V g curves at different BL inhibition voltages.The channel potential under inhibit mode follows the BL potential.By using a negatively larger BL inhibition voltage, the channel potential becomes lower.Since the PRG voltage is fixed at −5 V, the voltage that crosses the gate stack is smaller when the BL voltage decreases.The weak electric field in the HZO layer cannot

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© 2024 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd flip the written ERS polarization even when PRG voltage is applied to the gate electrode.The V th shift is suppressed for T2 in the ERS state in the unselected BL by the negative inhibit BL voltage.
In advance NAND Flash memory, instead of the conventional inhibit mode, the self-boost inhibit mode is used. 29)We also explored the possibility of using the self-boost program inhibit mode in NAND OS FeFET.A −3 V or −4 V voltage is applied to the SSL after the inhibit BL voltage is applied.The string is closed and the channel potential is floating before the writing progress.Figure 8 shows the MW versus BL voltage under both conventional and self-boost inhibition operation.The MW increases rapidly as the BL voltage becomes negatively large.The self-boost inhibit is more effective than the conventional method when the BL voltage is weak.Notice that the MW has a relationship with the gate voltage of SSL in the self-boost inhibit mode.This is because the impact of electric coupling from the gate of SSL can be obvious when the string is very short (only five cells in this model).In conclusion, a BL voltage negatively stronger than −3 V is necessary for effective inhibition operation in this device.

Prediction of stacking possibility
The high-level stacking is important for higher integration density in 3D NAND memory.It is reported that over 100 layers of memory cells can be integrated in NAND Flash technology nowadays. 30)However, the string current of NAND memory will decrease when the string is longer, which leads to a potential read failure.Due to the amorphous characteristics of the OS channel, the mobility of OS FeFETs is still limited.
To predict the stacking possibility, the mentioned 5 T model is further extended to 7 T and 9 T models with more memory cells.The characteristics of the central cell are always focused during the simulation.The read current and current ratio in the worst sensing case, in which all unselected cells are in high V th states, are extracted at different V pass .A BL voltage of 1.0 V is used during the read operation.
Figure 9(a) shows the I d -V g curves of the 5 T, 7 T and 9 T models under 1.0 V V pass .The string current decreases obviously with more transistors.Figure 9(b) shows the extracted read currents of the 5 T, 7 T and 9 T models at different V pass .The read current is extracted when all gate voltages are equal to V pass .With a longer memory string, the parasitic resistance of unselected cells increases when the cells are in high V th states.A linear extrapolation is conducted to predict the current level with more transistors.Note that the read current should show a saturation trend when the current is small enough, which is ignored in the prediction.As shown in Fig. 9(b), the read current is improved by using a larger V pass , especially in long strings.In current ratio prediction, both the PRG and ERS state current decrease with a longer string, making it difficult to predict the current ratio with only a few memory cells.To give the worst condition, the current level of the ERS state is fixed at 5 T (largest ERS state current) when calculating the current ratio, while the current of the PRG state is extracted from the simulation results of the 5 T, 7 T and 9 T models.As shown in Fig. 9(c), the current ratio decreases a lot when V pass is too large.Overall, the trade-off relationship between the current ratio and read current mentioned in the disturbance simulation still remains in a long string.Table II shows the possible stacking level with different limit factors.When V pass is 1.0 V, the number of stacking layers is limited to 19 by the low read current.When V pass is 1.2 V or 1.5 V, the number of stacking layers is limited to 42 and 34 by the degradation of the current ratio.The number of stacking layers can be improved by increasing the MW using a thicker FE-HfO 2 layer and interfacial layer engineering.Now that all the NAND memory operation is applicable to OS-channel FeFETs,  NAND OS FeFET is promising for low power consumption and fast write speed.Compared with other simulation works based on poly-Si channel NAND FeFETs, 31) the current ratio and read current are both improved in this work.By using a larger drain voltage for read operation (1 V), the read current is improved in the worst sensing case, even at a smaller V pass .The current ratio in OS FeFETs is obviously larger than in poly-Si channel devices under the same low write voltage (4 V or 5 V).During the ERS operation, the voltage drops more on the HZO layer in the OS FeFET compared to a poly-Si device, which has a low-k interfacial layer, resulting in more effective ferroelectric switching.An enhancement in mobility of the OS channel 32) and FE material with a larger polarization charge 33) is expected to improve the critical trade-off among the operation schemes.

Impact of in-plane polarization
In the discussions above, the device operation was studied only with out-of-plane polarization in the FE-HfO 2 layer to the channel, which is the ideal case that all polarization charge can be flipped only in the out-of-plane direction by the gate bias.However, there is a possibility that in-plane polarization exists, particularly under the spacer region.A comparative simulation using the 5 T model that includes inplane polarization is conducted.The voltage scheme of the interference study, in which all memory cells are programmed one by one, is used to explain the impact of inplane polarization.
As shown in Fig. 10, the PRG state V th of T2 shows an opposite shift after writing T3 with and without in-plane polarization.While the PRG state V th of T2 becomes lower without in-plane polarization, which is also seen in Fig. 5(b), it becomes higher with in-plane polarization.The potential distribution after writing T3 is extracted with and without inplane polarization under the spacer at T2 WL voltage of 0 V as shown in Fig. 11(a).Without in-plane polarization, the electrostatic potential on the drain side of T2 is higher because of the interference from T3, but it is lower than expected with in-plane polarization, even though the same write operation is used.
The lateral polarization component is extracted in Fig. 11  © 2024 The Author(s).Published on behalf of The Japan Society of Applied Physics by IOP Publishing Ltd of-plane polarization near the drain of T2 but also induces inplane polarization under the spacer between T2 WL and T3 WL.The potential near the drain side of T2 is decided by the in-plane polarization charge under the spacer between T2 and T3, the out-of-plane polarization charge, and the gate voltage bias.The in-plane polarization charge is relatively stronger than the out-of-plane polarization charge flipped by writing T3, and dominates the potential distribution near the drain side of T2 [See Fig. 11(c)], which induces fewer carriers (electrons here) in the channel of T2.Since the number of carriers decreases at the drain side of T2, the whole channel current of T2 is limited, leading to a positive shift of the PRG state V th of T2 in Fig. 10.Notice that although the MW is increased in the interference scenario after in-plane polarization is included, the MW is degraded in other writing operations.The impact of in-plane polarization under the spacer has not been experimentally confirmed yet, and experimental validation is desired.However, it will complicate the device design of 3D NAND FeFETs and should be carefully considered.

Conclusions
3D NAND memory operation is explored for OS-channel FeFETs by TCAD simulation with a multi-transistor model.We systematically provided the dependence of the MW and operation voltages, and found the optimum voltages that satisfy the requirement of disturbance, interference and inhibit mode.NAND array operation is applicable but the critical trade-off between the sensing ability and read speed may limit the possible stacking level of OS-channel FeFETs, which needs to be further improved.In-plane polarization largely influences the polarization and potential distribution, and thus complicates the 3D NAND FeFET design; this should be carefully considered.

Fig. 2 .
Fig.2.Five-transistor model that consists of target cell T2, its neighbor cells and selectors.3D device structure is shown.

Fig. 5 .
Fig. 5. (a) Waveform used for interference from the neighbor cells.T2 is read out after writing T3.(b) Simulated I d -V g curves of T2 before/after writing T3.PRG state of T2 is shifted left (V th decrease).

Fig. 3 . 3 ©
Fig. 3. (a) Waveform used for V pass disturbance simulation, T2 is read out after writing T2 and V pass disturbance.(b) Simulated I d -V g curves at different V pass .PRG state V th is lowered by V pass disturbance.

Fig. 6 .
Fig. 6.(a) Polarization charge distribution before (upper)/after (lower) writing T3.Polarization of T2 near T3 is partially flipped.(b) V th shift and MW at different write voltages.Interference is weaker at low voltage but MW is larger at large voltages.

Fig. 7 .
Fig. 7. (a) Waveform used for inhibit mode.GSL is closed, and then negative bias is applied on BL, and T2 is read out after inhibition.(b) Potential distribution in inhibit mode.(c) Simulated I d -V g curves at different BL voltage.ERS state V th shift becomes smaller with stronger inhibition voltage.

Fig. 8 .
Fig. 8. MW versus BL voltage.MW is larger with stronger BL inhibition bias.MW is in self-boost inhibit mode at same BL bias.Inhibition becomes effective when BL inhibition voltage is lower than −3 V.

Fig. 9 .
Fig. 9. (a) Simulated I d -V g curves of worst sensing case in 5 T, 7 T and 9 T models.Extracted and extrapolation of (b) read current and (c) current ratio at different V pass from TCAD simulation results.The trade-off relationship between read current and current ratio is same as in 5 T model even in long string.

Fig. 11 .
Fig. 11.(a) Potential distributions of (upper) without and (lower) with in-plane polarization under the spacer.(b) In-plane polarization distribution after writing T3.(c) Schematic of the impact and physical reason.

Table I .
Simulation parameters.

Table II .
Possible stacking level.