Enhancement-mode vertical (100) β-Ga2O3 FinFETs with an average breakdown strength of 2.7 MV cm−1

In this work, we report on the realization of vertical (100) β-Ga2O3 FinFET devices for the use in power electronics applications. The experiments are carried out on structures consisting of highly conducting (100) β-Ga2O3 substrates with a doping concentration N D of 3 × 1018 cm−3, and epitaxially grown layers with N D of 5 × 1016 cm−3 for the drift and channel region. The fabricated FinFET devices feature enhancement-mode properties with a threshold voltage of +4.2 V and on/off-current ratio of 105. Moreover, breakdown measurements of these devices reveal an average breakdown strength of 2.7 MV cm−1. Additional device simulation indicates the presence of electric field peaks near the gate edge outside the active device as high as 7 and 5 MV cm−1 in the Al2O3 gate oxide and β-Ga2O3 semiconductor, respectively.


Introduction
The semiconductor β-Ga 2 O 3 with an ultra-wide bandgap of around 4.8 eV has gained significant interest in recent years for the application in next-generation power electronic devices. The estimated high breakdown strength of 8 MV cm −1 and the resulting high Baliga's figure of merit of >3000 indicates that much more compact and therefore efficient power converters can be realized with this material compared to more established technologies using SiC and GaN. 1,2) Up to now impressive performances of lateral β-Ga 2 O 3 power transistor devices have been demonstrated featuring an average breakdown strength as high as 5.5 MV cm −1 3) and record breakdown voltages up to 8.03 kV. 4) Moreover, the power figure of merit is steadily increasing and almost surpasses a value of 1 GW cm −2 5) due to continuous material quality improvements and device optimizations. However, in order to use the full potential of the material properties of β-Ga 2 O 3 for high voltage/high-current applications, a vertical device structure is preferred over a lateral structure for active devices as widely demonstrated for vertical Schottky barrier diodes (SBD) based on β-Ga 2 O 3 . [6][7][8] Here, the main advantages include lower chip area requirement at high voltage levels, ideal separation of high voltage potentials, improved reliability, and thermal performance as well as the possibility of reaching higher current levels. 9) In the past years promising results have been obtained by the realization of vertical FinFET devices based on homoepitaxial β-Ga 2 O 3 wafers in the (001) orientation. [10][11][12][13] Through the use of an optimized postdeposition annealing step low R on,sp of 25.2 mΩ•cm 2 and a record-high breakdown voltage of 2.66 kV was achieved resulting in a power figure of merit of 280 MW cm −2 . 14) More importantly, due to the double gating of the channel at each fin structure this topology allows strong electrostatic gate control enabling enhancement-mode operation making the vertical FinFET structure very attractive for future highpower electronic applications.
In this work, we report on the fabrication of vertical β-Ga 2 O 3 FinFET devices based on homoepitaxial wafers in the (100) orientation. Up to now, there is no clear evidence on the optimum orientation of β-Ga 2 O 3 for lateral or vertical electronic devices. However, the (100) orientation represents the lowest surface-energy cleavage plane of β-Ga 2 O 3 and as a result, smooth, defect-free films can be epitaxially grown on it without faceting-albeit on offcut substrates to prevent twinning. 15,16) It is therefore expected that the improved material quality will have a beneficial impact on the device performance of vertical FinFETs. Furthermore, it is less challenging to realize good ohmic contacts by using the (100) orientation in comparison to (010) which makes the fabrication process much simpler. 17) Finally, electrical characterization of the vertical (100) β-Ga 2 O 3 FinFET devices reveals enhancement-mode properties and high voltage blocking capabilities with an average drift zone breakdown strength of 2.7 MV cm −1 . Furthermore, we analyze the electric field distribution inside the FinFET using TCAD simulations which suggest the origin of the breakdown at the edge of the device.
Before film growth, polished substrates were first etched in phosphoric acid (H 3 PO 4 , 85%) at 140°C for 15 min to remove the polishing damage and then annealed in an oxygen atmosphere at 900°C for 1 h to promote a terraced surface structure. Such annealing does not affect the electrical resistivity of the substrates. 18) The MOVPE system used in this work is a vertical showerhead reactor (Structured Materials Industries, Inc. -USA) equipped with a rotating susceptor. Triethylgallium (TEGa) was used as the metalorganic precursor for Ga, while O 2 (5 N) was used as the oxidant, and high-purity Ar (5 N) acted as the carrier gas. The growth temperature was fixed at 800°C with the chamber pressure kept at 25 mbar. The Ar flow rate through the chamber was constant at 4200 sccm. The TEGa molar flow rate is fixed at 60 sccm, and the oxygen molar flow rate is fixed at 165 sccm. The resulting growth rate is about 0.6 μm h −1 . More details on the growth conditions are reported elsewhere. 20) The double-layer structure was grown in one run. The drift layer was first grown without any intentional doping, followed by a 15 min break by switching off the Ga precursor and the capping layer was grown afterwards by increasing the TEOS flow rate to 20 sccm in order to realize highly Si-doped Ga 2 O 3 for improving ohmic contact to the source electrode.
Device processing started with the deposition of Ti/Pt (20 nm/130 nm) source contacts by evaporation which were structured by e-beam lithography defining the fin size of ∼220 nm. Subsequently, the fins with a height of 600 nm were realized using a BCl 3 /Ar-based inductively coupled plasma (ICP) etch process. Then, a 30 nm Al 2 O 3 gate dielectric was deposited by thermal atomic layer deposition at 300°C followed by sputtering of the TiW gate metal with a thickness of 150 nm. Formation of the contact pads and the realization of the device isolation was carried out by structuring the TiW gate metal in an SF 6 -based ICP etch step. An additional SiN x layer was deposited by plasmaenhanced chemical vapor deposition (PECVD) for passivation purposes. Then, a photoresist planarization/etchback process was used to structure the TiW gate metallization using H 2 O 2 as the etchant. Afterward, a 200 nm SiN x spacer was deposited by PECVD and a second photoresist planarization/etchback process was used to selectively etch away the SiN x /Al 2 O 3 on top of the Ti/Pt source contacts. Finally, the source interconnection and contact pads are formed by evaporating Ti/Au (20 nm/130 nm). The complete process flow of the FinFET fabrication is shown in Fig. 1. The final multi-fin device consists of 9 fins with a length of 10 μm and a pitch of 1.2 μm shaping a total device area of around 100 μm 2 . Figure 2(a) shows the device schematic and Fig. 2(b) a representative crosssection. As can be seen in the cross-section the final fin structures have a trapezoidal shape with a fin width of 230 nm at the top and 320 nm at the bottom resulting in an edge steepness of >85°.

Results and discussion
Prior to device fabrication, the epitaxial layers were characterized by atomic force microscopy (AFM). As shown in Fig. 3, the desired step-flow morphology along the [001] direction can be observed with a root-mean-square surface roughness below 0.5 nm.
Electrical characterization of the vertical β-Ga 2 O 3 FinFET devices was carried out by transfer and output characteristics measurements as shown in Fig. 4. The drain current was normalized to the actual device area of 100 μm 2 due to the fact that the drift layer is quite thin and the impact of current spreading on the increase of the effective area is negligible. 14) The transfer characteristic clearly demonstrates decent device functionality with proper modulation of the drain current featuring an on/off current ratio of around 10 5 . Furthermore, the threshold voltage which was extracted by extrapolating the value of the x-intercept of a fit to the linear I D -V G plot of the forward sweep is around +4.2 V emphasizing normally-off properties of the device. In addition, off-currents are very low which are in the range of the lower measurement limit of our measurement equipment used for the electrical characterization. However, significant clockwise hysteresis is observed indicating trapping of charge carriers in semiconductor/ dielectric interface defect states. 21) This is most likely due to the fact that no etch damage removal step was carried out after the fin realization using BCl 3 -based plasma etching which may leave a lot of such defect states at the Ga 2 O 3 /Al 2 O 3 interface after deposition of the gate oxide. In addition, the output curve shows similar hysteresis effects and no saturation regime indicating a highly resistive contribution inside the device which could also originate from the reduced dielectric/semiconductor interface quality. Various approaches have been investigated recently in order to remove plasma etch damages in Ga 2 O 3 -based devices such as thermal treatments 22,23) or wet chemical treatments in H 3 PO 4 , TMAH or HF. [24][25][26] We believe that such treatments will lead to a significant reduction of the transfer curve hysteresis as well as enhancement of the on/off current ratio. Another explanation for the poor performance of the device could be also related to increased ohmic contact resistances. Although the source and drain contacts are formed on highly doped β-Ga 2 O 3 in the (100) orientation which should in general result in low contact resistances as verified by our group and others 17,27) we cannot fully exclude that the BCl 3 /Ar-based etch process used for the realization of the fin structures could have led to the degradation of the ohmic properties of the source contact.
Nevertheless, three-terminal off-state breakdown measurements of the vertical β-Ga 2 O 3 FinFET were carried out at room temperature and in ambient air. The gate and drain leakage currents measured at V G = 0 V are presented in Fig. 5 showing an abrupt and catastrophic breakdown of the device at 260 V. Considering the fact that the drift layer of the device has a thickness of around 950 nm, this breakdown voltage corresponds to an average breakdown strength of around 2.7 MV cm −1 . This value is already much higher than what was previously demonstrated on lateral (100) β-Ga 2 O 3 MOSFETs 27,28) which emphasizes the high quality of the epitaxial β-Ga 2 O 3 layers.
In order to analyze the electric field distribution inside the vertical FinFET device TCAD analyses using Silvaco ATLAS were carried out. For the simulation, the device structure and doping concentrations were set to be the same as in the fabricated devices. Figure 6 shows the electric field distribution in off-state mode at V G = 0 V and V DS = 260 V.
As can be seen the main electric field peak evolves outside of the fin structures near the gate edge. More importantly, the field peak reaches values of around 7 MV cm −1 and 5 MV cm −1 inside the Al 2 O 3 gate oxide and β-Ga 2 O 3 , respectively.
However, it should be noted that the value of 7 MV cm −1 in the gate oxide is already much higher than the dielectric strength of our ALD-derived Al 2 O 3 which is typically in the range of 5-6 MV cm −1 as measured in vertical capacitors. This implies that the overall device breakdown could also be attributed to the breakdown of the gate oxide at the edge of the active device area and that the limit of the dielectric strength of β-Ga 2 O 3 has not been reached, yet. Further investigations are needed to verify this assumption. Nevertheless, these investigations emphasize that the realization of additional edge termination structures are mandatory   in order to improve the electric field distribution in the edge region and reduce those field peaks. Several approaches can be followed to achieve this as previously demonstrated with vertical SBDs such as mesa structuring, 29,30) ion implantation 31,32) or additional deposition of p-type guard rings. 33,34)

Conclusions
In this work, we demonstrated for the first time the successful realization of vertical FinFET devices on epitaxial β-Ga 2 O 3 wafers in the (100) orientation. The devices featured enhancement-mode properties with a threshold voltage of +4.2 V and on/off current ratios of 10 5 . However, increased hysteresis effects are observed as well as non-saturating output characteristics which can be attributed to reduced interface quality between the semiconductor and the gate oxide. Nevertheless, breakdown measurements showed decent blocking properties with an average breakdown strength of 2.7 MV cm −1 . Additional device simulation revealed high electric field peaks at the device edge with values of 7 MV cm −1 and 5 MV cm −1 inside the Al 2 O 3 gate oxide and β-Ga 2 O 3 semiconductor, respectively.

Acknowledgments
The authors would like to thank their colleagues in the process department at FBH for process technological support. Furthermore, the authors are grateful to Andreas Fielder and Palvan Seyidov from IKZ for insightful and fruitful discussions on Ga 2 O 3 related topics as well as Paul Plate and Jakob Zessin from SENTECH Instruments GmbH for realizing the ALD-derived gate oxide. This work was performed in the framework of GraFOx, a Leibniz-ScienceCampus partially funded by the Leibniz association.