Accurate evaluation of interface trap density at InAs MOS interfaces by using C–V curves at low temperatures

InAs has attracted considerable attention as a channel material for advanced MOSFETs with high-k gate insulators because of its superior electron transport properties. ^1–7) InAs is also promising for photodiodes (PDs) in the near-infrared region because of its narrow band gap, superior avalanche multiplication gain, and low excess noise. ^8–11) However, the InAs MOS channel has the problem of high interface trap density (D_it) at high-k/InAs interfaces, ^12–19) which significantly degrades the performance of MOSFETs and PDs, such as reliability, drive current, dark current, and subthreshold swing. Therefore, a fabrication method to reduce the high D_it is required, indicating the importance of the accurate evaluation of D_it values. However, there are challenges in the accurate evaluation of D_it at InAs MOS interfaces, including many interface traps with a wide range of time constants, as shown in Fig. 1. First, there are many fast interface traps because the narrow band gap of 0.36 eV causes fast thermal generation and recombination of carriers between interface traps and bands. ^12,13) Second, there are many slow traps, resulting in the large hysteresis of capacitance-voltage (C–V) measurements owing to border traps in the oxides. ^12,13,16,18) The coexistence of considerable fast and slow traps makes it difficult to apply the conductance method to InAs MOS interfaces. ¹²⁾ Therefore, the Terman method is suitable for the accurate evaluation of D_it, which is based on C–V curves under the high-frequency limit. The Terman method determines D_it by comparing the experimental C–V curve under the high-frequency limit and the theoretical ideal C–V curve without D_it. ²⁰⁾ However, guidelines on how to apply the Terman method to InAs MOS interfaces remain unclear. Thus, the measurement method used to obtain C–V curves under the high-frequency limit, and the calculation method of the ideal C–V curve should be clarified for InAs.

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Therefore, in this study, the C–V curves were obtained under the high-frequency limit by performing measurements at low temperatures to slow down the thermal generation and recombination of the interface states. While it has been reported that the high-frequency limit cannot be obtained at 140–180 K, ^12,13) there are still no detailed reports on the impact of measurement temperatures on C–V characteristics of InAs MOS capacitors, and the D_it evaluation using the Terman method. In this work, we examine the temperature at which the high-frequency limit can be obtained by systematically changing the measurement temperatures down to significantly lower temperatures of 31 K. Additionally, we have clarified that the response of slow traps can be suppressed by limiting the sweeping range of the gate voltage, resulting in the negligible impact of slow traps on the D_it evaluation.

Furthermore, we studied issues regarding the validity of the theoretical C–V curves: (1) the influence of the accuracy of the estimated oxide capacitance (C_OX), and (2) the choice of the Fermi–Dirac or Boltzmann distribution, which can be critical to the accurate evaluation of D_it at low temperatures using the high-frequency C–V method. For issue (1), the value of C_OX used to calculate the theoretical C–V curve can be determined by fitting the experimental C–V curve in the accumulation region. However, it is difficult to determine the semiconductor capacitance (C_s) of InAs in the accumulation region from experiments because of the high interface trap capacitance, as shown in Fig. 2. ^15,21–24) The ideal C_s of InAs without D_it is considerably low because of the significantly low density of states (DOS), ^2,24–26) while the real C_s of InAs can be significantly high owing to many interface traps. ^21–24) The difference between ideal and real C_s makes it difficult to determine C_OX experimentally. Therefore, it is necessary to discuss the impact of the accuracy of C_OX estimation on D_it evaluated by the Terman method.

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For issue (2), the Fermi level tends to be located inside the conduction band at low temperatures for InAs because of the considerably low DOS of electrons. ^19,24) Therefore, the Boltzmann distribution should be inaccurate for simulating electron concentrations in the InAs band structure, while the Boltzmann distribution is used to simplify the calculation. Therefore, in this study, the impact of the choice of the distribution function on D_it evaluated by the Terman method was examined. In comparison with the published abstract, ²⁷⁾ new simulation results considering the quantum effect on the two-dimensional electron gas (2DEG) in the accumulation region and in-depth discussions on the accuracy of D_it evaluation have been added in this study.

The process flow of the n-type InAs MOS capacitors is shown in Fig. 3. First, the unintentionally doped (100) InAs substrate was cleaned with acetone for 1 min, followed by BHF cleaning to remove the native oxide. ¹²⁾ Thereafter, the (NH₄)₂S_y solution was used to passivate the InAs surface by sulfur atoms. ²⁸⁾ The soaking times of the substrates in the BHF and (NH₄)₂S_y solutions were 15 s and 5 min, respectively. The concentrations of BHF and (NH₄)S_y in water were 22% and 0.6%–1%, respectively. The cleaning was performed at room temperature (R.T.). After each treatment, samples were rinsed with H₂O. Subsequently, 120-cycle-Al₂O₃ (∼10 nm) deposition was performed at 200 °C by atomic layer deposition (ALD) using trimethylaluminum (TMA) as a precursor and H₂O in the PicoSun ALD system. ²⁹⁾ The carrier gas was N₂ at flow rates of 150 sccm and 200 sccm for TMA and H₂O, respectively. The pulse times and purge times of them were 0.1 s and 4.0 s, respectively. The 120 nm thick Al gate electrode was fabricated by thermal evaporation. Finally, a 300 nm thick Al contact was deposited on the back side, followed by rapid thermal annealing at 350 °C for 1 min. The gate electrode was circular, with a diameter of 200 μm. The donor concentration N_D of the InAs substrates was determined to be 1.84 × 10¹⁶ cm⁻³ by Hall measurements at room temperature. Here, the Hall scattering factor ${\gamma }_{H}$ of 1.1 is used because ${\gamma }_{H}$ is limited by polar optical phonon scattering, which is dominant for InAs, and is known to be 1.1. ^30,31) The C–V measurements were performed in a cryo-prober. The temperature was varied from room temperature to 30 K.

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Figures 4(a)–4(c) show the C–V curves with bias voltages ranging from −1.5 to −4.5 V at 300 K, 79 K and 31 K, respectively, as a function of the measurement frequency from 1 MHz to 1 kHz. The capacitance change is less steep, and the frequency dispersion is larger at room temperature, which is attributed to the fast responses of the interface traps. However, the slope becomes steeper and the frequency dispersion decreases with decreasing temperature, which is attributed to the suppression of the high-frequency responses of interface traps at lower temperatures. Figure 5 shows the temperature dependence of C–V curves at 1 MHz. It was clearly confirmed that the slope became steeper with decreasing temperature. The C–V curves between 41 and 31 K were similar, suggesting that a high-frequency limit can be obtained in this temperature range. One of the concerns of C–V measurements at low temperatures is the freeze-out of the carriers. However, it is well known that for n-type InAs, the carriers do not freeze even at 4 K because the donor level is located above the conduction band edge. ^32,33) Furthermore, this is confirmed in Fig. 4(c), where there is no measurement frequency dependence of the accumulation capacitance at 31 K, indicating that the increase in the substrate resistance component owing to freeze-out is negligible in the present measurements. Figure 6 shows the temperature dependence of the minority carrier density in an n-InAs MOS capacitor when −4.5 V is applied. Under this bias condition, the Fermi level was located within the band gap, approximately 0.06 eV upper above the edge of the valence band, even for a large negative applied voltage. Consequently, the minority carrier density was strongly dependent on the temperature. However, the values are smaller than the interface state density, indicating that the impact of minority carriers is negligible in the present analysis. Such a low areal density is owing to the Fermi-level position cannot reach the valence band edge at any temperature because of the large D_it in the MOS interfaces of In-based III–V semiconductors, which causes strong Fermi-level pinning near the valence band side of the band gap.

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To evaluate D_it using the Terman method, it is necessary to confirm the validity of the conditions under which the theoretical C–V curve is calculated. First, we investigated the impact of the accuracy of the estimated C_OX on D_it evaluated by the Terman method. The oxide capacitance C_OX was experimentally determined by fitting the experimental C–V curves in the accumulation region. However, as shown in the equivalent capacitance model in Fig. 2, it is difficult to determine C_OX for InAs because C_it is an unknown value, and can be larger than the accumulation-layer capacitance (C_acc). ²⁴⁾ Note that the typical capacitance equivalent thickness (CET) of C_acc is ∼2 nm for InAs, which is five times thicker than that of Si. ²⁴⁾ To investigate the impact of C_OX, the three cases of C_OX are compared, as shown in Fig. 7(a).

• (1)  
  C_OX = C_OX,1 for C_it = ∞, where C_OX,1 is the maximum value of the measured capacitance C_max.
• (2)  
  C_OX = C_OX,2 for C_it = 0 determined by fitting the experimental curve without considering the quantum confinement effect of 2DEG at the interface. ³⁴⁾ The electrons are modeled as three-dimensional carriers in the entire region, and the carrier density is calculated using the Fermi–Dirac distribution.
• (3)  
  C_OX = C_OX,3 for C_it = 0, considering the quantum effect of 2DEG at the interface. Here, the wavefunction of the 2DEG and the potential were calculated by solving the Schrödinger and Poisson equations self-consistently. CET of C_acc is 2.0 nm for the 2DEG density N_s of 2 × 10¹² cm⁻², where the measured capacitance is C_max at the bias voltage of −1.5 V.

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Specifically, C_OX,1 and C_OX,3 correspond to the minimum and maximum limits, respectively, of C_OX. Figure 7(b) shows the energy distributions of D_it evaluated using the Terman method for the C–V curves at 31 K using the Fermi–Dirac distribution under the assumption that C_OX is C_OX,1, C_OX,2, and C_OX,3. Note that the evaluated interface traps near the conduction band are not valid for the Terman method because the interface traps can quickly respond; thus, the response is included in the capacitance component because of the existence of many free electrons near the interface. Therefore, the D_it values near the conduction band, evaluated by the Terman method, are inaccurate, regardless of the C_OX we assumed. In addition, there are small shifts in the surface potential on the valence band side; however, these shifts are significantly small, even under a relatively large change in C_OX. Therefore, it is shown that this ambiguity in C_OX does not provide a meaningful error in D_it, as evaluated using the Terman method. Although it is a challenge to determine C_OX accurately from C–V curves because of the large C_it for III–V semiconductors with low electron effective mass, such as InAs, these results indicate that the accurate determination of C_OX is not a critical factor in D_it evaluation. Because InAs has a large C_it, C_OX,1 is closer to the true C_OX. Therefore, C_OX,1 was used for the subsequent calculations of the theoretical C–V curves.

Second, we investigated the impact of the choice of Boltzmann and Fermi–Dirac statistics in the calculation of the theoretical C–V curves on the D_it evaluation. Figure 8 shows the energy distributions of D_it evaluated by the Terman method using the Fermi–Dirac and Boltzmann distributions. There was almost no difference, except near the conduction band. As previously described, the D_it values near the conduction band, evaluated by the Terman method, were inaccurate, regardless of the assumed distribution type. Because there is no difference in D_it near the midgap, where the Terman method is valid and accurate, the choice of the distribution function has a slight effect on the evaluated D_it. This is because the Fermi energy is far from the conduction and valence band edges in the depletion region; thus, the Boltzmann statistics remain valid for the calculation of the capacitance under the depletion condition. However, the Fermi–Dirac distribution was used for subsequent calculations of the theoretical C–V curves, which provided highly accurate calculations at low temperatures.

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Furthermore, the influence of the C–V hysteresis owing to slow traps should be examined. Figure 9(a) shows the hysteresis of C–V curves for two different voltage scan ranges. When the voltage range is wide from −1.5 to −4.5 V, the observed hysteresis causes the difference in the slope of the capacitance change between the forward and backward sweep. As shown in Fig. 9(b), slow traps have a significant impact on the evaluated D_it. Especially in the forward sweep, the de-trapping of holes from slow traps or trapping of electrons into slow traps makes the slope less steep, resulting in a higher apparent D_it. However, as shown in Fig. 9(a), the hysteresis can be eliminated, and the C–V curves between the forward and backward sweeps become identical by utilizing the narrow voltage scan range from −2.4 to −2.9 V. Consequently, the evaluated D_it is almost the same between the forward and backward sweeps, as shown in Fig. 9(b). It is also shown that the slow traps are mainly charged when a negative gate bias voltage is applied because the C–V curves of the backward sweep are almost the same for the wide and narrow voltage ranges. This is surprisingly different from the general behavior of slow traps, such as Ge MOS interfaces. ³⁵⁾ Slow traps are charged in the accumulation region because slow traps originating from the border traps inside the gate insulators and free carriers at the interfaces are required to charge the border traps. However, the slow traps of InAs MOS interfaces are charged only in the depletion region, although theoretical calculations suggest that no inversion carriers are generated, and there are no free carriers at the interface. The origin of slow traps at InAs MOS interfaces remains unclear. The important points in the C–V measurement are the careful selection of the minimum value of the negative gate bias to suppress the trapping/de-trapping of charges in slow traps and to use C–V curves measured in a narrow voltage range for the Terman method.

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Finally, Fig. 10(a) shows the temperature dependence of the C–V curves in a narrow voltage range with negligible hysteresis. Similar to Fig. 4, the C–V curves between 40 and 31 K were almost identical, indicating that the high-frequency limit was obtained. Figure 10(b) shows the energy distributions of D_it evaluated from the C–V curves using the Terman method. E_C and E_FB were used at 31 K. Note that the changes in E_C and E_FB owing to temperature changes are considerable small, and have a slight impact on the plot of the D_it distributions at different temperatures. Because the D_it values are almost similar between 40 and 31 K, it can be judged that an accurate evaluation of D_it at the InAs MOS interfaces was achieved by the Terman method using the proper conditions clarified in this study. Consequently, a minimum value of D_it of ∼10¹¹ cm⁻² eV⁻¹ was obtained for the ALD Al₂O₃/InAs MOS capacitors.

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We studied the influence of the measurement conditions of C–V characteristics and the theoretical model in the calculation of the ideal C–V curves on the D_it evaluation at the InAs MOS interfaces using the Terman method. Consequently, the C–V measurements at less than 40 K are necessary to suppress the response of interface traps, and to obtain the high-frequency limit of the C–V curves. A small negative gate voltage should be chosen to suppress the hysteresis of C–V curves because slow traps are charged in the surface potential near the valence band. In the calculation of the ideal C–V curves, the choice of the Fermi–Dirac or Boltzmann statics and the accuracy of C_OX, which cannot be simply obtained from experimental C–V curves on III–V semiconductors, have a slight impact on the D_it evaluation. These guidelines allow us to evaluate D_it accurately using the Terman method. Consequently, the D_it of the ALD-Al₂O₃/InAs interface was accurately evaluated, and the minimum value of D_it was ∼10¹¹ cm⁻² eV⁻¹.

This work was supported by JSPS KAKENHI, Grant Nos. 22H00208 and 21J10272, Japan, and by a project, JPNP16007, commissioned by the New Energy and Industrial Technology Development Organization (NEDO), Japan.