Evaluation of the border traps in LPCVD Si₃N₄/GaN/AlGaN/GaN MIS structure with long time constant using quasi-static capacitance voltage method

Figure 2 shows the measured HF capacitance voltage (C–V) and conductance voltage (G/ω–V) curves of the MIS structure at frequencies of 1 kHz and 1 MHz. The dc bias sweeping direction is from negative to positive and then back with a sweep rating of 0.1 V s⁻¹. The theoretical low frequency curve without traps calculated without considering quantum effect is also shown for comparison. From the theoretical curve, it can be seen that two sharp rising of capacitance corresponding to the formation of 2DEG and the spillover of electrons in the GaN cap layer are observed. It should be noted that the second rise could also be induced by the response of trap states at the Si₃N₄/GaN interface. ^21,22) However, the second rising is not observed in experimental C–V curves even up to 6 V for both frequencies. The lack of the second rise of capacitance suggests that there are high density of deep trap near the Si₃N₄/GaN interface. The large density of deep trap states near the interface would pin the surface Fermi level at a certain energy level below the conduction band of GaN and prohibit the communication of carriers between the 2DEG channel and the interface. The lack of the G/ω–V peak in positive bias also proves the above analysis as no loss would be observed if the carriers does not response to the ac signal. Meanwhile, those trap states responsible for the flat C–V curve in positive bias would not response at 1 kHz and the time constant should be larger than 1 ms. Those traps would most likely to be the border traps, which have a relatively long time constant.

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The results in Fig. 3 are measured with the following sequences: QSCV with integration time from 50 ms to 10 s, and AC–CV curves with frequencies of 20 Hz, 100 Hz, 1 kHz and 1 MHz. With high positive gate bias, part of trapped carriers with extremely long time constant would not be emitted even after 5 min relaxation between each measurement, which could contribute to the shift between QSCV and AC–CV curves.

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It can be seen in Fig. 3 that the second rising of capacitance is already observed with 50 ms integration time during QSCV measurement. The quasi-static capacitance in the second rising continuously increases with the integration time from 50 ms to 10 s, suggesting a broad distribution of border traps. For AC–CV measurement, there is also signs of the second rising of capacitance at ac frequency of 20 Hz. The measured AC–CV curves at low frequency is noisy due to the small ac current as the capacitor under test is smaller than 15 pF. The equivalent ac frequency for an integration time of 50 ms in QSCV measurement is $f=1/2\pi \tau \approx 3\,{\rm{Hz}}.$ From Fig. 3 it can be seen that the measured QSCV and HFCV capacitance values are continuous as a function of measurement frequency, suggesting that the QSCV measurement is effective in probing trap states, especially the one with long time constant.

Figure 4 shows the conduction band diagram of the Si₃N₄/GaN/AlGaN/GaN MIS structures. E_Fs is the location of Fermi level in the semiconductor layer. E_Fm is the location of Fermi level of the anode metal. For the border traps distributed with a distance x from the Si₃N₄/GaN interface, the capture cross section ${\sigma }_{T}$ is reduced by the factor $\exp \left(-x/\lambda \right)$ when viewed by an electron at the GaN surface from the quantum tunneling theory if the tunneling process is elastic, ^23,24)

$$\begin{eqnarray}&&{\sigma }_{T}={\sigma }_{n}\exp \left(-x/\lambda \right),\end{eqnarray} \tag{ 1 }$$

where ${\sigma }_{n}$ is the capture cross section of the interface traps (located with distance 0 from the interface) and λ is the insulator tunneling attenuation distance defined as ${\rm{\lambda }}=\hslash /\sqrt{8{m}^{* }{{\rm{\Phi }}}_{B}}.$ m^* is the electron effective mass of the insulator and ${{\rm{\Phi }}}_{B}$ is the barrier height from the energy level of interface traps to the conduction band of Si₃N₄ layer.

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Then the time constant of the border trap τ (mean time before the trap captures an electron) is expressed as,

$$\begin{eqnarray}&&\tau =\displaystyle \frac{1}{{n}_{s}{v}_{th}{\sigma }_{T}}=\displaystyle \frac{1}{{n}_{s}{v}_{th}{\sigma }_{n}\exp \left(-x/\lambda \right)}={\tau }_{0}\exp \left(x/\lambda \right),\end{eqnarray} \tag{ 2 }$$

$$\begin{eqnarray}&&{\tau }_{0}=\displaystyle \frac{1}{{n}_{s}{v}_{th}{\sigma }_{n}}=\displaystyle \frac{1}{{v}_{th}{\sigma }_{n}{N}_{C}}\exp \left(\displaystyle \frac{{E}_{C}-{E}_{T}}{kT}\right),\end{eqnarray} \tag{ 3 }$$

where τ₀ is the time constant of traps at the interface, ${v}_{th}$ is the thermal velocity of electrons. N_C is the density of states of the conduction band. E_T is the energy level of the interface traps relative to the conduction band of GaN layer. The probing depth boundary x_m within which the traps would response can be expressed as:

$$\begin{eqnarray}&&{x}_{m}=\lambda \,\mathrm{ln}\left({\tau }_{m}/{\tau }_{0}\right),\end{eqnarray} \tag{ 4 }$$

where τ_m is the integration time during QSCV measurement. The trapped charge δQ in the energy range δE from E₁ to E₂ is

$$\begin{eqnarray}&&\delta Q=\displaystyle {\int }_{0}^{{x}_{m}}q{N}_{t}\left(x\right)\delta Edx,\end{eqnarray} \tag{ 5 }$$

where N_t(x) is the border trap density in unit of cm⁻³ eV⁻¹ and E is the energy level of the traps relative to the conduction band of GaN. The depth and energy distribution N_t of border traps could be extracted from the integration time dependent quasi-static capacitance C by,

$$\begin{eqnarray}&&{N}_{t}\left(E,x\right)=\displaystyle \frac{d\left(\delta Q/\delta E\right)}{qdx}=\displaystyle \frac{1}{q\lambda \delta E}\displaystyle \frac{d\left(\delta Q\right)}{d\left(ln{\tau }_{m}\right)},\end{eqnarray} \tag{ 6 }$$

$$\begin{eqnarray}&&Q=\displaystyle \int CdV,\end{eqnarray} \tag{ 7 }$$

where V is the dc bias during QSCV measurement. In order to accurately calculate δE and the energy level E relative to the conduction band edge of GaN, we adopted the method proposed by C. N. Berglund in SiO₂/Si system. ²⁵⁾ It can be seen in Fig. 4 that

$$\begin{eqnarray}&&d{V}_{a}=d{V}_{I}+d{V}_{b}+d{\psi }_{s},\end{eqnarray} \tag{ 8 }$$

where V_a is the voltage applied on the anode, V_I is the voltage drop on the insulator, V_b is the voltage drop on the barrier layer (including AlGaN layer and the GaN cap) and ψ_s is the surface potential of the channel layer. If the 2DEG channel is in accumulation and degenerated in the sweeping range of V_a, ψ_s would not change much with the anode bias and $d{\psi }_{s}$ could be neglected. Then, the measured capacitance could be expressed as

$$\begin{eqnarray}&&C\left({V}_{a}\right)=\displaystyle \frac{dQ}{d{V}_{a}}={C}_{I}\displaystyle \frac{d{V}_{I}}{d{V}_{a}}={C}_{I}\left(1-\displaystyle \frac{d{V}_{b}}{d{V}_{a}}\right),\end{eqnarray} \tag{ 9 }$$

where C_I is the capacitance of the insulator layer.

Hence,

$$\begin{eqnarray}&&\displaystyle \frac{d{V}_{b}}{d{V}_{a}}=1-\displaystyle \frac{C\left({V}_{a}\right)}{{C}_{I}}.\end{eqnarray} \tag{ 10 }$$

Then, ${V}_{b}({V}_{a})$ could be calculated by integration Eq. (10) with the QSCV curve measured at an integration time of 20 s, supposing that all the traps would response

$$\begin{eqnarray}&&{V}_{b}\left({V}_{1}\right)={V}_{b}\left({V}_{0}\right)+\displaystyle {\int }_{{V}_{0}}^{{V}_{1}}\left[1-\displaystyle \frac{C\left({V}_{a}\right)}{{C}_{I}}\right]d{V}_{a}.\end{eqnarray} \tag{ 11 }$$

It can be seen that Eq. (11) is similar with the situation in SiO₂/Si system, ²⁵⁾ taking advantage of the degenerated 2DEG in AlGaN/GaN heterostructure. The trap energy level E at a certain V_a is directly correlated to V_b by

$$\begin{eqnarray}&&E\left({V}_{a}\right)={V}_{b}+{\rm{\Delta }}{E}_{c}+{\psi }_{s}+{E}_{n},\end{eqnarray} \tag{ 12 }$$

where ${\rm{\Delta }}{E}_{c}$ is the conduction band offset between AlGaN and GaN, E _n is the distance between the conduction band and the Fermi level in the GaN buffer. Due to the complication of the 2DEG system, it is difficult to match the experimental curve of $\tfrac{d{V}_{b}}{d{V}_{a}}$ versus V_b and the theoretical curve assuming no trap states in the strong accumulation region as is done in SiO₂/Si system. ²⁵⁾ Alternately, we chose V₀ as 0 V and E(0) could be calculated from the 2DEG density extracted from HF curves by solving the self-consistent Poisson's equation. The theoretical net negative charge at the GaN/Al_0.25Ga_0.75N interface and and positive charge at the Al_0.25Ga_0.75N/GaN interface induced by polarization effect is set to be 1.05 × 10¹³ cm⁻². In our calculation, the net charge at the Si₃N₄/GaN interface (including the surface donor traps and polarization induced charge) is tuned to fit the measured 2DEG density. The trap energy level at a certain bias V_a could be calculated by,

$$\begin{eqnarray}&&E\left({V}_{a}\right)=E\left(0\right)+{V}_{b}\left({V}_{a}\right)-{V}_{b}\left(0\right).\end{eqnarray} \tag{ 13 }$$

The prerequisite of Eq. (9) is also satisfied as the lower limit of the integration (V₀) is 0 V and the 2DEG is degenerated from 0 to 6 V. Once we got the bias dependent trap energy level E(V_a), then the barrier height ${{\rm{\Phi }}}_{B}$ influencing the attenuation length λ in Eqs. (1) and (2) could be calculated by ${{\rm{\Phi }}}_{B}\left({V}_{a}\right)=E\left({V}_{a}\right)+{\rm{\Delta }}{E}_{C,MIS},$ where ${\rm{\Delta }}{E}_{C,MIS}$ is the conduction band offset between Si₃N₄ and GaN. Figure 5 shows the calculated ${{\rm{\Phi }}}_{B}$ and attenuation length λ as a function of bias with the equations above.

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Figure 6 shows the distribution of border traps extracted using Eqs. (6), (7), (11) and (13). There are high density of border traps up to an order of 10²¹ cm⁻³ eV⁻¹ located at energy level between E_C,GaN − 0.04 eV and E_C,GaN − 0.66 eV with a distance of 1.0–4.2 nm from the Si₃N₄/GaN interface. The extracted value is comparable with the 10¹³–10¹⁴ cm⁻² eV⁻¹ in the work of Ramanan et al., supposing that the border traps are distributed in several nanometers from the interface. ¹⁴⁾

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Figure 7 shows the temperature dependent QSCV curves of the MIS structure from 25 °C to 70 °C. The capacitance in the second rise region is positive temperature dependent and the behaviour is more obvious at low integration time, suggesting that the capture process is thermal activated. In our experiment, the time constant is much larger than that of the interface states and we attribute the response in QSCV measurement to border traps in the Si₃N₄ layer close to the Si₃N₄/GaN interface. The charge exchange between the border trap and interface states is initially supposed to be based on the elastic tunneling mechanism, which is weak temperature dependent. The observed thermal activation behavior in QSCV measurement could be explained if the tunneling process is not elastic and there are lattice relaxation during trapping. ^26,27) The electron–phonon interaction could be illustrated using the coordinate diagram. Figure 8 shows the configuration-coordinate diagram of the border traps featuring lattice relaxation after trapping. ^26,28,29) The energy barrier for electron capture and emission between neutral and occupied states is E_a and E_b, respectively. For the trap time constant and capture cross section calculation, we used the formulation proposed by C. H. Henry and D. V. Lang. ²⁸⁾ The capture cross section ${\sigma }_{T,LR}$ considering the lattice relaxation is expressed as,

$$\begin{eqnarray}&&{\sigma }_{T,LR}={\sigma }_{T}\,\ast \,\exp \left({E}_{a}/kT\right)={\sigma }_{n}\exp \left(-x/\lambda \right)\,\ast \,\exp \left({E}_{a}/kT\right)\,.\end{eqnarray} \tag{ 14 }$$

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Then, the time constant of the border trap considering the lattice relaxation could be expressed as:

$$\begin{eqnarray}&&\tau ={\tau }_{0}\exp \left(x/\lambda \right)\,\ast \,\exp \left(-{E}_{a}/kT\right).\end{eqnarray} \tag{ 15 }$$

The thermal activated capture cross section and smaller time constant would lead to the increased QSCV capacitance at high temperature due to thermal enhanced trapping during integration time τ_m. ^28–30) From Eq. (15) we can calculate the probing depth ${x}_{m,LR}$ of the border traps with lattice relaxation,

$$\begin{eqnarray}&&\mathrm{ln}\left(\displaystyle \frac{{\tau }_{m}}{{\tau }_{0}}\right)=\displaystyle \frac{{x}_{m,LR}}{{\rm{\lambda }}}-\displaystyle \frac{{E}_{a}}{kT}\,,\,\end{eqnarray} \tag{ 16 }$$

$$\begin{eqnarray}&&{x}_{m,LR}={\rm{\lambda }}\,\mathrm{ln}\left({\tau }_{m}/{\tau }_{0}\right)+\displaystyle \frac{{\rm{\lambda }}{E}_{a}}{kT}\,.\end{eqnarray} \tag{ 17 }$$

Comparing Eq. (17) with (4), it can be seen that the probing depth of the border trap is shifted by a constant $\tfrac{{\rm{\lambda }}{E}_{a}}{kT}$ if we know the activation energy E_a. If the capture cross section is not thermal activated (E_a = 0), we can see that Eq. (17) is reduced to Eq. (4). The calculation is self-consistent. The current work mainly focused on the methodology to extract the properties of border traps using QSCV measurement. The calculation of activation energy for carrier capture after tunneling is our further work. For the device under test in this study, the actual distribution of border traps is a redrawn figure of Fig. 6 by replacing the title of x axis with $x-\tfrac{{\rm{\lambda }}{E}_{a}}{kT}$ or shift the tick label of x axis by $\tfrac{\lambda {E}_{a}}{kT}.$ The probing depth is deeper.

Previous, it was found that directly grown LPCVD Si₃N₄ on (Al)GaN surface would lead to a disorder interface between Si₃N₄ and (Al)GaN, possibly induced by the H erosion effect during growth. ¹⁶⁾ The contamination of the GaN surface before extrinsic dielectric growth may also induce trap states. Figure 9 shows the energy-dispersive X-ray (EDX) spectroscopy of the Si₃N₄/GaN/AlGaN interface. It can be found that the O centration is relatively high close to the Si₃N₄/GaN interface. It has also been reported that the Ga–O component is higher at the surface in an ICP etched GaN surface, which lead to a high density of border traps in gate recessed Al₂O₃/GaN MOSFET. ¹³⁾ The result suggests that in situ or early surface protection should be adopted to reduce the density of border traps.

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Finally, we would like to briefly discuss the feasibility of the proposed method in extracting the properties of border traps in GaN MIS structure with buried channel. In AlGaN/GaN MIS structure, the interface traps could not directly exchange carriers with the channel due to the existence of the AlGaN barrier. The electrons in the 2DEG channel could transport through the AlGaN barrier layer and be captured by the interface related traps if the position of the trap energy level is lower than the Fermi level. The charging and discharge time constant of the carriers between the surface channel and 2DEG channel may range from μs to ms due to the large conduction band offset and polarization enhanced barrier. ³¹⁾ In the above analysis, the rising of the second slope is supposed to be induced solely by the charging of trap states. However, electrons could also be accumulated in the surface of GaN cap layer at high enough bias and induce the rising of capacitance. The proposed method stands for the results measured with long integration time, such as 50 ms and above in this work, as the charging and discharge time of free electrons in the barrier layer should be smaller. If one would like to detect border traps with characteristic time constant well below 50 ms, such as those close to the interface with energy level approaching the conduction band of GaN, directly calculating the trap density from the measured CV curves would overestimate the value. Meanwhile, Eq. (8) assumes that electrons does not spill over to the GaN cap. The upper limit of the integration V₁ in Eq. (11) is limited not only by the thickness of Si₃N₄ and barrier layer, but also the density of interface related traps. The large density of border traps in the current device prohibit the formation of surface channel in the GaN cap layer and the aforementioned analysis could be performed.