On-chip leakage current variation measurement using external-reference-free current-to-time conversion for densely placed MOSFETs

Figure 1 shows our proposed current-to-time converter. The capacitor C_L is first charged to V_dd by turning the M_charge ON. Then, C_L is discharged through a selected DUT MOSFET. The time interval d between the two outputs' switching transition is then measured. The discharge time d_ia from V_dd to V_X1, and the discharge time d_ib from V_dd to V_X2 for the ith MOSFET can be approximated as follows.

$$\begin{eqnarray}&&{d}_{i{\rm{a}}}\simeq \displaystyle \frac{({V}_{\mathrm{dd}}-{V}_{{\rm{X}}1})\cdot {C}_{{\rm{L}}}}{{I}_{i}}+{\varepsilon }_{{\rm{a}}},\end{eqnarray} \tag{ 1 }$$

$$\begin{eqnarray}&&{d}_{i{\rm{b}}}\simeq \displaystyle \frac{({V}_{\mathrm{dd}}-{V}_{{\rm{X}}2})\cdot {C}_{{\rm{L}}}}{{I}_{i}}+{\varepsilon }_{{\rm{b}}}.\end{eqnarray} \tag{ 2 }$$

Here, I_i is the drain current of the ith selected MOSFET M_i , and ε_a and ε_b are inverter delays. In a typical current to time conversion, inverter or comparator delay causes an error in the measurement. Here, as we measure the delay difference d_i corresponding to the ith DUT M_i with drain current I_i which can be expressed as follows.

$$\begin{eqnarray}&&{d}_{i}={d}_{i{\rm{b}}}-{d}_{i{\rm{a}}}\simeq \displaystyle \frac{({V}_{{\rm{X}}1}-{V}_{{\rm{X}}2})\cdot {C}_{{\rm{L}}}}{{I}_{i}}+({\varepsilon }_{{\rm{a}}}-{\varepsilon }_{{\rm{b}}}).\end{eqnarray} \tag{ 3 }$$

For accurate measurement of subthreshold leakage current, we need to make sure that the following issues are properly addressed.

• (1)  
  Cancel out the inverter delay,
• (2)  
  minimize the voltage drop across the switch tree,
• (3)  
  make (V_X1 − V_X2) stable across a wide temperature range, and
• (4)  
  make V_ds fluctuation of the selected MOSFET small during the measurement.

We explain the different design decisions to meet the above-mentioned requirements in the following. First, if we design the two inverters to have similar transition delay, the term (ε_a − ε_b) becomes negligible. These delay components can be expressed as follows.

$$\begin{eqnarray}&&{\varepsilon }_{{\rm{a}}}=\displaystyle \frac{{C}_{\mathrm{out}1}\cdot {V}_{{\rm{X}}1}}{{I}_{{\rm{p}}1}},{\varepsilon }_{{\rm{b}}}=\displaystyle \frac{{C}_{\mathrm{out}2}\cdot {V}_{{\rm{X}}2}}{{I}_{{\rm{p}}2}}.\end{eqnarray} \tag{ 4 }$$

$$\begin{eqnarray}&&\displaystyle \frac{{\varepsilon }_{{\rm{a}}}}{{\varepsilon }_{{\rm{b}}}}=\displaystyle \frac{{C}_{\mathrm{out}1}}{{C}_{\mathrm{out}2}}\cdot \displaystyle \frac{{I}_{{\rm{p}}2}}{{I}_{{\rm{p}}1}}\cdot \displaystyle \frac{{V}_{{\rm{X}}1}}{{V}_{{\rm{X}}2}}.\end{eqnarray} \tag{ 5 }$$

Here, C_out1 and C_out2 are output load capacitances for the two inverters. V_X1 and V_X2 are the logic threshold voltages. I_p1 and I_p2 are the driving currents. Based on Eq. (5), we can tune the load capacitance ratio such that ε_a/ε_b is close to 1. The load capacitances can be adjusted by tuning the gate area of the following inverters. Thus, using a time-difference-based approach, the effects of inverter delay can be canceled out.

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Second, we explain the minimization method of the switch resistance. As shown on the left side of Fig. 2, the gate-source voltage of the switch transistor is small during the initial period which may cause an error in the conversion. To reduce the effect of the switch transistor's resistance, the drain voltage of the switch should be low enough. As the right side of Fig. 2 shows, the voltage drop across the ON-state switch is not negligible when V_d is high. After the drain voltage V_d, which corresponds to the output node voltage, is sufficiently low, the voltage drop across the switch becomes negligible. Thus, the voltage drop across the switch tree can be minimized by making sure that the measurement is taken when the output node voltage is sufficiently low such that the voltage drop across the switches is close to zero. In the figure, when capacitor node voltage V_CL reaches V_X1, which is 0.38 V in this design at 1.0 V operation, V_CL and internal node voltage V_d are almost identical.

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Third, as the same types of pMOSFET and nMOSFET are used for the inverters, both of the inverter logic threshold voltages are expected to have similar temperature coefficients. Logic threshold voltage V_X of an inverter can be expressed as follows. ¹⁴⁾

$$\begin{eqnarray}&&{V}_{{\rm{X}}}=\displaystyle \frac{{V}_{\mathrm{dd}}+{V}_{\mathrm{thp}}+\sqrt{\gamma }{V}_{\mathrm{thn}}}{1+\sqrt{\gamma }},\end{eqnarray} \tag{ 6 }$$

$$\begin{eqnarray}&&\gamma =\displaystyle \frac{{\mu }_{{\rm{n}}}{C}_{\mathrm{oxn}}{W}_{{\rm{n}}}/{L}_{{\rm{n}}}}{{\mu }_{{\rm{p}}}{C}_{\mathrm{oxp}}{W}_{{\rm{p}}}/{L}_{{\rm{p}}}}.\end{eqnarray} \tag{ 7 }$$

Here V_thp and V_thn are threshold voltages of pMOSFET and nMOSFET, respectively. μ_p and μ_n represent mobility for pMOSFET and nMOSFET. C_oxp and C_oxn are gate oxide capacitances per area. W_p and W_n are the gate widths, and L_p and L_n are the gate lengths. γ here thus represents the driving strength ratio between nMOSFET and pMOSFET. From Eq. (6), we can tune the logic threshold by tuning γ and threshold voltages. Consider the case of tuning the logic threshold by adjusting the pMOSFET threshold voltages of the two inverters. In this case, ΔV_X is equal to V_thp2 − V_thp1. Different threshold voltages can be obtained by gate length modulation for example. Threshold voltage typically has a sensitivity of 1–2 mV K⁻¹ against temperature. ¹⁴⁾ Assuming both the threshold voltages change by the same amount with a change in temperature, we expect a stable ΔV_X over a wide range of temperatures. It should be noted that there are second-order dependencies that may cause some deviation. Figure 3 shows the simulated threshold voltage difference against temperature. The amount of fluctuation for (V_X1 − V_X2) across a temperature range of 100 °C under five different process corners of "TT", "SF", "FS", "SS" and "FF" is plotted in the figure. We observe negligible fluctuation of (V_X1 − V_X2) across the temperature range. Thus, we find the second-order effects to be small in the target process.

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Finally, we also need to make sure that the drain voltage remains constant during the current measurement for accurate characterization of different process parameters such as the subthreshold coefficient and threshold voltage. This can be achieved by setting the two threshold voltages close to each other. As illustrated in Fig. 2, the inverters are designed such that the two threshold voltages of V_X1 and V_X2 become close to each other and these values are much lower.

The design of the switch tree is important to maximize DUT current ratio to other leakage current ratios. Putting all the DUT MOSFETs in parallel will cause large gate leakage which can be large in scaled processes. To reduce the number of parallel MOSFETs, we use a tree-based switch structure as shown in Fig. 4. In the structure, the switches are divided into several stages and each stage has several branches. With the stacking of the switches, the source voltage of the intermediate transistors rises resulting in negative V_gs and V_bs values. Negative V_gs and V_bs decrease the leakage current further. For the case of 256 DUT MOSFETs, the ratio between DUT current and other leakage currents is simulated to be 168 for the target process when V_g = 0.2 V.

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Figure 5 shows the block diagram of our measurement circuit. Inside the chip, N number of DUT (Device Under Test) MOSFETs are placed and routed along with the switches. First, using serial clock "sclk" and serial data "sdin", the address of the target MOSFET is sent to the chip. The decoder inside the chip decodes the address and generates the signals for the switches to activate the path for the target MOSFET. The "meas" signal is then lowered for some time to allow the output node to charge to V_dd. The "meas" signal is then set to high to let the output node to be discharged by one of the DUT MOSFETs. After the output node is lowered to cross the logic threshold voltages of the inverters, the output signals "out1" and "out2" are then inverted sequentially. The delay difference between the two output signals gives the delay corresponding to the subthreshold current of the target MOSFET. This process is then iterated by selecting the next MOSFET.

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A similar complementary test structure can be implemented to measure variations of pMOSFETs. In that case, the output node will be discharged to V_ss first, and then the node will be charged by one of the pMOSFETs. In this implementation, we change the address after the completion of each measurement by sending the serial signals which cause some delay. To reduce the test time further, we can implement a counter-on-chip that will increment the address value after the completion of each measurement.

As (V_X1 − V_X2) is shared among all the DUT devices, and its value is constant across temperature, we can relate the variance of delay to the variance of subthreshold leakage current as follows

$$\begin{eqnarray}&&\mathrm{ln}d=\mathrm{ln}({V}_{{\rm{X}}1}-{V}_{{\rm{X}}2})+\mathrm{ln}{C}_{{\rm{L}}}-\mathrm{ln}I,\end{eqnarray} \tag{ 8 }$$

$$\begin{eqnarray}&&\mathrm{Var}\left(\mathrm{ln}d\right)=\mathrm{Var}\left(\mathrm{ln}I\right).\end{eqnarray} \tag{ 9 }$$

The subthreshold coefficient of each MOSFET can be calculated by measuring the current at different gate-source voltages where the MOSFETs operate at weak inversion. Different gate-source voltages can be achieved by tuning V_g in our circuit. Choosing two values of V_g to be V_g1 and V_g2, we obtain the following relationships. ¹⁵⁾

$$\begin{eqnarray}&&{I}_{1}={I}_{{\rm{S}}}\exp \left(\displaystyle \frac{{V}_{{\rm{g}}1}-{V}_{\mathrm{th}}}{m{\rm{k}}T/{\rm{q}}}\right),\end{eqnarray} \tag{ 10 }$$

$$\begin{eqnarray}&&{I}_{2}={I}_{{\rm{S}}}\exp \left(\displaystyle \frac{{V}_{{\rm{g}}2}-{V}_{\mathrm{th}}}{m{\rm{k}}T/{\rm{q}}}\right),\end{eqnarray} \tag{ 11 }$$

$$\begin{eqnarray}&&{d}_{2}=\displaystyle \frac{{C}_{{\rm{L}}}({V}_{{\rm{X}}1}-{V}_{{\rm{X}}2})}{{I}_{2}},{d}_{1}=\displaystyle \frac{{C}_{{\rm{L}}}({V}_{{\rm{X}}1}-{V}_{{\rm{X}}2})}{{I}_{1}},\end{eqnarray} \tag{ 12 }$$

$$\begin{eqnarray}&&\displaystyle \frac{{d}_{2}}{{d}_{1}}=\displaystyle \frac{{I}_{1}}{{I}_{2}},\end{eqnarray} \tag{ 13 }$$

$$\begin{eqnarray}&&\mathrm{ln}\left(\displaystyle \frac{{d}_{2}}{{d}_{1}}\right)=\displaystyle \frac{{\rm{q}}({V}_{{\rm{g}}2}-{V}_{{\rm{g}}1})}{{\rm{k}}T}\cdot \displaystyle \frac{1}{m},\end{eqnarray} \tag{ 14 }$$

$$\begin{eqnarray}&&m=\displaystyle \frac{{\rm{q}}({V}_{{\rm{g}}2}-{V}_{{\rm{g}}1})}{{\rm{k}}T}\cdot \displaystyle \frac{1}{\mathrm{ln}\left(\tfrac{{d}_{2}}{{d}_{1}}\right)}.\end{eqnarray} \tag{ 15 }$$

Here, I_S is the reverse saturation current, q is the elementary charge, k is the Boltzmann constant, m is the subthreshold coefficient, and T is the absolute temperature. From Eq. (15), we can obtain the value of subthreshold coefficient m for each MOSFET by measuring two delays at two different V_g values.

Accurate characterization of MOSFET threshold voltage variation is not straightforward. Different approaches are used in the literature to define threshold voltage to characterize its variation. ^16–19) We can see from Eq. (10) that the threshold voltage V_th and the subthreshold voltage m are closely coupled. These two values cannot be decoupled by tuning the V_gs values only. Thus, for scaled MOSFETs, where the subthreshold coefficient m varies largely, careful interpretation is required for threshold voltage variation. For larger devices, where m variation is negligible, V_th variation can be readily calculated by measuring delays at a constant V_g value using our circuit. ²⁰⁾

$$\begin{eqnarray}&&d=\displaystyle \frac{{C}_{{\rm{L}}}({V}_{{\rm{X}}1}-{V}_{{\rm{X}}2})}{I},\end{eqnarray} \tag{ 16 }$$

$$\begin{eqnarray}&&{\sigma }_{\mathrm{ln}d}={\sigma }_{\mathrm{ln}I}=\displaystyle \frac{{\sigma }_{{V}_{\mathrm{th}}}}{m{\rm{k}}T/{\rm{q}}},\end{eqnarray} \tag{ 17 }$$

$$\begin{eqnarray}&&{\sigma }_{{V}_{\mathrm{th}}}={\sigma }_{\mathrm{ln}d}\cdot \displaystyle \frac{m{\rm{k}}T}{{\rm{q}}}.\end{eqnarray} \tag{ 18 }$$

We have fabricated a test chip integrating 256 nMOSFETs, the switch tree, the current-to-time converter, and the switch decoder in a 65 nm bulk low-power CMOS process. The layout is designed with a cell-based design flow. Figure 6 shows the chip photograph and layout of our proposed circuit. The area is 0.038 mm². C_L is implemented using MIM capacitor. The value of C_L is 10 pF in this test chip which takes an area of 0.0086 mm². The values of V_X1 are 0.29 V, 0.38 V and 0.45 V at V_dd of 0.8 V, 1.0 V and 1.2 V, respectfully. The values of V_X1 − V_X2 are 40 mV, 50 mV and 70 mV at the three supply voltages.

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Figure 7(a) shows the QQ plot of the logarithm of measured delays at V_g = 0.2 V for different temperatures. A linear relationship is observed referring to that leakage current follows a lognormal distribution. This is further confirmed by plotting the histograms of the logarithm of delays for two different temperatures of 0 °C and 100 °C. The histograms are shown in Fig. 7(b). We observe Gaussian-like histograms for the delay logarithms. The variance increases with the lowering of temperature. Figure 8 shows the standard deviation of logarithm of delay against 1/T for three different supply voltages. As predicted by Eq. (17), the standard deviation of the logarithm of delay has a linear relationship against 1/T. We also observe the same linear relationship in Fig. 8, which confirms the validity of the measurement. We also observe that supply voltage change has negligible effect on the distribution.

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We have measured the delay value for each of the MOSFETs by measuring at different V_g values. Figure 9(a) shows the 1/d over a V_g range from 0.2 V to 0.4 V. We can observe that most of the devices show a linear relationship up to 0.3 V. However, some of the devices show nonlinear relation from 0.35 V which suggests that channel inversion has started for these devices at this point. Next, we have calculated the subthreshold coefficient m for each of the nMOSFETs using delay values at V_g values of 0.2 V and 0.25 V. Figure 9(b) shows the histograms of the calculated m values for two different temperatures of 0 °C and 100 °C. We observe large variation in the m values. This observation is supported by literature reports. ²¹⁾ However, to the best of our knowledge, our results are the first to demonstrate m distribution for scaled nMOSFETs that are densely placed as found in a digital circuit.

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As seen in Fig. 9(b), subthreshold coefficient m is not constant in this process for the minimum sized nMOSFETs. Therefore, Eq. (18) cannot be applied. We need more sophisticated extraction methods to accurately extract threshold voltage variation. Understanding the limitation of Eq. (18), we derive V_th variation assuming that m is constant. We use the median value of m from Fig. 9(b). The extracted standard deviation of V_th is then calculated to be 37 mV at 20 °C temperature. However, we should be careful that this value can be overestimated due to the variation in subthreshold coefficient m.