High-performance p-channel transistors on flexible substrate using direct roll transfer stamping

The Si NRs fabrication steps are similar to the description given in our previous work. ⁶⁾ Briefly, the fabrication process involved patterning of Si NRs with a length of 55 μm and width of 5 μm using a lateral dry etching process. The Si NR arrays were patterned by lithography and reactive-ion etching (RIE) (CHF₃/O₂, 50 sccm, 55 mTorr, 5 min) to define the NRs geometries and expose the buried oxide (Box) layer. Thermal diffusion doping was performed on the source wafer to create ohmic contacts. The SiO₂ diffusion barrier mask layer (thickness ∼ 250 nm) was deposited by using the plasma-enhanced chemical vapor deposition (PECVD). The openings of source and drain regions were performed using conventional photolithography steps. The resist served as a mask for selective dry etch process with a CH₃/Ar plasma using RIE system (40 sccm CH₃/Ar flow with a chamber base pressure of 30 mTorr, 200 W RF power). This step was carried out to etch the exposed areas of the oxide mask and open windows for diffusing boron in active regions (S/D) while the channel is covered by the SiO₂ mask. The selective doping of the source and drain regions of NRs was performed using spin-on dopant (SOD) through thermal diffusion of boron (Filmtronics, P451). The furnace annealing was carried out to activate p-type dopants at 1050 °C in Ar ambient for 30 min. The doping concentration, measured using 4-point-probe, was found to be >1 × 10 ¹⁸ cm^–3. The etching of the SiO₂ mask and Box layer was carried by hydrofluoric acid (HF) solution to obtain the suspended nanoribbons with delicate anchor points at both ends.

Custom-made DRTS set up ³⁾ was used to carry out a reliable transfer of suspended Si NR arrays (selectively p-type doped) on SOI substrate. The DRTS is a single step (direct transfer) process. To carry out the direct roll-based transfer process, first, an adhesion promoter of ∼1.0 μm (PI-2545 precursor from HDmicrosystems) was applied on the commercial PI substrate. Next, Si NRs are brought into direct physical contact with the semi-cured PI receiver substrate. The applied force during roll transfer stamping is 12 N, and the roll speed is 0.1 mm s⁻¹. After NR transfer, the PI substrate is subsequently cured at 250 °C for 2 h.

After DRTS, p-channel transistors were fabricated using RT processes. This includes deposition of high-quality gate dielectric (SiN_x , 100 nm) using ICP-CVD followed by metal deposition (Ti (10 nm)/Au (120 nm)) for gate, source, and drain using e-beam evaporation and lift-off. Electrical characterizations were performed using Cascade Micro-tech Auto-guard probe station interfaced with a semiconductor parameter analyser. Linkam PE120 Peltier system was used for heating and cooling the NRFETs to perform temperature dependence electrical measurements.

Figure 1 schematically shows the steps followed to fabricate p-channel NRFETs. As a first step, silicon NRs are fabricated on a rigid SOI wafer using a conventional nanofabrication process [Fig. 1(i)]. During this step, selective doping of the NRs was also carried out using SOD through the diffusion of boron to define source/drain (S/D) contact. This step produces an array of horizontally aligned and suspended NRs with well-defined channel lengths over SOI source wafers, which are eventually transferred to flexible receiver substrates using DRTS [Fig. 1(ii)]. The process is described in detail elsewhere. ³⁾ Briefly, the source SOI wafer with released NR arrays is brought into direct physical contact with the semi-cured PI thin film over the receiver substrate. Partially cured PI enhances the adhesion between NRs and receiver substrate and helps to improve the transfer yield and registration factor. A transfer yield of 95% with a registration factor of <100 nm can be achieved using the DRTS process. Figure 2(a) demonstrates a top-view SEM image of a single Si NRs array in releasable form, ready for direct retrieval onto the target substrate. The inset of Fig. 2(a) shows a magnified image of the suspended NRs, anchored at both edges (5 μm width at both sides and supported by the underlying Box layer) to maintain the correct alignment and registration accuracy. To have a uniform and high transfer yield over a large area, conformal contact between the semi-cured PI layer and Si NRs is needed which we achieved by applying a high force of 12 N. But the use of semi-cured PI makes the direct transfer process slower. To overcome this drawback, UV-cured polymers, as an adhesive layer, could be used. ³²⁾ Following the DRTS of NRs, low-temperature steps (e.g. dielectric and metal deposition) were carried out to finalize p-channel NRFETs [Figs. 1(iii) and 1(iv)].

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The fabricated p-channel NRFETs with length ∼5 μm and width ∼45 μm (9 NRs of 5 μm width) on PI substrates were characterized in ambient dark conditions. The electrical characterization results of a typically fabricated p-channel FET device are shown in Figs. 2(b)–2(d). The transfer characteristics (I_DS–V_GS) with drain bias (V_DS) of −1 V were obtained by varying gate-source voltage (V_GS) from 3 to −2 V and shown in both linear and logarithmic scale in Fig. 2(b). Critical FET performance parameters to consider were extracted using the transfer scan: on-state (I_on), off-state current (I_off), current on/off ratio (I_on/I_off), effective mobility (${\mu }_{{\rm{e}}{\rm{f}}{\rm{f}}}$), and subthreshold slope (SS). ³³⁾ The measured devices showed typical I_on (>10 μA)/I_off (<1 nA) current ratio of >10⁴ suggesting an excellent gate-channel control. The extracted SS from the logarithm transfer plot is 1 ± 0.3 V/decade. Large variation in SS suggests non-uniformity in the deposited SiN_x dielectric film and/or presence of interface traps between the channel and SiN_x interface non-uniformly. Further experiments are needed to confirm the exact reason for variation in SS. Next, threshold voltage (V_T) was extracted using the linear extrapolation method. For this, the linear extrapolation of I_DS–V_GS graph, intercepting the I_d = 0 at the x-axis (V_GS) gives the V_T value (0.6 V). This was followed by the calculation of transconductance (g_m ), according to Eq. (1) shown below:

$$\begin{eqnarray}&&{g}_{m}=\,\displaystyle \frac{\partial {I}_{{\rm{D}}{\rm{S}}}}{\partial {V}_{{\rm{G}}{\rm{S}}}}\left| \left| {V}_{{\rm{D}}{\rm{S}}}\right.\right.={\rm{c}}{\rm{o}}{\rm{n}}{\rm{s}}{\rm{t}}{\rm{a}}{\rm{n}}{\rm{t}}.\end{eqnarray} \tag{ 1 }$$

The extracted g_m was used to calculate the field-effect (effective) mobility, ${\mu }_{{\rm{e}}{\rm{f}}{\rm{f}}},$ using Eq. (2) where W and L are the gate width and length respectively and C_OX stands for the dielectric capacitance (W/L = 45 μm/5 μm, thickness of SiN_x dielectric = 100 nm)

$$\begin{eqnarray}&&{\mu }_{{\rm{e}}{\rm{f}}{\rm{f}}}=\displaystyle \frac{L}{W}\left(\displaystyle \frac{{g}_{m}}{{C}_{{\rm{o}}{\rm{x}}}{V}_{{\rm{D}}{\rm{S}}}}\right).\end{eqnarray} \tag{ 2 }$$

The extracted effective mobility was found to be ∼100 ± 10 cm² V⁻¹ s⁻¹ which compares well with most of the state-of-the-art p-channel Si NR-based FETs. Further, the performance of DRTS p-channel NRFET is compared with the other p-channel devices fabricated using conventional transfer-based techniques (Table I).

Next, the output characteristics (V_DS–I_DS) were obtained by varying V_GS from 0 to −3 V with a step of 0.5 V. Notably, the low-V_DS region shows a linear dependence of I_DS with increasing V_DS without any inflection point. This device characteristic (low-resistive metal–semiconductor (MS) contacts) is needed for achieving high device performance. Further, the output characteristics show strong drain current saturation (I_DS ^SAT) with increasing V_DS, confirming the excellent gate-channel capacitive coupling. To confirm the MS contact ohmicity, we have calculated the ratio of the change in the saturation voltage (V_DS ^SAT) with V_GS. In conventional transistors with ohmic contacts, a gradual channel approximation model is used to describe the drain current saturation: ³³⁾ V_DS ^SAT ≈ [V_GS − V_T]. According to the theory, the ratio of the change in the saturation voltage with gate voltage, for FETs with ohmic contacts, would be close to unity. The fabricated p-channel devices showed $\frac{\partial {V}_{{\rm{DS}}}^{{\rm{SAT}}}}{\partial {V}_{{\rm{GS}}}}\approx 1$ (confirming formation of ohmic contacts). Figure 2(d) shows the transfer characteristics of Si NRFET at various values of V_DS. It is worth noting from Fig. 2(d) that the V_T remains constant with varying V_DS, indicating high stability charge transport behavior under different drain voltages. We have further studied the device stability under bending and varying temperature conditions in the following sections.

The mechanical robustness of the flexible p-channel NRFETs were evaluated under different bending conditions. We obtained the transfer characteristic under planar conditions after bending by mounting the device on 3D printed convex and concave structures both with a radius of curvature of 30 mm. The cyclic bending measurement was performed after every 10 cycles (up to 100 cycles). An optical image showing durability test by repeating device bending up to 100 times is included in the inset of Fig. 3(a). Using the transfer characteristics, variation in the on-current [Fig. 3(a)] and threshold voltage [Fig. 3(b)] of the device were extracted. The peak values of drain current were obtained at V_GS = −3 V. As can be seen from this set of data, the I_on showed a 23% rise after 100 bending cycles. On the other hand, the V_T of the device showed slight random variations initially (up to 60 °C) but it eventually stabilized to the initial V_T value. This change in the electrical performance after bending could be attributed to the change of the band structure of the active material (Si), which affects the effective mass and hence the mobility of the charge carrier. ^35–37) Such a bending-related variation in device performance could be solved by adding an encapsulation layer on top of the final device or by placing the device in the neutral plane. ^27,38) This could enhance the bendability, device stability and also resolve the slight variation of the electrical properties under bending conditions. ²⁷⁾

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The temperature dependence device stability is also studied in this work [Fig. 4]. Before we measured the transfer characteristics, the gate leakage current was monitored at different temperatures of the present device under investigation. This was performed to evaluate the dielectric stability at different temperatures. The mechanical robustness of the RT deposited SiN_x under different bending conditions was tested and reported in our previous work. ⁶⁾ In this work, we have studied temperature-dependent stability. As shown in Fig. 4(a), there is one order decrease in gate leakage current from 3 nA 0.3 nA at 5 V_GS when the temperature was increased from 15 °C to 90 °C. Although there is variation in leakage current, the values remain very low which confirms the high quality, and robustness of the RT deposited dielectric at a wide temperature range. Next, transfer scans [in the forward (+5 to −2 V_GS) and reverse (−2 to +5 V_GS) direction] were obtained at different temperatures (15 °C–90 °C with a step of 5 °C), as shown in Fig. 4(b). Important FET parameters were extracted using temperature varying transfer scans and are shown in different figure panels of Fig. 4. As can be seen in Fig. 4(b), the I_on of the device showed a sharp decrease after 35 °C with a stepwise increase in temperature. Similarly, I_off showed a slight decrease with an increase in temperature. This could be explained through the increase of scattering events (acoustic-phonon assisted and Coulombic) in the channel and/or at the semiconductor/dielectric interface, which degrades the charge transport efficiency. ³⁹⁾ In fact, the gain in kinetic energy of the charge carrier, with increasing temperature, alters two distinct phenomena that could affect the charge transport in FETs (in the range of temperature we have performed measurements): (i) scattering events in the channel and/or channel/dielectric interface, and (ii) increase of thermionic current. Which one of these will dominate the charge transport depends on the nature of MS contact in FETs. For Schottky contacted FETs, the I_on and I_off should show an increase in values. ³³⁾ This is because charge carriers acquire sufficiently high kinetic energy with increasing temperature to overcome the MS contact potential barrier and thus, the thermionic emission current component will increase. On the other hand, for an ideal ohmic contacted FETs, scattering events will dominate the charge transport as there will be a negligible increase in the thermionic emission part. As we showed above using the family of output scans, the FET device demonstrated the electrical behavior of a typical ohmic MS contact device which could explain the negative temperature dependence of FET current with temperature. To gain further insight on the decrease in I_on, we have analyzed other important FET parameters including SS, V_T, and hysteresis. The change in SS with temperature change is shown in Fig. 4(d). This figure reveals that the absolute SS value increases sharply above RT (1.1 V/dec) up to 45 °C–50 °C (1.5 V/dec). After 50 °C, SS saturates, remains constant until 70 °C, and shows slight degradation after that. It is well known that the SS of a FET device is largely affected by the interface (channel/dielectric) trap charge density. Also, these interface charges lead to a shift in FET threshold voltage. To correlate the change in SS trend to interface traps, we have calculated the magnitude shift of V_T with temperature [Fig. 4(e)]. The data in Fig. 4(e) shows a similar trend like SS change with temperature. Accordingly, both SS and V_T change can be correlated to the transfer of mobile charges to immobile trapping states at the semiconductor/insulator interface. Finally, we have monitored the magnitude of these interface charges by calculating the hysteresis value (change in V_T of forward and reverse transfer scan) at each temperature [Fig. 4(f)]. As expected, after 35 °C, there is a sharp increase of the hysteresis up to 50 °C–55 °C and then it saturates. The analyzed data shows a significant increase in the interface trap density above 30 °C–35 °C which leads to an increase in the scattering events at the channel/dielectric interface. Thus, the sharp decrease in the device on-current after 35 °C could be related to the thermal activation of interface traps that degrade the charge transport.

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