Distinguishing capture cross-section parameter between GIDL erase compact model and TCAD

A compact model of 3D NAND enables simulation at circuit- or system-level. Although a compact model for gate-induced-drain-leakage (GIDL)-assisted erase was proposed in a previous study, it is difficult to use practically because it has not been properly validated. In particular, a capture cross-section (CCS) value that is far from the real value is used. Furthermore, it does not consider the latest device structure and its operation. In this paper, a conventional GIDL-assisted erase compact model is validated using TCAD and has been improved more practically. It is confirmed that we should distinguish between CCS in TCAD and the compact model due to their differences. Based on their physical differences, an equation that can interconvert them is proposed and the model is successfully validated with proper CCS. Finally, the advanced GIDL-assisted erase compact model considering a tapered angle, single-side injection and word-line voltage is suggested.

Compact models for 3D NAND have been constantly developed because they can offer system-or circuit-level analysis, which cannot be rapidly accomplished by technology computer-aided design (TCAD). [10][11][12][13][14] These compact models are generally validated using TCAD or experimental data . 10,12,13) In particular, in the early stages of product development without any experimental data, TCAD is used to validate a compact model and to extract the required model parameters. Figure 1(a) shows a conventional GIDL-assisted erase compact model (in short, GIDL erase compact model). 12) However, the conventional model in Fig. 1(a) is difficult to use practically for two reasons. First, the model is not validated or calibrated against experimental data or TCAD. Second, it does not consider the latest device issues and its operation (tapered structure, double stacking and CUA structure).
In this study, to make the model more practical, we validate the conventional GIDL erase compact model using TCAD and improve it to include issues and operations of the latest device. In Sect. 2, model validation is attempted through TCAD before improving the conventional model. Through the validation process, it is confirmed that the compact model and TCAD results show severe disagreement in spite of the same tunneling current and capture crosssection (CCS). The cause of the disagreement and the way to obtain a proper CCS for the compact model are discussed using simple silicon-oxide-nitride-oxide-silicon (SONOS) structure. In Sect. 3, an advanced compact model considering a tapered angle, single-side injection and word-line (WL) voltage is suggested.

Description of a conventional GIDL erase model
The conventional model in Fig. 1(a) is modeling erase operation using combination of a GIDL compact model (GIDL circuit) 13) and a semi-analytical erase model (cell circuit). 12) It models half of a symmetric 3D NAND string structure with N WL WLs. Therefore, it includes one bitline (BL), one select gate (SG) stack and 1 2 N WL WLs. I GIDL represents the band-to-band tunneling current between the BL and SG. I , h I h,r and I h,t represent the hole tunneling current, hole recombination current and hole trapping current in a unit cell, respectively. V n+ represents the built-in potential. Figure 2(b) shows capacitances used in the model on a cross-section of the string near the SG. The potential of the hole accumulated region (orange region) is considered to be constant as V B regardless of its position. V N represents the potential at the n + −n junction (boundary between the BL and channel). The hole accumulated region is coupled by C NB to the depletion layer of n + region. L x is the length of the depleted region under the SG. C dep represents the capacitance of the depletion layer of the n + region. C f,out , C f,in and C f,B are fringing capacitances. C ono is the capacitance per unit length of the O/N/O layer. C G1 represents capacitance between the channel and middle of the nitride layer in a unit cell, and C G2 represents the capacitance between the WL and the middle of the nitride layer in a unit cell. Calculations for I GIDL and the capacitances are introduced in Ref. 13. Figure 2 schematically shows the semi-analytical erase model used in Fig. 1(a). Holes are injected into nitride by Fowler-Nordheim (FN) tunneling I . h ( ) Then, they are recombined (I h,r ) with electrons or trapped (I h,t ). Electrons are emitted by Poole-Frenkel (PF) emission (I e ). The following differential equations represent this mechanism: 12,15) t,e n t,h and n total,h represent concentrations of trapped electrons, trapped holes and total hole traps, respectively. e n is the emission rate calculated using a PF equation. 16) J h is hole FN tunneling current density. s s and  tunneling in the compact model. 17,18) The electron trap is set at 1.5 eV below the conduction band, and its concentration is 5 × 10 19 cm −3 . Figure 3 shows the assumed simple SONOS structures to observe the capture mechanism in TCAD. Heavily p-doped silicon is commonly used for the gate, drain and source. This is done to make analysis simple by eliminating the initial potential differences between them. Monocrystalline channel is assumed. Shockley-Read-Hall recombination and a nonlocal band-to-band tunneling model is assumed in the silicon channel. The nonlocal tunneling model in TCAD is used to simulate charge exchange at the nitride layer. The electron tunneling from the gate is ignored, as assumed in the semi-analytical erase model. 12) The tunneling mass of the hole in oxide (m h,ox *) is assumed to be 0.5m 0 (m 0 is free electron mass) and the tunneling barrier is assumed to be 4eV. 19,20) The energy level of the acceptor trap and donor trap are set at 1.5 and 2.5 eV below the conduction band of nitride, and their concentrations are 5 × 10 19 cm −3 and 3 × 10 19 cm −3 , respectively . 12,21) Constant CCS values are assumed for holes and electrons in TCAD (p0 = 0 in J-model). 22) 2.3. Different definition of CCS between TCAD and the compact model As shown in Fig. 4, the nonlocal tunneling model in TCAD and the FN tunneling model in the compact model show similar tunneling current for the same electric field. However, the results show that there are significant differences between the compact model and TCAD, as shown in Fig. 5. The   Disagreement is due to the different definition of CCS. Figure 6 compares capture mechanisms of TCAD and the compact model. In TCAD, CCS is defined for holes that have already been injected and remained on the valance band of nitride, whereas the compact model defines it for holes that are tunneling into nitride. Therefore, CCS in TCAD and compact models should be distinguished. From this section onwards, CCS in TCAD will be expressed as s , T and CCS in the compact model will be expressed as s .

TCAD simulation setup for validation
C Since s h and s r in Sect. 2.2 are defined in the compact model, they should be denoted as s C h , and s .  s T and s C can be interconverted considering their physical meaning. In TCAD, the capture rate is calculated as follows: 22,23) where s T is the CCS for TCAD, v th p is thermal velocity of holes (1.56 × 10 7 cm s −1 is used in this study), and p is the concentration of holes on the nitride valance band. As shown in Eq. (3), s T is defined for holes in the valance band of nitride.
On the other hand, considering Eqs. (1) and (2), the capture rate can be calculated as follows: where s C is the CCS for the compact model. s C is being defined for tunneling current density in the compact model. Therefore, properly converted CCS should be used to compare the results of TCAD and the compact model. If the same capture rate is assumed considering the same structure, we can obtain their relation as follows (i.e. supposing Eqs. k is the fitting parameter. Considering that q and v th p are constants, the CR depends on the ratio between the hole concentration in the valance band and the tunneling hole  , and s C r , in the compact model should be set CR times larger than s T h , and s T r , in TCAD. Figure 7 shows the result of Eq. (5) using extracted p and J h from TCAD for two cases. This shows that s C is approximately 2.1 × 10 5 times larger than s T in the given condition. Figure 8 shows the results of TCAD and the compact model with a converted CCS, as calculated in Fig. 7. The same CCS value is used for both recombining and hole trapping. With converted CCS, compact model results show good agreement with TCAD results for I D and ΔV T. However, when the CCS exceeds a critical value, erase characteristics are not affected by the CCS anymore, neither in TCAD nor in the compact model. Figure 9 shows the cross-section of half of the assumed 3D NAND string structure for GIDL erase. Ten WLs, two selectlines (DSL and SSL), heavily n-doped BL and sourceline (SL) are assumed for the full string. The WL length is reduced to 50 nm, and a lightly n-doped channel with macaroni structure is used. The other physical conditions are the same as in the previous simple SONOS structure. Although the actual 3D NAND channel is made of a polycrystalline silicon channel, 24,25) a monocrystalline silicon channel is assumed in the conventional model and in this paper. This is not only for simplicity of the compact model, but for consideration of the significantly reduced number of polysilicon grains along the string. [26][27][28] Figure 10 compares the results of TCAD and those of the GIDL erase compact model (Fig. 1). It is confirmed that the transient results of I BL and ΔV T of the compact model are in good agreement with the results of TCAD. Unlike in a simple SONOS structure, two current peaks appear, as shown in Fig. 10(a). This is because GIDL current occurs at DSL before FN tunneling current occurs at WL. 12)

Advanced erase compact model
The compact model validated in Sect. 2 assumed a constant channel radius (no tapered angle). In addition, it assumed symmetric structure and the same GIDL injection current from DSL and SSL. However, these conditions are far from the actual 3D NAND string. Figure 11 schematically shows a   The Japan Society of Applied Physics by IOP Publishing Ltd more realistic 3D NAND string structure. A string consists of two stacks, an upper stack and a lower stack. It has a tapered angle due to the limitation of the etch process. [29][30][31][32] Unlike the model in Fig. 1(a), single-side injection (GIDL injection only from DSL) is assumed in this structure. This is the result of considering the recent operation of 3D NAND with CUA structure.
The tapered structure causes variations in the dimension parameters of cells in the same string. Each cell should be modeled to have different C G1, C G2, C fB , I c , I e and I h . Therefore, to model the string that has N WL WLs, tapered string structure and single-side injection voltage scheme, one GIDL circuit and N WL cell circuits are required, as shown in Fig. 12. However, this model causes high computing cost because differential equations [Eqs. (1) and (2)] should be solved N WL times to simulate N WL -layer structure. Therefore, we propose the model in Fig. 13 to increase the simulation efficiency by reducing the number of differential equations to be solved. Figure 13 shows the advanced compact model considering a tapered angle, single-side injection and WL voltage. The advanced model assumes that the cells, except for the top and bottom cells in each stack, have the same size as the cell located at the center of the stack (mid cell). Therefore, the model consists of a total of four circuits. Each circuit represents GIDL, two top cells (one from the upper stack and the other from the lower stack), two bottom cells and (N WL -4) mid cells. The GIDL circuit is the same as the conventional model. C G1,top , C G2,top , C fB,top , I c,top , I e,top and I h,top represent the changed C G1 , C G2 , C fB , I c , I e and I h of the top cell due to the tapered angle. Components in other cell circuits also represent changed C G1 , C G2 , C fB , I c , I e and I h according to their position (mid or bottom). This simple modeling is based on the fact that the distance from the GIDL injection point does not affect the erase performance of the cell. 8) This also means that users of this model can further subdivide cells and add them to the channel node for more precise analysis. Although the simulation time can vary depending on the number of cell circuits, the compact model shows overwhelmingly fast analysis compared to TCAD, which takes tens or hundreds of hours or more. In addition, the voltage source (V WL ) is added to the cell circuit to consider the WL voltage. In recent NAND operation, different WL voltages have been applied depending on the positions of the cells. This is to suppress the cell-to-cell variation caused by the tapered angle. This operation can be analyzed by using our model.

Conclusion
TCAD defines CCS for holes below the valance band of nitride. On the other hand, the conventional compact model defines it for tunneling hole current density. Therefore, we should distinguish between the CCS of TCAD and that of the compact model. Proper CCS for the compact model can be