Single-trap phenomena stochastic switching for noise suppression in nanowire FET biosensors

LG Si NW FET biosensors were fabricated using silicon-on-insulator (SOI) wafers with 50 nm thin 〈100〉-oriented Si layer and 145 nm thick buried oxide layer. SOI wafers were commercially purchased from SOITEC, France. Widths of designed and fabricated NWs are in the range from 70 to 500 nm and lengths vary in the range from 100 nm to 4 μm. The detailed steps involved in the fabrication process of Si NW structures were previously reported and can be found elsewhere. ^2,29) Briefly, before NW patterning, SOI wafers were covered with a 20 nm thick SiO₂ layer using PECVD to serve as a layer for hard mask formation employing reactive ion etching. The NW pattern was defined using e-beam lithography and mesa structures were defined utilizing photolithography. After this, structures were transferred into the active silicon layer of SOI wafers using wet chemical etching in tetramethylammonium hydroxide (TMAH) solution. Afterward, ion implantation was performed with Boron dopants to create accumulation mode FETs (p⁺–p–p⁺) transistor structures. Then, an 8 nm thin SiO₂ layer was thermally grown on the NWs to serve as the gate dielectric and protect the conductive channel of transistor-based biosensors from the liquid environment. The metallization process was then performed by sputtering of a metal stack consisting of 5 nm TiN and 200 nm of Al followed by the lift-off patterning and annealing process. To protect metal leads against the liquid environment, the structures were passivated with a polyimide layer. The access of the liquid solution to Si NWs was provided by patterning the passivation layer with photolithography. After the fabrication process wafers were cut into chips which were further wire-bonded, encapsulated with polydimethylsiloxane (PDMS), and used for the experiments. All the fabrication steps were performed at the Helmholz Nano Facility of Forschungszentrum Jülich.

Noise characterization of the fabricated NW devices was performed using a modernized and fully automated ultralow-noise measurement setup developed in-house. A detailed description of the setup can be found in Ref. 29. Briefly, the gate-source and drain-source biases are applied to the device-under-test (DUT) using a battery-operated and fully automated voltage supply system which allows precise electrical biasing of DUT with the accuracy approaching 1 mV. The Agilent U2542A simultaneous data acquisition analog input channels in polling mode configuration are used to control and measure all the voltages applied. However, the Agilent voltmeters are disconnected from the noise measurement circuit during the noise data acquisition to avoid any impact on noise measurement results. The noise measurements are performed using an analog input channel in the AC configuration. First, the signal (time-dependent source-drain voltage fluctuations) is preamplified using an ultralow-noise homemade pre-amplifier with a gain of 172. Then, the signal is passed through the commercial amplifier ITHACO 1201 with a variable gain from 1 to 10k and further amplified with a low-noise general-purpose programmable-gain amplifier PGA-103. Note, to exclude the influence of the amplification cascade the measurement system has been calibrated before noise measurements. At maximum amplification, the noise level of the noise measurement setup is low as $16\,{\rm{nV}}/\sqrt{{\rm{Hz}}}\,\,$at 10 Hz. Afterward, the signal is filtered using digitally controlled antialiasing continuous-time filter LTC 1564. Finally, the measured time-dependent source-drain voltage fluctuations are transferred to a PC via a high-speed USB 3.0 interface were then translated into a voltage power spectral density. As a result, the noise measurement setup allows acquiring the noise spectra in the frequency range from 1 Hz to 100 kHz and time-traces of the voltage fluctuations with the sampling rate up to 500 kHz. To obtain reliable noise characteristics of DUT, noise measurements are performed inside a metal Faraday cage to shield against external electromagnetic radiation and other parasitic disturbances.

To evaluate the g-factor noise from the RTS time trace, we proposed and employed a so-called sliding window algorithm that is schematically demonstrated in Fig. 2. More precisely, we extract g-factor g(t) over a given time window Θ directly from the time distribution of RTS voltage fluctuations. Then, by sliding the window along with the RTS time trace, a new time trace with the trap occupancy factor fluctuations in time is constructed. Finally, the time-domain data of g-factor noise can be then translated into a frequency spectrum resulting in the power spectral density ${S}_{g}.$

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In this study, we focus on the noise suppression effect offered by STP in nanoscale devices. Therefore, only NW FETs demonstrating RTS noise are of interest. Figures 3(a)–3(d) show typical RTS time traces as time-dependent fluctuations in the drain current measured on 100 nm wide and 200 nm long Si NW FET that was operated at a constant drain-source bias of −20 mV and different liquid-gate voltages. The RTS measurements were performed in a physiological phosphate-buffered-saline (PBS) solution with 10  mM concentration and pH = 7.4 at room temperature. The liquid-gate potential was applied using Ag/AgCl reference electrode. The data clearly demonstrate that STP is well-pronounced in the tested device and dominates over all the other noise sources when a single trap is electrically active near the conductive channel of the NW FET. As a result of STP, the drain current of the nanostructure fluctuates between two distinct levels that correspond to the "capture" and "emission" states of the single trap. Clear two-state switching kinetic due to STP can be further evident from the corresponding amplitude histograms that are also shown in Figs. 3(a)–3(d). An analysis method based on a hidden Markov model ^30,31) was then applied to extract the single-trap states for measured RTS time traces.

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The mean duration of stay of a charge carrier in the capture and the following emission states are usually characterized by the average emission (${\tau }_{e}$) and capture (${\tau }_{c}$) time constants, respectively. The corresponding average capture and emission time constants characterizing the registered RTS process are shown in Fig. 4(a) as a function of the liquid-gate voltage applied. As can be seen in Fig. 4(a), the average ${\tau }_{e}$ remains about constant in the range of the liquid-gate voltage applied, while the average ${\tau }_{c}$ displays a superlinear dependence on ${V}_{{\rm{L}}{\rm{G}}}$ in the semilogarithmic scale suggesting a strong dependence of the RTS capture dynamic on surface potential controlled by the liquid gate. It should be noted that such behavior of RTS characteristic time constants is typical for LG NW FETs. ^18,20)

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Figure 4(b) displays the liquid-gate voltage dependence of trap occupancy probability, g, calculated as

$$\begin{eqnarray}&&g=\displaystyle \frac{{\tau }_{e}}{{\tau }_{e}+{\tau }_{c}},\end{eqnarray} \tag{ 1 }$$

where ${\tau }_{e}$ is the average emission time of a charge carrier from the trap and ${\tau }_{c}$ is the average time for a random charge carrier to be captured by the trap.

For STP in LG NW FETs, the gate-voltage dependence of g can be explained by a widened Fermi-type distribution due to the partial potential drop at the trap depth. Figure 4(b) shows that at low liquid-gate voltages, the probability of a charge carrier to be captured by the trap is small, while the latter is fully occupied at high ${V}_{{\rm{L}}{\rm{G}}}.$ At $g=0.5$ which corresponds to the case when the trap energy level coincides with the Fermi level of the system, the probability of the trap to be occupied is equal to 50% and therefore, the number of switching events between capture and emission states within the measured period of time is maximized. As a result, the RTS noise is also maximized when $g=0.5$ as can be evident in Fig. 4(b). However, below we show that if g is monitored as a signal, RTS noise becomes an object of increasing interest providing an excellent opportunity for noise suppression in an approach similar to the stochastic resonance.

Figure 5 shows the noise spectra of g-factor fluctuations calculated from the RTS voltage fluctuations at different liquid-gate voltages using the above-described sliding window approach. The g-factor time traces and corresponding g-factor noise spectra were obtained for the time window of $\theta =10\,s$ in this case. Figure 6(a) shows the gate voltage dependence of the evaluated g-factor noise, ${S}_{g}$ that was taken at the frequency of 10 Hz. As can be seen from Fig. 6(a), the maximum of the g-factor noise was observed at ${V}_{{\rm{L}}{\rm{G}}}=-0.80\,{\rm{V}},$ which corresponds to the case when $g=0.5.$ At this condition, the number of trapping/detrapping events is maximized within a given time window resulting in the maximum of g-factor noise when calculating the trap occupancy probability. It should be emphasized that calculated ${S}_{g}$ noise as a function of liquid-gate voltage follows the gate voltage dependence of the g-factor slope squared [Fig. 6(a)]. The fact additionally supports the selection of optimal gate voltage at −0.8 V to utilize the full potential of STP for noise suppression.

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To compare the noise caused by the current fluctuations in the channel and fluctuations of the trap occupancy factor, we calculate an equivalent input-referred g-factor noise, ${S}_{gg}$ similarly as for the input-referred voltage noise:

$$\begin{eqnarray}&&{S}_{gg}=\displaystyle \frac{{S}_{g}}{{g}_{g}^{2}},\end{eqnarray} \tag{ 2 }$$

where ${S}_{g}$ is the g-factor PSD and ${g}_{g}\,\,$is the g-factor derivative calculated as $\tfrac{\partial g}{\partial {V}_{{\rm{L}}{\rm{G}}}}.$ The input-referred g-factor noise at 10 Hz calculated using Eq. (2) is shown in Fig. 6(b) as a function of the liquid-gate voltage. For the comparison, Fig. 6(b) displays also the input-referred voltage noise that was measured for the tested 100 nm wide and 200 nm long LG Si NW FET demonstrating pronounced two-level RTS noise. As can be seen in Fig. 6(b), the ${S}_{gg}$ noise calculated for the time window $\theta =10\,{\rm{s}}$ is considerably lower than the measured voltage noise. This reveals that $\theta =10\,{\rm{s}}$ is a large enough time window for the meaningful statistical evaluation of the g-factor. Thus, these results clearly demonstrate that by monitoring the g-factor as a signal, the low-frequency noise in the nanosensors exploiting STP can, in fact, be suppressed by the selection of optimized conditions. Remarkably, the lower ${S}_{gg}$ noise compared to the voltage noise level was obtained for the entire range of the applied liquid-gate voltages [Fig. 6(b)] due to electrically active single trap generating pronounced two-level RTS signal. The latter is an important parameter to improve sensitivity and SNR in NW FET biosensors.