Improving mobility of silicon metal-oxide–semiconductor devices for quantum dots by high vacuum activation annealing

With rapid development of silicon quantum devices, quantum dots fabricated on silicon have become one of the most promising candidates for quantum computing [1]. In particular, employing nuclear spin-free ²⁸Si [2], which is abundant in natural silicon, this kind of structure enables high fidelity control of spin qubits by offering long coherence times [3–7]. High-quality silicon-based material is necessary for the implementation of fault-tolerant quantum computing [8,9]. As silicon metal-oxide semiconductors (MOS) are widely used in commercial electronic devices, specifically for their stable performances [10], leveraging complementary MOS (CMOS) technology to scale up spin-qubit manipulations is an alternative solution. Possible applications of commercial MOS technology in the field of spin qubits have been identified [11,12]. Therefore, using commercial silicon wafers to fabricate high-quality quantum dots is an important issue.

As a metric for assessing the quality of the semiconductor/oxide interface, high mobility indicates low disorder and material uniformity at the confining interfaces. Quantum dots for spin qubits usually operate at a low density, where the disorder and material uniformity affect the electrical property significantly. The increasing of the mobility suggests an enhancement of the quality of silicon wafers, which is beneficial for obtaining reproducible quantum dots [13]. Early studies on Si MOS show the results of quantum dot devices with relative low-mobility wafers [14,15]. For example, a gate-defined quantum dot has been achieved in intrinsic silicon with the mobility of $0.5 \ \text{m}^{2}\text{/(V}\cdot \text{s)}$ [16]. Researchers are trying to further improve electron mobility by reducing defect at the SiO₂/Si interface. A recent research shows a peak mobility of $1.4\ \text{m}^{2}\text{/(V}\cdot \text{s)}$ which can be extended to $2.3\ \text{m}^{2}\text{/(V}\cdot \text{s)}$ by forming gas annealing [17]. To determine the dominant sources of disorder in Si MOS devices, investigations on the magneto-transport of Hall bars of these structures were performed [18–20]. By analysing the mobility $(\mu)$ as a function of density (n) and quantum lifetime $({\tau }_{q})$, the dominant source limiting mobility was identified [21]. Similar experiments were performed on GaAs/AlGaAs heterostructure [22–24], Si MOSFET [25], and Si/SiGe heterostructure [26–28]. Based on these findings, several means to reduce disorder to improve mobility in Si MOS structures were found, including using strained silicon and annealing samples in N₂ environments [29,30].

In this letter, we study silicon MOS Hall bars fabricated using commercial silicon wafers with different activation environments and growth methods. We obtain a peak mobility of $1.5\ \text{m}^{2}\text{/(V}\cdot \text{s)}$, along with a critical electron density of $2.6\times 10^{11}\ \text{cm}^{-2}$, in a commercial silicon wafer by using high vacuum annealing during implantation activation in addition to forming gas annealing. The mobility of two-dimensional electron gas (2DEG) is increased by a factor of two by using activation annealing in high vacuum rather than in nitrogen atmosphere. We find that the dominant scattering mechanism that limits the peak mobility is short-range scattering, and the effect of phonon scattering can be ignored below 1.5 K. Furthermore, a single quantum dot is fabricated to demonstrate the possibility of producing high-quality quantum dots using wafers with the improved mobility.

The Hall bars and quantum dots devices are fabricated on 8 inch commercial silicon wafers. The wafers consist of a 10 nm SiO₂ cap layer formed by thermal oxidation and a $725\ \mu \text{m}$ Si substrate. All batches of samples are fabricated using the same process steps except for different annealing conditions. The standard fabrication process for sample preparation is as follows: ion implantation (phosphorus) with a dose of $2\times 10^{15}\ \text{cm}^{-2}$; application of an annealing process for ion activation at the temperature of $1050\ ^{\circ}\text{C}$ in either high vacuum $({<}10^{-3}\ \text{Pa})$ or N₂ atmosphere; fabrication of Ohmic contact regions using buffered oxide etching and evaporation of Ti/Au; and deposition of 30 nm thick aluminium oxide (Al₂O₃) as gate insulator at the temperature of $300\ ^{\circ}\text{C}$. After that, a layer of Al above the Al₂O₃ is added to define the conductive channel. A final annealing with forming gas (15% H₂ and 85% N₂) for 30 min at the temperature of $400\ ^{\circ}\text{C}$ is performed to reduce the defects induced by e-beam lithography and metal evaporation [17,31].

A channel length of ${L} = 300\ \mu \text{m}$ and width of ${W} = 100\ \mu \text{m}$ are chosen for the Hall bars on commercial silicon wafers (fig. 1(a)). The inset of fig. 1(b) shows a cross-section schematic of the device. The top gate (faint yellow area) is for applying a DC voltage V_t to accumulate the 2DEG at the Si/SiO₂ interface to generate a current with a voltage ${V}_{t}>1.89\ \text{V}$. The standard "turn on" curve of the current (fig. 1(b)) saturates at ${V}_{t}\sim3\ \text{V}$ with a total resistivity of $2.5\ \text{k }\Omega$ at 4.2 K.

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Then, low-temperature transport measurements are performed at temperatures $0.24\ \text{K}<\mathrm{T}<1.5\ \text{K}$ in a He-3 refrigerator using an SR830 lock-in amplifier at a frequency of ${\sim}70.23\ \text{Hz}$ to reveal the properties of our devices. In our devices, the density of the 2DEGs shows a linear dependence on the top gate voltage, with a typical curve shown in fig. 2(a). Meanwhile, the mobility of the 2DEGs also changes as the gate voltage varies. The dependence of the mobility $(\mu )$ on the density (n) under different top gate voltages is presented in fig. 2(b). In the low-density $(n<6\times 10^{11}\ \text{cm}^{-2})$ regime, the curve roughly follows a $\mu \propto n^{3}$ trend, corresponding to the effect of fixed charges [32]. The mobility decreases when further increasing the density $(n>1\times 10^{12}\ \text{cm}^{-2})$ due to interface roughness scattering at the Si/SiO₂ interface [33]. The mobility reaches a peak value of $1.5\ \text{m}^{2}/(\ \text{V }\cdot \text{s})$ at a density of $9.06\times 10^{11}\ \text{cm}^{-2}$.

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In fig. 2(c), at the peak mobility, Hall transport measurements are performed by mapping the longitudinal resistivity $\rho_{xx}$ and the transverse resistivity $\rho_{xy}$ under different magnetic fields. The onset of magnetic field for Shubnikov-de Hass (SdH) oscillations is 0.7 T ($\textit{B}_{\mathrm{SdH}}$). When the magnetic field is above $\textit{B}_{\mathrm{SdH}}$, the transverse resistivity $\rho_{xy}$ shows plateaus with an even filling factor $\nu =4,6,8,\ldots$ while oscillations of the longitudinal resistivity $\rho_{xx}$ are observed. The transverse resistivity $\rho_{xy}$ plateaus with odd filling factor are invisible as a result of valley degeneracy. Spins split at a higher magnetic field of ${B}_{s}=3.1\mathrm{T}({\nu } = 10)$, corresponding to a Zeeman splitting energy of ${E}_{z}={g}{\mu }_{B}{B}_{s}=360\ \mu \text{eV}$, where $\textit{g} = 2$ is the electronic Lande factor and $\mu_{B}$ is the Bohr magneton.

In fig. 2(d), we obtain $\rho_{xx}$ as a function of magnetic field (B) from 1 T to 2 T. After subtracting the polynomial background and $\rho_{xx}(0)$ (the longitudinal resistivity at zero magnetic field), six oscillations $\Delta \rho_{xx}(B)=\rho_{xx}(B)-\rho_{xx}(0)$ vs. 1/B are plotted under different temperatures. The oscillations show a period of 4 in ν, consistent with two-fold valley degeneracy and two-fold spin degeneracy. The oscillations can be fitted perfectly using the formula [34]

$$\begin{equation} \Delta \rho_{xx}(B)=4\rho_{xx}(0)\cdot \cos \left(\frac{E_{F}}{\hslash \omega_{c}}\right)\cdot D(m^{*},T)\cdot \exp (-\pi /\omega_{c}\tau_{q}), \end{equation} \tag{ 1 }$$

where $D(m^{*},T)$ is the Dingle factor, where at low field $D(m^{*},T)=\xi /\sinh \xi$, with $\xi =2\pi^{2}k_{B}T/\hslash \omega_{c}$, $\omega_{c}=eB/m^{*}$ is the cyclotron frequency, $m^{*}$ is the effective mass, k_B is Boltzmann's constant, $\tau_{q}$ is the quantum lifetime of the electrons and ℏ is the reduced Planck constant. When $\xi \gg 1$, the extrapolated amplitude for $\Delta \rho$ in eq. (1) can be used to obtain effective mass $m^{*}=0.19m_{0}$, which is consistent with the transverse effective mass of silicon in theory.

Figure 2(e) shows $\ln (\frac{\Delta \rho_{xx}(B)\cdot \sinh \xi }{\xi })$ as a function of $1/B$, from which the quantum lifetime values $\tau_{q}$ can be extracted. We find that $\tau_{q}$ is independent of temperature, similar to the transport lifetime $\tau_{t}=\frac{\mu \cdot m^{*}}{e}$, as shown in fig. 2(f). We note that this result differs from previous works on Si/SiGe heterostructure [28] and GaAs/AlGaAs heterostructures [24], where phonon scattering was non-negligible. In addition, the value of ${\tau }_{q} = 0.8$ ps implies a Landau-level broadening of $\Gamma =\frac{\hslash }{2{\tau }_{q}}=410\ \mu \text{eV}$, which is consistent with the reported value of $480\ \mu \text{eV}$ [13], giving the upper bound of valley splitting energy in our devices. For comparison, valley splitting energies range from 0.7 to $1.5\ \text{meV}$ in previous Si MOSFETs [35–38].

It is worth noting that the Dingle ratio $(\tau_{q}/\tau_{t})$ almost equals unity, indicating that the dominant scattering mechanism restricting the peak mobility of this sample (fig. 2(f)) is short-range scattering rather than long-range scattering. This result is in accordance with a previous work in which the fixed charges and defects at the SiO₂/Al₂O₃ or SiO₂/Si interfaces dominate the scattering [39]. The insensitivity of both $\tau_{q}$ and $\tau_{t}$ to temperature implies that phonon effects are not dominant here even if we cannot rule out other effects that limit the mobility of the wafers [40].

In fig. 3(a), by varying the gate voltage (V_t), $\rho_{xx}$ ($\textit{B}=0\ \text{T}$) as a function of density (n) is obtained. After changing the temperature, these curves feature a stable crossing point at a critical electron density (${n}_{c}=2.6\times 10^{11}\ \text{cm}^{-2}$), which is a signature of metal-insulator transition. The value of n_c in our MOS Hall bars is consistent with the previously reported value [41–44]. In fig. 3(b), the peak mobility and density for different parameter settings are listed. Data of hollow symbols are from devices using high vacuum $({<}10^{-3}\ \text{Pa})$ activation annealing, while those of solid symbols come from devices activated in nitrogen atmosphere. Moreover, different wafers, which can be used for quantum dots fabrication, are introduced to identify if there is any difference between intrinsic substrates (floating zone (FZ) grown wafers) and doped substrates (Czochralski (Cz) grown wafers), even both of them can be used for quantum dots fabrication [45–47]. Batches 1 and 2 are fabricated using Cz wafers, while batch 3 is fabricated with FZ wafers. Cz wafers are slightly boron (B+)-doped with a resistivity of $20\text{--}30\ \Omega \cdot \text{cm}$, whereas FZ wafers are intrinsic and undoped with a resistivity of approximately $10\ \text{k }\Omega \cdot \text{cm}$. Comparing those with the same wafer but under different annealing conditions, a higher peak mobility is clearly observed for the ones under high vacuum activation annealing instead of nitrogen atmosphere annealing. A peak mobility up to $1.5\ \text{m}^{2}\text{/(V}\cdot \text{s)}$ is obtained for batch 3. Overall, the peak mobility of the 2DEGs fabricated using FZ wafers is higher than that of the 2DEGs fabricated using Cz wafers here. We attribute this trend to fewer donors in FZ wafers than in Cz wafers. Considering dopant atoms, the background doping values of Cz wafers and FZ wafers are approximately $10^{14}\ \text{cm}^{-3}$ and $10^{12}\ \text{cm}^{-3}$, respectively. For FZ wafers, the possible effects from dopant atoms are relatively small. Additionally, for quantum dots in Si MOS, three kinds of charge transitions are usually considered, namely, $E'$ centres, P_b centres, and unintentional quantum dots [39]. For $E'$ centres, the effect is related to the fixed charges, typically arising from the interface between Al₂O₃ and SiO₂. This kind of defect is usually induced by radiation during e-beam evaporation and is usually located further from the quantum well. Such defects could be worsened when implementing e-beam lithography for smaller structures [31]. Another kind of defect, the P_b centre, is formed by a single dangling bond on silicon [48]. Previous experiments have identified that the most common defects of the P_b centre form at the interface between Si and SiO₂ [49]. The final annealing with H₂ is performed to passivate the P_b centres. Unintentional quantum dots are formed by strains between different materials [50], which is not discussed here. All of the effects would behave as disorders and they usually occur simultaneously. Mitigation of any of these effects will lead to an increase of electron mobility.

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In fig. 3(c), we focus on electron mobility's dependency on density for both high vacuum annealing activated and nitrogen atmosphere annealing activated devices. Taking batch 1 as an example, the device with high vacuum activation annealing has a higher mobility. The mobility at the same density is increased by a factor of two by replacing nitrogen atmosphere annealing with high vacuum activation annealing. The results in fig. 3(d) show that our improvement by high vacuum annealing is universal for both intrinsic substrates and boron-doped substrates. Additionally, samples of batch 3 have higher mobilities than those of batches 1 and 2 for both methods, which may possibly be attributed to strain releasing and diffusing of impurity atoms induced by high vacuum activation annealing. Overall, to achieve a higher peak mobility, high vacuum activation annealing is a promising solution and an FZ substrate is a better choice.

We demonstrate a single quantum dot using Cz wafers (batch 2) with an improved mobility of $1.2\ \text{m}^{2}\text{/(V }\cdot \text{s)}$ by high vacuum activation annealing and the result shows that the commercial wafers after our processing can be used for fabricating quantum dot devices. The quantum dot design was based on a double top-gated architecture, similar to previous work conducted on GaAs and Si [51,52]. This single quantum dot and quantum point contact structure is confined by six gates between the Al₂O₃ layer and SiO₂ layer. The structure of the planar gates is displayed in fig. 4(a). By detecting the charge sensing signal of the single dot, the standard stability diagram of the single dot can be obtained. In fig. 4(b), dozens of tunnelling lines are mapped by changing the gate voltages at G3 and G5. These parallel lines show a single dot behaviour. Moreover, the interval between two proximal lines gradually increases when lowering the gate voltages, corresponding to the change in the electron number in the dot. Clearly, these lines are not cut off by other lines arising from disorder. No impurities are involved in this regime. More than 15 consecutive Coulomb oscillations can be observed without visible parasitic dot effect. The collection of process described in the paper to improve the device mobility, in a long run, should help to improve the quality of Si MOS quantum dots.

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In conclusion, we perform the quantum transport characterizations on silicon MOS Hall bars using commercial silicon wafers. We report that high vacuum activation annealing helps to increase the mobility of 2DEGs by a factor of two, leading to a peak mobility of $1.5\ \text{m}^{2}\text{/(V }\cdot \text{s)}$. We find that high vacuum activation annealing and selection of FZ wafers are helpful to approach the higher mobility and the behavior of our single dot device is a good example of improving the mobility for high-quality quantum dot formation. For further improvement in quantum devices, more efforts are still needed to handle residual impurities and defects at the interface between Si and SiO₂. Our results may provide valuable insights into wafer optimization in silicon-based quantum computing.

This work was supported by the National Key Research and Development Program of China (Grant No. 2016YFA0301700), the National Natural Science Foundation of China (Grant Nos. 61674132, 11674300 and 11625419), the Strategic Priority Research Program of the CAS (Grant No. XDB24030601), and the Anhui Initiative in Quantum Information Technologies (Grant No. AHY080000), and this work was partially carried out at the USTC Center for Micro and Nanoscale Research and Fabrication.