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(Invited) Materials and Process Technologies for Scaling BEOL Interconnects

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© 2021 ECS - The Electrochemical Society
, , Citation Rinus Lee et al 2021 Meet. Abstr. MA2021-01 1004 DOI 10.1149/MA2021-01301004mtgabs

2151-2043/MA2021-01/30/1004

Abstract

Historically, complementary metal-oxide-semiconductor (CMOS) technology was driven by geometrical scaling of the front-end-of-line (FEOL) transistor but it has slowed down significantly in recent years. On the other hand, back-end-of-line (BEOL) interconnects are projected to continue scaling aggressively to meet power, performance and area targets in advanced nodes. In this paper, we will introduce and review BEOL interconnect options targeting sub-7nm metal pitch with an emphasis on materials and process technologies.

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10.1149/MA2021-01301004mtgabs