(G03 Best Paper Award Winner) Si-Passivated Ge Gate Sacks with Low Interface State and Oxide Trap Densities Using Thulium Silicate

Germanium is considered as a high mobility channel material for its potential to be introduced in future CMOS technology nodes. Ge surface passivation with a thin silicon layer (Si-cap) has been shown to be efficient for pFETs because of a sufficient valence band offset between Ge and Si-cap, which confines the holes in the Ge layer. Strained Ge pFinFETs outperforming Si pFinFETs due to four times higher mobility have been demonstrated using Si-cap process [1]. Interfacial defects can be further passivated with a high-pressure anneal in H₂ resulting in reduced sub-threshold swing and increased mobility in Ge nanowires [2]. Moreover, by using a Si-cap, Negative-bias temperature instability reliability is improved compared to GeO_x passivation because of the energy decoupling between holes and defects in SiO₂/HfO₂ gate stack [3]. However, a Si-cap process poses gate stack scalability issues because in order to achieve sufficient surface passivation, the Si-cap thickness cannot be scaled. An introduction of a high-k interfacial layer instead of a chemical oxide SiO₂ could potentially help to scale down equivalent oxide thickness. Integrating thulium silicate (TmSiO) as a replacement of the SiO₂ interfacial layer has been demonstrated on silicon, and a hole and electron mobility enhancement compared to SiO₂/HfO₂ gate stacks has been achieved for an equivalent oxide thickness (EOT) < 1 nm [4]. Moreover, we have previously displayed the compatibility of Tm₂O₃ with Ge by demonstrating GeO_x/Tm₂O₃ gate stacks with interface state density D_it < 5·10¹¹ eV^-1cm^-2 [5]. In this work, we integrate TmSiO with a Si-cap process to achieve D_it comparable to GeO₂ passivation.

In order to evaluate Ge/Si/TmSiO interfaces, MOS capacitors (MOSCAPs) were fabricated on n-type Ge strain relaxed buffers epitaxially grown on n-type Si wafers in a two-step process using GeH₄ precursor [6]. Si-caps of different thicknesses were grown at 400 °C using Si₂H₆. Si growth was confirmed by ellipsometry spectroscopy and testing that the surface is hydrophobic. While trying to keep the Si-cap exposure to air to a minimum, 400 nm PECVD SiO₂ was deposited and active areas were defined. After removing the remaining SiO₂ from the active areas with 1 % HF, Tm₂O₃ was deposited by atomic layer deposition (ALD) at 225 °C. Rapid thermal anneal at 550 °C for 60 s in N₂ was then employed to form TmSiO layer. High-k HfO₂ was deposited by ALD at 350 °C followed by a post deposition anneal in O₃ for 10 min. TiN gate metal was deposited at 425 °C by ALD and 500 nm Al was deposited by sputtering for probing purposes. After patterning, the samples were subjected to a forming gas anneal of 10% H₂ in N₂ at 400 °C for 30 min. Reference MOSCAPs with Ge/GeO_x/Tm₂O₃/HfO₂ gate stacks were also fabricated as described in [5] with addition of ALD HfO₂.

Interface state density in the midgap of Ge/Si/TmSiO/Tm₂O₃/HfO₂ gate stacks was evaluated by CV measurements where measured CV characteristics where compared to calculated ones assuming a parabolic D_it distribution. D_it highly depends on Si-cap thickness, as displayed in Fig. 1. An optimal Si-cap thickness corresponding to 40-50 min deposition time provides D_it at midgap ~5·10¹¹ cm^-2eV^-1 at CET of 4 nm. Reference MOSCAPs with Ge/GeO_x/Tm₂O₃/HfO₂ gates exhibit similar D_it of 4-5·10¹¹ cm^-2eV^-1. Interface state density distribution within the band gap of Ge/Si/TmSiO interface with 40 min Si-cap deposition time was evaluated using the conductance method at different temperatures and is displayed in Fig. 2. D_it in the midgap is in agreement with the results obtained from CV measurements, and increases towards the valence and conduction band edges. The oxide trapped charge Q_ox of 2.5·10¹⁰ cm^-2 (40 times lower than in the Ge reference devices without Si-cap) was determined from CV measurements and corresponds to only 5 mV hysteresis showing the potential of superior reliability.

A Si-cap process with high-k TmSiO interface has been demonstrated on Ge MOS devices. A low D_it comparable to GeO_x passivation has been shown. In addition, devices with TmSiO potentially have a superior reliability vs GeO_x devices due to low oxide trapped charge density.

References:

[1] J. Mitard et al., Dig. Tech. Pap. - Symp. VLSI Technol., vol. 2016–Septe, 1–2, 2016.

[2] H. Arimura et al., 2017 Symposium on VLSI Technology, 2017, T196–T197.

[3] J. Franco et al., 2013 Int. Electron Devices Meet., 397–400, 2013.

[4] E. Dentoni Litta et al., Eur. Solid-State Device Res. Conf., vol. 2, 155–158, 2013.

[5] L. Žurauskaitė et al., ECS Trans., vol. 86, no. 7, 67–73, Jul. 2018.

[6] A. Abedin et al., ECS Trans., vol. 75, no. 8, 615–621, 2016.

Figure 1