A Comparative Study and Analysis of Various Interconnects for Very Large-Scale Integration

Various interconnects utilised in very large-scale integration in this work. The expanding use of portable devices has increased the demand for low-power circuit design. Sub-threshold circuits are the greatest option to address the demand for even more-low power. However, decreased performance and increased variability are the main problems with sub-threshold circuits. Furthermore, global interconnects have a significant impact on the performance and power dissipation of sub-threshold circuits. For future VLSI circuit applications, interconnect is a brand-new and very promising alternative that has to have its propagation latency and stability analysed in order to substantiate its claim that it can replace existing interconnect designs.

Due to the aforementioned challenges, developing global interconnects is one of the key element factors for creating high-performance devices.Scaling has produced faster, denser processors with everincreasing capability over the past 30 years.As technology is pushed down below 100 nm, device performance considerably increases while connection performance sharply declines.Interconnects were not previously taken into consideration while developing IC circuits; only device models were.Interconnects in the recent nanometre regime are divided into three levels based on their lengths: local, intermediate, and global.Global interconnects comprise the first and second levels, semiglobal/intermediate interconnects the third and fourth, and local interconnects the lowest shown in Fig. 1.The metal fillings that allow for inter-level wire connections are called vias.
Dielectric is stacked on interconnects, materials between two layers or a transistor and a layer.Interlayer dielectrics (ILD) separate the wires from one level to another level, and inter-metal dielectrics (IMD) isolate them within the same level (Elgamel and Bayoumi 2003) When building a circuit in the sub-micron or nanometre range, the connecting component is the most crucial factor to take into account in order to improve performance and avoid some circuit errors.The connecting wires are subpar in real applications.Interconnect has a specific impact on signal integrity.Interconnect effects increasingly control device performance.These days, interconnects are bigger than devices.Al interconnects were used before to 2010.Between 2010 and 2015, cu with tungsten was in use.
The development of on-chip interconnects are listed in the above Table I, in that 14 nm, 10 nm and 7 nm technology was developed by Intel.5or 3 nm was developed by IMEC and less than 3 nm was established by TSMC.

Carbon Nanotube Interconnects
In a work on carbon nano tube bundle interconnects by M. Shefali et al, 1 they found that For SWCNT and MWCNT interconnects at various global interconnect lengths for 20 nm and 14 nm technology nodes, performance parameters such as crosstalk delay, power dissipation, power crosstalk delay product (PCDP) and crosstalk noise are calculated and compared.It is observed that, upon using different dielectric materials in CNT bundle interconnect, MWCNT bundle interconnects is performing better compared to SWCNT bundle interconnects at 20 nm and 14 nm technology nodes for all global interconnect lengths.
Power temperature product (PTP) is defined in a research by Femi Robert et al. 2 that discusses the carbon nano tube bundle interconnects' ability to withstand power.For interconnect lengths ranging from 500 m to 2000 m, the PTP is determined.Results indicate that square and triangular CNT bundles both have good power withstanding capacities.
P. Uma Sathyakam et al. 3 have presented a paper on a particle swarm optimization (PSO)-based optimal repeater number for different lengths of carbon nanotube (CNT) interconnects at 20 nm and 14 nm technology nodes.The optimal number of repeaters and the propagation delay for CNT interconnects with lengths ranging from 500 to 2000 m are found.Multi-walled carbon nanotubes (MWCNTs) have established as the start interconnect material for nanoelectronic integrated circuit (IC) designs, according to a publication by Sandha et al. 4 The findings demonstrate that at nanoscaled technology nodes for various connection lengths, mixed MWCNT (MMW) architectures perform better overall than MWCNT (MW).The results further show that, in comparison to alternative structures, the proposed structure for MMW3 is the optimal structure for interconnects for nano electronics IC design.

Electro Migration in Integrated Circuit Interconnects
An overview of physics-based modelling approaches for electro migration and their applications for integrated circuit interconnects has been published by Wen-Sheng Zhao et al. 5 The impact of electromigration on power grids and signal interconnects is examined in this research.The conventional method and physics-based modeling for electromigration are described.Then studies on how electromigration affects powers grids and signal interconnects are discussed in detail.Some of them focus on the comprehensiveness of modeling methodology, while others aim at the strategies for improving computation accuracy and speed and the strategies for accelerating/decelerating aging.Considering the importance of electromigration for circuit reliability, this paper is dedicated to providing a review on physics-based modeling methodologies on electromigration and their applications for integrated circuits interconnects.
In order to address reliability problems.M. Chandrakar et al. 6 give the equivalent RLGC modelling and performance study of air gap defected TSVs in comparison with defect free vertical connection at 7 nm technology.Peak noise has increased by 4.83%, getting closer to defect-free.The dependability of integrated circuits is becoming more and more challenged by migration-induced metal interconnect degradation, according to a work by S. Rothe et al. 7 In addition to increasing with each new technological node, the danger of failure due to migration is also restricting the shrinking of interconnecting architectures.Migration is progressively deteriorating signal and clock lines with DC lines, such as power supply networks.

Effect on Noise due to Interconnects
A paper by Tongguang Yu et al. 8 describes an effective hardware encryption method based on ferroelectric field-effect transistor z E-mail: susaritha.kumar@gmail.comECS Advances, 2023 2 031003 (FeFET) active interconnects with little complexity and overhead.According to the experimental study, the encryption probability for ISCAS85 benchmarks is 97.43% on average, with an increase of 2.24% delay for the most critical path/sum of 100 critical paths.In order to increase performance and reliability, Bhawana Kumari et al. 9 submitted a research on aspect ratio optimization of several intercalation doped MLGNR interconnects using a various approach.For any random nano interconnect system, more number of optimization method is presented to calculate the optimised aspect ratio while taking into account the collective effects of performance, reliability metrics, and noise.The experimental results showed that, compared with copper, performance increases added with technological advancement.A study by Tianzhuo Zhan et al. 10 describes how different bonding layers are used to change bonding at the Ru/SiO2 interface.Ru interconnects could eventually take the place of the recent Cu-based ones credit to thermal boundary resistance (TBR), which is used in the thermal management of VLSI circuits.In an article titled "New Improved Elmore Delay Estimation Model (RC) to Reduce Delay and Power Consumption in Interconnect Circuits," Himani Bhardwaj et al.In order to decrease the time constant of the interconnect circuits, an optimised Elmore delay computation was carried out for uniform and non-uniform wires.The proposed model is also theoretically approximated and confirmed.The designed -model is contrasted with a new upgraded RC model, which yields impressive results.The outcome demonstrates the amazing results, with an average uniform distribution achieving power improvements of 75.167% and delays of 74.714%.The variability of processinduced physical and geometrical characteristics in capacitively coupled Li-doped MLGNR interconnects operating in the sub threshold phase limits the transient analysis reported by Ramneek Sidhu et al. in their study at.Ref. 12 In order to investigate the performance characteristics of MLGNR interconnects, an analogous mean free path (MFP) that takes surface roughness scatterings into account is developed.Crosstalk-induced delay (XTID) increases with temperature or connection length while decreasing with dielectric thickness, fermi energy level, and width.It is important to note that the average error values for the obtained Vmax and Vtimeduration are not higher than 5% and 18%, respectively.
For the future generation of high performance integrated circuit (IC) design, Sandip Bhattacharya et al. 13 submitted a work on a sidecontact reduced graphene nano-ribbon (SC-RGNR) connection model to decrease crosstalk noise and latency.According to experimental study, the SC-RGNR interconnect, which is based on a higher MFP, exhibits less dynamic delay than the SC-GNR interconnect for both the STD and STAGG interconnect models under both the best-and worst-case switching conditions (SP5) (SP2).The dynamic latency of the SC-RGNR interconnect is 1.33-2.62less than the SC-GNR interconnect for the STD interconnect model with the worst-case switching situation (SP5).
Scaling Effect for rising Nanoscale Interconnect material is the topic of a research publication by Kai Zhao et al. 14 Future nodes in the M0 and M1 layers will have significant difficulties as a result of the resistivity of Cu interconnects increasing quickly with continuous reduction due to scatterings.For the purpose of analysing the  GNR,CNT [13][14][15] Ballistic transport Integration/contact resistance TSMC  behaviours of electron transport, a Boltzmann-transport-equationbased Monte Carlo simulator is created.This simulator includes all of the significant interconnect scattering processes.For Cu, Ru, Co, and W, the experimental results are obtained from bulk down to 10 nm interconnects.According to the findings, plasma excimer scattering, surface abrasion, and grain boundary scattering all play significant roles in nano-scale interconnects.Atomic Layer Deposited RuO2 Diffusion Barrier for Next Generation Ru-Interconnects is the topic of a paper by Y. Kim et al. 15 In order to better understand the performance of the ALD-RuO2 film's diffusion barrier, the physical and electrical characteristics of the Ru/ RuO2/Si multilayer are examined.The fact that the inter diffusion of Ru and Si is entirely suppressed by a thin (5 nm) ALD-RuO2 film is shown by the fact that the formation of Ru silicide does not take place without the conductivity degradation of the Ru/RuO2/Si multilayer with an raise in the annealing temperature up to 850 °C.The realistic development behaviour and diffusion barrier as a result Ru interconnects may encounter a diffusion barrier due to RuO2's performance.

Accurate Crosstalk Noise Modeling and Analysis of Non-Identical Lossy Interconnections Using Convex Optimization
Method is a research study by F. Zahedi et al. 16 that examines delay and crosstalk of lossy coupled interconnections in both like and non-like forms.Less than 1.03% and 1.19%, respectively, are the determined percentage errors of the suggested model with respect to ADS and HSPICE.The proposed approach also has a computational speed that is roughly twice as fast as ADS (Advanced Design System) and HSPICE.The calculated crosstalk percentage error of the proposed model with respect to ADS and HSPICE are less than 1.03% and 1.19%, respectively.In addition, the computational speed of the proposed method is about twice higher than ADS (Advanced Design System) and HSPICE.The suggested model is suitable for modelling intricate integrated circuit interconnections since it may be expanded to handle coupled lines.A report on the performance of sub threshold global interconnect with six alternative DG FinFET driver circuit designs, including FinFET SG, TGIG, THYBRID, TGSG, TPIGNSG, and TPSGNIG, was published by Walunj et al. in.Ref. 17 According to performance studies, the energy efficiency of the FinFET SG configuration at 225 mV supply voltage is 60.7, 0.8, 2.3, 37, and 40% higher than that of the TGIG, THYBRID, TGSG, TPIGNSG, and TPSGNIG, respectively.The effectiveness of traditional buffer insertion techniques for improving the performance of DG FinFET driven sub threshold global interconnects is also investigated in this work.According to the results, the unbuffered interconnect circuit powered by FinFET SG exhibits a 25% less spread in latency in the sub-threshold region than the buffered circuit study by S. Rothe et al. 18 is titled "Avoiding Migration-Induced Failure in IC Interconnects."Metal connection degradation brought on migratory migration is putting integrated circuit dependability in danger.Three on-chip connecting approaches that mitigate the performance deprivation difficulties brought on by continuous scaling of global interconnect parameters are described in a research study by Jayshree et al. 19 It has been suggested to use a dynamic adaptive (DyAD) routing method that relies on path congestion data.In comparison to point-to-point based interconnection (PTP-BI) and the advanced extensible interface (AXI4-BBI), which has been extensively explored in this study, the result observation demonstrates that network-on-chip based interconnection (NoC-BI) scales fairly effectively.
A paper on high-speed interconnects was presented by V. R. Kumbhare et al. 20 This article provides a thorough account of the development of interconnects while highlighting the major technological advances made over the previous 40 years.Signal transmission between chips on a printed circuit board and between devices on a chip is supported by interconnects (PCB).An integrated circuit's performance, functionality, reliability, efficiency, and general construction all depend on the architecture and design of its interconnect.Paper on Stability Analysis of Nanoscale Copper-Carbon Hybrid Interconnects was presented by B. Kumari et al. 21or upcoming VLSI circuit applications, the copper carbon (Cu-Carbon) hybrid connection is a brand-new and incredibly intriguing contender.According to the experimental findings, Cu-Carbon fusion is the most stable contender out of all the potential interconnects configurations, making it a promising interconnects option for next VLSI applications.
A work titled Beyond-Cu Intermediate-Length Interconnect Exploration for SRAM Application was published by Z. Pei et al. in Ref. 22. Results show that the EDP of the thick graphene wire cache is reduced by nearly 19% when compared to the Cu equivalent.It has been demonstrated that with a 2MB cache size at 7 nm, thick graphene wires can boost EDAP by up to 37%.
Software usage mentioned in this paper is HSPICE.HSPICE is an analog circuit simulator Capable of performing transient, steady state, and frequency domain analyses.Interconnects are modelled as a distributed RC line with n number of segments in a SPICE simulation.For the most precise delay estimation, infinite n and infinitesimal segment length are required.For a lengthy on-chip wire, a simple RC network model produces appreciable errors because of the high resistance and capacitance.

Interconnect Centric IC Design Flow
The three main steps in interconnect centric flow are depicted in the flow chart Fig. 5. Interconnect planning comes first, then interconnect synthesis, and interconnect layout comes last.Physical hierarchy creation, floor layout, and placements are all covered by interconnect planning.Interconnect synthesis is the process of choosing the best or nearly best interconnect topology, wire routing, buffer sizes and placements, wire width and spacing, etc to satisfy all nets' performance and signal reliability needs while adhering to routability and space restrictions.Interconnect layout uses a flexible and effective multi-layer general-area gridless routing technique to execute sophisticated routing to meet the intricate width and spacing requirements of all wires.Using these novel connecting materials can help decrease interconnect latency; however, it does not offer a permanent fix for the growing difference in performance between devices and interconnects.The interconnect performance is at most improved by one or two technology generations.

Conclusions
We have examined numerous interconnect modelling approaches that scholars have employed in this work.In order to fabricate ICs in the beyond nanometre range, interconnect is essential.To increase performance in terms of speed, power reduction, and noise reduction, various connectivity techniques are used.Size and speed have become more crucial an aspect of VLSI interconnects as a result of technological breakthroughs.As the technology advances to the deep below submicron level, the device's channel length shrinks to tens of nanometres.As a result, VLSI chips must have lengthy interconnects.Interconnects are regarded as the fundamental building piece that comes in a variety of sizes.They serve as a link between two or more number of blocks and have scalability issues that an IC designer must deal with during the design process.The importance of interconnect in VLSI circuits got even more significant as scaling increased.On the chip, it regulates all the significant electrical properties.With downsize technology, interconnects not only get faster to one another but also vary in size, which can have an immediate effect on the circuit parameters.The below table shows that different interconnects techniques and the performance, results obtained in experimental setups.ECS Advances, 2023 2 031003 (Continued).

s.no Various Interconnects
Methodology used and results obtained

MLGNR (multilayer graphene nano ribbon) interconnects
This approach is cost effective and will be extremely useful to industry for selection of aspect ratio of interconnects as it is a non-SPICE method and reduces fabrication iterations for achieving desired performance and reliability.

coupled Li-doped MLGNR interconnects
The average error values obtained are not greater than 5% and 18% for the obtained V max and V time-duration , respectively.7. side-contact reduced graphene nano-ribbon (SC-RGNR) interconnect Reduce crosstalk noise and delay for next generation high performance integrated circuit (IC) design.

Future aspects of the work
Performance metrics for SWCNT bundle and Optics with Cu/ low-k interconnects have been compared.There are still a lot of alternatives to traditional interconnects, though.To evaluate their suitability for upcoming high performance VLSI applications, performance comparison studies of interconnects with spintronics and plasmonics must be carried out with a variety of limitations.It is also crucial to compare the performance of those solutions with traditional Cu/low-k connection.In order to gain a better understanding of real-world situations, the performance evaluation work of CNTs and optical interconnects should be expanded to include more application-or architecture-specific limitations.ORCID M. Susaritha https://orcid.org/0000-0003-0547-0979

Table I .
The Developement of On-chip interconnects.
Comparison of different interconnects and their performance: (TBR) for thermal management.4.ferroelectric field-effect transistor (FeFET) active interconnectsshows an average encryption probability of 97.43% with an increase of 2.24%