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Integrated circuit (IC) technologies have so far successfully achieved Moore's assertion that the number of transistors on a microchip doubles every two years while the cost of computing is halved. Increasing the number of transistors on a chip provides lower per-component manufacturing cost and improves system performance. The semiconductor industry has seen several advancements in the FEOL, MOL and BEOL processes. As gate sizes are reduced, they lead to the development of new device architectures, new integration schemes, and ultimately new commercial products. Several technological evolutions have been taking place in making logic, DRAM and flash memory devices. For example, the NAND memory industry has undergone a revolution whereby planar structures have given way to 3D structures with 128 layers; and more are forecasted in the future. Transistor size has reduced with time to below 10 nm. The driving force behind this progress is the exposure technology known as photolithography where tremendous changes have taken place in the light sources as we have gone from g-line (436 nm), to i-line (365 nm), to excimer laser KrF (248 nm), to ArF (193 nm), to immersion ArF (equivalent to 134 nm) and now to EUV (13.5 nm). However, reducing the size of the transistor alone is not enough to increase performance, as with increased number of transistors one needs an increased amount of interconnection which cause longer delay times.
Chemical mechanical planarization (CMP), a polishing step that provides not only local planarity, but also global planarity needed to meet the stringent requirements of lithography has led the way toward integrating multilevel interconnects such that performance and speed for sub-10 nm devices are not compromised. CMP works via a combination of chemical reactions and mechanical action on a non-planar wafer surface. While initially developed for planarizing dielectric and metal layers, CMP is now the method of choice in a wide range of developmental efforts ranging from simple surface finishing of bulk substrates to planarizing composite film stacks over multi-level topography involving completely dissimilar materials. CMP continues to be one of the most innovative technologies that allows Moore's Law to continue and expand. The technical challenges of CMP have traditionally centered on removal rates and rate selectivities, dishing, erosion and wafer-level defects. However, these have been solved somewhat by developing new pads and slurries, coupled with advanced in-line monitoring and end-point detection. CMP process requirements have become more stringent for sub-10 nm devices. For instance, the migration from planar to 3D FINFET transistor structures for sub 10 nm devices has necessitated more than 15 CMP steps in FEOL and MOL processes, as such, CMP has now become the key process enabler for building transistors in FEOL and MOL rather than in BEOL planarization.
The most important consumables in CMP are the slurry, the pad, the conditioner and the retaining ring. In order to improve process performance, it is essential to understand the combined thermal, tribological, kinetic and micro-textural functions and attributes of these components from a fundamental (rather than the traditional trial-and-error) point of view. Enormous investments in research and development from industry, academia and various governmental entities are required to understand and optimize these consumables in terms of materials selection and process integration. Additionally, post-CMP cleaning consumables and processes have become one of the primary challenges in the semiconductor manufacturing for sub-10 nm devices. Since defects left on the wafer surface after CMP negatively impact yields, formulation of slurries and the materials of construction of pads, coupled with post-CMP cleaning chemistries and the physical features of PVA brushes, all combine to drive continuous innovations in our quest for improved performance. Both PVA brushes and cleaning chemistries are gaining more importance in particle removal, surface engineering, corrosion prevention and organics removal after CMP. As such, the effectiveness of CMP has to be judged not only by its performance, but also by the cleaning challenges that may generate. As the technology is moving toward smaller nodes, sub-10 nm defects have become serious contributors to reduced yield. This is especially true for cleaning after STI CMP using slurries with ceria nano-particles where removal of small residual ceria particles has proven to be a huge challenge. Other concerns have been caused by metallic ion defect formation from tungsten CMP, and corrosion issues during polishing of interconnects and barrier metals such as copper and cobalt. Modeling and validation of complex phenomena related to the tribological aspects of CMP, and how the pad, slurry, disc and retaining ring system, and fluid dynamics affect stick-slip events, has become more critical than ever.
It is of great interest to the CMP research community to exchange ideas from both academic studies and industrial perspectives. A paradigm shift in semiconductor manufacturing is inevitable and we believe that CMP needs to become more advanced in terms of hardware and software, and fundamental knowledge, to enable this shift. The market is migrating from single-driver technologies such as PCs and mobile phones, to a multi-driver space used for IoT, cloud, 5G, autonomous driving and AI. The number of these devices is relatively small today, but we expect things to grow fast thus necessitating active preparations and pre-positioning, on our part to make sure future CMP requirements are met.
As such, the main motivation of this focus issue has been to recognize the latest developments in CMP in light of sub 10-nm technologies. We believe this issue has met our objectives by delivering interesting findings to the community as many of the published papers have tackled critical aspects of existing problems as well as helped understand some of the fundamentals needed for future solutions. We would like to express our sincere gratitude to Dr. Jennifer Bardwell, Ms. Beth Schademann, and all ECS staff members who have worked tirelessly to create an environment where authors have been given sufficient time to submit their research findings as well as a fair platform for their works to be reviewed. We further appreciate all authors who have submitted their valuable research findings and we are immensely grateful to the reviewers for spending their valuable time to review and critique the works in a timely manner that has resulted in identifying and publishing the most deserving works. It is our sincere wish that this focus issue will serve as valuable reference material to the community for the continued successful journey that CMP has embarked on for the present and future device manufacturing.